KR920007124A - Manufacturing Method of Poly-Emitter Bipolar Transistor - Google Patents

Manufacturing Method of Poly-Emitter Bipolar Transistor Download PDF

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Publication number
KR920007124A
KR920007124A KR1019900013935A KR900013935A KR920007124A KR 920007124 A KR920007124 A KR 920007124A KR 1019900013935 A KR1019900013935 A KR 1019900013935A KR 900013935 A KR900013935 A KR 900013935A KR 920007124 A KR920007124 A KR 920007124A
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KR
South Korea
Prior art keywords
forming
oxide film
poly
etching
film
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Application number
KR1019900013935A
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Korean (ko)
Inventor
김규철
윤종밀
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019900013935A priority Critical patent/KR920007124A/en
Priority to FR9100086A priority patent/FR2666450A1/en
Priority to GB9100672A priority patent/GB2247780A/en
Priority to ITMI910068A priority patent/IT1245092B/en
Priority to DE4103594A priority patent/DE4103594A1/en
Priority to JP3253022A priority patent/JPH0629302A/en
Publication of KR920007124A publication Critical patent/KR920007124A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology

Abstract

내용 없음No content

Description

폴리 에미터 바이폴라 트랜지스터의 제조방법Manufacturing Method of Poly-Emitter Bipolar Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도(A) 내지 (N)는 본 발명의 낮은 에미터 저항을 갖는 바이폴라 트랜지스터의 제조공정도이다.1 (A) to (N) are manufacturing process diagrams of a bipolar transistor having a low emitter resistance of the present invention.

Claims (6)

실리콘기판(1)상에 매몰층(5)과 N형 에피택셜층(6)을 형성하는 공정과, 에피택셜층(6)상에 N형 불순물을 이온주입하여 바이폴라 트랜지스터가 형성될 영역인 N형 웰(10)을 형성하는 공정과, 통상의 산화공정으로 필드산화막(145)을 형성하는 공정과 콜렉터 영역(10)내에 N+확산층(17)을 형성하는 공정과, P형 불순물을 이온주입하여 베이스영역 형성용 이온 주입영역(20)을 형성하는 공정과, 산화막(21)을 도포하는 공정과, 상기 산화막(21)을 식각하여 접촉장(23)을 형성하는 공정과, 램프-업 도포법을 이용하여 폴리실리콘막(26)을 도포한 다음 패터닝하여 폴리패널(26')을 형성하는 공정과, 기판전면에 걸쳐 에미터 영역을 형성하기 위한 이온주입 공정과, 확산공정을 통하여 이온주입된 불순물을 동시에 확산시켜 베이스영역(27)과 에미터영역(28)을 형성하는 공정과, 산화막(29)과 BPSG막(30)을 형성하는 공정과, 상기 BPSG막(30)과 산화막(29,21)을 사진식각공정으로 순차 식각하여 금속 접촉구(31)를 형성하는 공정과, 금속막을 도포하고 패터닝하여 금속전극패턴(32)을 형성하는 공정으로 이루어지는 것을 특징으로 하는 폴리 에미터 바이폴라 트랜지스터의 제조방법.A process of forming the buried layer 5 and the N-type epitaxial layer 6 on the silicon substrate 1, and an N-type impurity ion implantation on the epitaxial layer 6 to form a bipolar transistor. A process of forming the type well 10, a process of forming the field oxide film 145 by a normal oxidation process, a process of forming the N + diffusion layer 17 in the collector region 10, and ion implantation of P-type impurities Forming the base region forming ion implantation region 20, applying the oxide film 21, etching the oxide film 21 to form a contact field 23, and a ramp-up coating method. Polysilicon film 26 is applied and patterned to form a polypanel 26 ', an ion implantation process for forming an emitter region over the entire surface of the substrate, and ion implantation through a diffusion process Simultaneously diffusing impurities to form the base region 27 and the emitter region 28; Forming an oxide film 29 and a BPSG film 30, sequentially etching the BPSG film 30 and the oxide films 29 and 21 by a photolithography process to form a metal contact hole 31; A method of manufacturing a poly-emitter bipolar transistor, comprising forming a metal electrode pattern (32) by applying and patterning a film. 제1항에 있어서, 접촉장(23)은 단결정 실리콘 기판과 폴리 패턴(26')을 접촉시키기 위한 것을 특징으로 하는 폴리 에미터 바이폴라 트랜지스터의 제조방법.A method according to claim 1, wherein the contact field (23) is for contacting the single crystal silicon substrate with the poly pattern (26 '). 제1항 또는 제2항에 있어서, 접촉장을 형성하는 공정은, 산화막(21)위에 감광성 물질(22)을 전면 도포하는 스텝과, 사진식각 공정으로 감광성 물질(22)을 식각하여 접촉장이 형성될 부위를 노출시키는 스텝과, 산화막(21)을 반응성이온 에칭법으로 식각하는 스텝과, 산화막(21)이 식각될 때 발생한 단결정 실리콘 기판의 손상된 부분(24)을 식각하는 스텝으로 이루어지는 것을 특징으로 하는 폴리 에미터 바이폴라 트랜지스터의 제조방법.The process for forming a contact field according to claim 1 or 2, wherein the contact field is formed by coating the entire surface of the photosensitive material 22 on the oxide film 21 and etching the photosensitive material 22 by a photolithography process. Exposing a portion to be etched, etching the oxide film 21 by a reactive ion etching method, and etching the damaged portion 24 of the single crystal silicon substrate generated when the oxide film 21 is etched. Method for producing a poly-emitter bipolar transistor. 제3항에 있어서, 단결정 실리콘 기판의 손상된 부분(24)을 플라즈마 방식으로 식각하는 것을 특징으로 하는 폴리 에미터 바이폴라 트랜지스터의 제조방법.4. A method according to claim 3, wherein the damaged portion (24) of the single crystal silicon substrate is etched in a plasma manner. 제1항에 있어서, 상기 폴리실리콘막(26)의 도포시, 웨이퍼를 도포튜브로 인입시킬때에는 도포튜브의 온도를 400℃정도의 저온으로 유지하고, 웨이퍼를 도포튜브로 완전히 인입시킨 후에는 서서히 온도를 정상적인 폴리실리콘의 도포 온도까지 상승시켜 폴리실리콘막(26)을 도포하는 것을 특징으로 하는 폴리 에미터 바이폴라 트랜지스터의 제조방법.The method of claim 1, wherein when the polysilicon film 26 is applied, the temperature of the coating tube is maintained at a low temperature of about 400 ° C. when the wafer is drawn into the coating tube, and gradually after the wafer is completely drawn into the coating tube. A method for producing a poly-emitter bipolar transistor, characterized in that the polysilicon film (26) is applied by raising the temperature to a normal coating temperature of polysilicon. 제1항에 있어서, 상기 폴리 패턴(26')이 에미터 영역의 확산 소오스가 되는 것을 특징으로 하는 폴리 에미터 바이폴라 트랜지스터의 제조방법.The method of claim 1, wherein the poly pattern (26 ') is a diffusion source of an emitter region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900013935A 1990-09-04 1990-09-04 Manufacturing Method of Poly-Emitter Bipolar Transistor KR920007124A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019900013935A KR920007124A (en) 1990-09-04 1990-09-04 Manufacturing Method of Poly-Emitter Bipolar Transistor
FR9100086A FR2666450A1 (en) 1990-09-04 1991-01-04 METHOD FOR MANUFACTURING A BIPOLAR TRANSISTOR WITH MULTIPLE TRANSMITTERS.
GB9100672A GB2247780A (en) 1990-09-04 1991-01-11 Fabricating a bipolar transistor
ITMI910068A IT1245092B (en) 1990-09-04 1991-01-11 PROCEDURE FOR MANUFACTURING A BIPOLAR TRANSISTOR WITH A POLYSILIC EMITTER
DE4103594A DE4103594A1 (en) 1990-09-04 1991-02-04 METHOD FOR PRODUCING BIPOLAR POLYEMITTER TRANSISTORS
JP3253022A JPH0629302A (en) 1990-09-04 1991-09-04 Manufacture of polysilicon-emitter bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900013935A KR920007124A (en) 1990-09-04 1990-09-04 Manufacturing Method of Poly-Emitter Bipolar Transistor

Publications (1)

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KR920007124A true KR920007124A (en) 1992-04-28

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Application Number Title Priority Date Filing Date
KR1019900013935A KR920007124A (en) 1990-09-04 1990-09-04 Manufacturing Method of Poly-Emitter Bipolar Transistor

Country Status (6)

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JP (1) JPH0629302A (en)
KR (1) KR920007124A (en)
DE (1) DE4103594A1 (en)
FR (1) FR2666450A1 (en)
GB (1) GB2247780A (en)
IT (1) IT1245092B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980054454A (en) * 1996-12-27 1998-09-25 김영환 Polysilicon Cone Formation Method
KR100382725B1 (en) * 2000-11-24 2003-05-09 삼성전자주식회사 Method of manufacturing semiconductor device in the clustered plasma apparatus

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DE4240738A1 (en) * 1992-12-03 1993-08-26 Siemens Ag Bipolar transistor prodn. for long service life - by forming base in surface of substrate, short term temp. adjusting, and forming emitter
JPH09500760A (en) * 1993-07-12 1997-01-21 ナショナル・セミコンダクター・コーポレイション Manufacturing process of semiconductor device with arsenic implanted emitter
US6093613A (en) * 1998-02-09 2000-07-25 Chartered Semiconductor Manufacturing, Ltd Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits
US7737049B2 (en) 2007-07-31 2010-06-15 Qimonda Ag Method for forming a structure on a substrate and device

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DE3165937D1 (en) * 1981-04-14 1984-10-18 Itt Ind Gmbh Deutsche Method of making an integrated planar transistor
JPS58501927A (en) * 1981-12-31 1983-11-10 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Method for reducing oxygen precipitation in silicon wafers
DE3304642A1 (en) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München INTEGRATED SEMICONDUCTOR CIRCUIT WITH BIPOLAR TRANSISTOR STRUCTURES AND METHOD FOR THEIR PRODUCTION
DE3580206D1 (en) * 1984-07-31 1990-11-29 Toshiba Kawasaki Kk BIPOLAR TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF.
KR880000483B1 (en) * 1985-08-05 1988-04-07 재단법인 한국전자통신 연구소 Fabricating semiconductor device with polysilicon protection layer during processing
US4693782A (en) * 1985-09-06 1987-09-15 Matsushita Electric Industrial Co., Ltd. Fabrication method of semiconductor device
EP0239825B1 (en) * 1986-03-21 1993-08-25 Siemens Aktiengesellschaft Method for producing a bipolar transistor structure for very high speed switchings
JPS6353928A (en) * 1986-08-22 1988-03-08 Anelva Corp Dry etching
US4839302A (en) * 1986-10-13 1989-06-13 Matsushita Electric Industrial Co., Ltd. Method for fabricating bipolar semiconductor device
JPS63182860A (en) * 1987-01-26 1988-07-28 Toshiba Corp Semiconductor device and manufacture thereof
JP2654011B2 (en) * 1987-03-31 1997-09-17 株式会社東芝 Method for manufacturing semiconductor device
JPH01157565A (en) * 1987-12-14 1989-06-20 Nec Corp Manufacture of bi-mos integrated circuit device
JPH0736389B2 (en) * 1988-11-10 1995-04-19 三菱電機株式会社 Method for forming electrode wiring of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980054454A (en) * 1996-12-27 1998-09-25 김영환 Polysilicon Cone Formation Method
KR100382725B1 (en) * 2000-11-24 2003-05-09 삼성전자주식회사 Method of manufacturing semiconductor device in the clustered plasma apparatus

Also Published As

Publication number Publication date
ITMI910068A1 (en) 1992-07-11
IT1245092B (en) 1994-09-13
FR2666450A1 (en) 1992-03-06
ITMI910068A0 (en) 1991-01-11
FR2666450B1 (en) 1993-02-26
JPH0629302A (en) 1994-02-04
DE4103594A1 (en) 1992-03-05
GB9100672D0 (en) 1991-02-27
GB2247780A (en) 1992-03-11

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