KR920015624A - Bipolar Transistor Manufacturing Method - Google Patents

Bipolar Transistor Manufacturing Method Download PDF

Info

Publication number
KR920015624A
KR920015624A KR1019910000289A KR910000289A KR920015624A KR 920015624 A KR920015624 A KR 920015624A KR 1019910000289 A KR1019910000289 A KR 1019910000289A KR 910000289 A KR910000289 A KR 910000289A KR 920015624 A KR920015624 A KR 920015624A
Authority
KR
South Korea
Prior art keywords
film
polysilicon film
type
forming
insulating oxide
Prior art date
Application number
KR1019910000289A
Other languages
Korean (ko)
Other versions
KR940000985B1 (en
Inventor
이경수
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000289A priority Critical patent/KR940000985B1/en
Publication of KR920015624A publication Critical patent/KR920015624A/en
Application granted granted Critical
Publication of KR940000985B1 publication Critical patent/KR940000985B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음No content

Description

바이폴라 트랜지스터 제조방법Bipolar Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제조공정단면도.1 is a cross-sectional view of the manufacturing process of the present invention.

Claims (1)

실리콘막기판위에 제1절연용산화막을 형성하고 그위에 n-형 폴리실리콘막과 제2절연용산화막을 차례로 형성하는 단계, 상기 n-형 폴리실리콘막을 어닐링하여 재결정화 시키는 단계, 포토/에치 공정을 실시하여 상기 n-형 폴리실리콘막과 제2절연용산화막의 불필요한 부분을 제거하는 단계, 전체적으로 n+형 폴리실리콘막을 증착하고 이를 에치하여 상기 한정된 n-형 폴리실리콘막과 제2절연용산화막의 측면에 소오스/드레인 영역으로서 측벽 폴리실리콘막을 형성하는 단계, 포토/이온주입 공정을 실시하여 상기 n-형 폴리실리콘막의 선택된 부분에 P-형 베이스 영역을 형성하는 단계, 상기 제2절연용산화막에 포토/에치 공정을 실시하여 베이스 금속 전극용 콘택트를 형성한후 이 콘택트를 통해 이온 주입을 실시하여 P-형 베이스 영역에 P+형 영역을 형성하는 단계, 베이스와 에미터 및 콜렉터 금속전극을 형성하는 단계가 차례로 포함됨을 특징으로 하는 바이폴라 트랜지스터 제조방법.Forming a first insulating oxide film on a silicon film substrate and sequentially forming an n - type polysilicon film and a second insulating oxide film thereon, annealing the n - type polysilicon film, and recrystallizing the photo / etch process Removing unnecessary portions of the n - type polysilicon film and the second insulating oxide film by depositing the n + type polysilicon film as a whole and etching the n - type polysilicon film and the second insulating oxide film Forming a sidewall polysilicon film as a source / drain region on a side of the film, performing a photo / ion implantation process to form a P - type base region on a selected portion of the n-type polysilicon film, and the second insulating oxide film A photo / etch process was performed on the base metal electrode to form a contact, and then ion implantation was performed through the contact to form a P + type zero in the P - type base region. And forming a base, and then forming a base, an emitter, and a collector metal electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000289A 1991-01-10 1991-01-10 Manufacturing method of bipolar transistor KR940000985B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000289A KR940000985B1 (en) 1991-01-10 1991-01-10 Manufacturing method of bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000289A KR940000985B1 (en) 1991-01-10 1991-01-10 Manufacturing method of bipolar transistor

Publications (2)

Publication Number Publication Date
KR920015624A true KR920015624A (en) 1992-08-27
KR940000985B1 KR940000985B1 (en) 1994-02-07

Family

ID=19309617

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000289A KR940000985B1 (en) 1991-01-10 1991-01-10 Manufacturing method of bipolar transistor

Country Status (1)

Country Link
KR (1) KR940000985B1 (en)

Also Published As

Publication number Publication date
KR940000985B1 (en) 1994-02-07

Similar Documents

Publication Publication Date Title
KR910013577A (en) Manufacturing Method of Semiconductor Device
KR890005884A (en) Manufacturing method of bipolar transistor
KR920015624A (en) Bipolar Transistor Manufacturing Method
KR920007124A (en) Manufacturing Method of Poly-Emitter Bipolar Transistor
KR970003939A (en) Method for manufacturing bipolar transistors of horizontal structure
KR890005885A (en) Manufacturing method of bipolar transistor
KR920015487A (en) Bipolar Transistor Manufacturing Method
KR920015594A (en) Manufacturing method of bipolar transistor
KR890005893A (en) Manufacturing Method of Semiconductor Device
KR920007229A (en) Bipolar Transistor Manufacturing Method
KR920007144A (en) Bipolar transistor manufacturing method using polycrystalline silicon
KR900019255A (en) Self-aligned bipolar transistor manufacturing method using nitride film
KR920015615A (en) Manufacturing method of bipolar transistor
KR900001030A (en) High voltage semiconductor device and manufacturing method thereof
KR920017270A (en) Fabrication method of bipolar transistor of Laterally Graded Emitter (LGE) structure using polycrystalline silicon side wall
KR930001478A (en) Structure and manufacturing method of Mospat
KR920001748A (en) Manufacturing method of bipolar transistor
KR920015606A (en) Base electrode formation method of bipolar transistor
KR920007231A (en) Manufacturing Method of Semiconductor Device
KR960005895A (en) Most transistor manufacturing method
KR920007211A (en) High speed bipolar transistor and method of manufacturing the same
KR930001480A (en) Structure and manufacturing method of trench buried LDD MOSFET
KR960019764A (en) Manufacturing method of self-aligned dipole transistor
KR930001467A (en) Manufacturing method of bipolar device
KR890017817A (en) High voltage semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050124

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee