KR920015487A - Bipolar Transistor Manufacturing Method - Google Patents

Bipolar Transistor Manufacturing Method Download PDF

Info

Publication number
KR920015487A
KR920015487A KR1019910000567A KR910000567A KR920015487A KR 920015487 A KR920015487 A KR 920015487A KR 1019910000567 A KR1019910000567 A KR 1019910000567A KR 910000567 A KR910000567 A KR 910000567A KR 920015487 A KR920015487 A KR 920015487A
Authority
KR
South Korea
Prior art keywords
forming
region
trench
film
photo
Prior art date
Application number
KR1019910000567A
Other languages
Korean (ko)
Other versions
KR930010674B1 (en
Inventor
이경수
손효헌
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000567A priority Critical patent/KR930010674B1/en
Publication of KR920015487A publication Critical patent/KR920015487A/en
Application granted granted Critical
Publication of KR930010674B1 publication Critical patent/KR930010674B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음No content

Description

바이폴라 트랜지스터 제조방법Bipolar Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본발명의 제조 공정 단면도.2 is a cross-sectional view of the manufacturing process of the present invention.

Claims (2)

기판에 이온주입을 실시하여 고농도 베이스접촉영역을 형성하고 그 위에 절연막을 형성한 다음 포토/에치공정을 실시하여 격리 영역형성용 트렌치를 형성하는 단계, 상기 트렌치에 채널스톱이온을 주입하고 트렌치내에 산화막을 채워 결리영역을 완성하는 단계, 상기 산화막위에 포토/에치공정을 실시하여 고농도 베이스 접촉 영역상의 소정폭 만큼을 제거하고 이위에 소정폭의 폴리실리콘막을 형성하는 단계, 포도/이온주입 공정을 상기 폴리실리콘막위에 실시하여 에미터 영역과 베이스 영역과 콜렉터 영역 및 콜렉터 접촉영역을 형성하는 단계, 전체적으로 절연막을 형성하고 이위에 포토/에치 공정을 실시하여 각 금속 전극 콘택트를 형성한 다음 이 콘텍트들에 금속을 증착하여 에미터와 베이스 및 콜렉터 금속전극을 형성하는 단계가 차례로 포함됨을 특징으로 하는 바이폴라 트랜지스터 제조방법.Implanting ions into the substrate to form a highly concentrated base contact region, forming an insulating film thereon, and then performing a photo / etch process to form an isolation region forming trench; implanting channel stop ions into the trench and oxidizing an oxide film in the trench Completing the isolation region by filling a gap, performing a photo / etch process on the oxide film to remove a predetermined width on a high concentration base contact region, and forming a polysilicon film having a predetermined width thereon; Forming an emitter region, a base region, a collector region, and a collector contact region on a silicon film, forming an insulating film as a whole, and performing a photo / etch process thereon to form respective metal electrode contacts, and then forming a metal on these contacts. Deposition to form the emitter and base and collector metal electrodes That the method for producing the bipolar transistor according to claim. 제1항에 있어서, 상기 트렌치내에 산화막대신 폴리실리콘막을 채워 격리영역을 형성하는 것을 특징으로 하는 바이폴라 트랜지스터 제조방법.The method of claim 1, wherein an isolation region is formed by filling a polysilicon film instead of an oxide film in the trench. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000567A 1991-01-15 1991-01-15 Manufacturing method of bipolar transistor KR930010674B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000567A KR930010674B1 (en) 1991-01-15 1991-01-15 Manufacturing method of bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000567A KR930010674B1 (en) 1991-01-15 1991-01-15 Manufacturing method of bipolar transistor

Publications (2)

Publication Number Publication Date
KR920015487A true KR920015487A (en) 1992-08-27
KR930010674B1 KR930010674B1 (en) 1993-11-05

Family

ID=19309835

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000567A KR930010674B1 (en) 1991-01-15 1991-01-15 Manufacturing method of bipolar transistor

Country Status (1)

Country Link
KR (1) KR930010674B1 (en)

Also Published As

Publication number Publication date
KR930010674B1 (en) 1993-11-05

Similar Documents

Publication Publication Date Title
KR930005257A (en) Thin film field effect element and its manufacturing method
KR960002690A (en) Method for manufacturing a semiconductor device having a low resistance gate electrode
KR910013577A (en) Manufacturing Method of Semiconductor Device
KR890013796A (en) Semiconductor device and manufacturing method
KR850700182A (en) Manufacturing Method of Metal Oxide Semiconductor Device
KR880005690A (en) BiCMOS manufacturing method using selective epitaxial layer
KR920015487A (en) Bipolar Transistor Manufacturing Method
KR920007124A (en) Manufacturing Method of Poly-Emitter Bipolar Transistor
KR970003939A (en) Method for manufacturing bipolar transistors of horizontal structure
KR0152897B1 (en) Bipolar device and method of manufacturing the same
JPH02133929A (en) Semiconductor device and its manufacture
KR920015624A (en) Bipolar Transistor Manufacturing Method
KR920015594A (en) Manufacturing method of bipolar transistor
KR0142875B1 (en) Fabrication method of mosfet
KR890005885A (en) Manufacturing method of bipolar transistor
KR920007098A (en) Method of manufacturing insulated gate field effect transistor
KR930003296A (en) Drain leakage current prevention MISFET and its manufacturing method
KR970013108A (en) Method of manufacturing a horizontal bipolar transistor
KR920007144A (en) Bipolar transistor manufacturing method using polycrystalline silicon
KR930015081A (en) Shallow Bonded MOSFET Manufacturing Method
KR950024332A (en) Manufacturing method of semiconductor device
KR970053071A (en) Manufacturing method of MOSFET
KR960009165A (en) Manufacturing method of BiCMOS semiconductor device with improved reliability
KR970024283A (en) MOS transistor and manufacturing method thereof
JPH0215673A (en) Semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021018

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee