KR890005893A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR890005893A
KR890005893A KR1019880011337A KR880011337A KR890005893A KR 890005893 A KR890005893 A KR 890005893A KR 1019880011337 A KR1019880011337 A KR 1019880011337A KR 880011337 A KR880011337 A KR 880011337A KR 890005893 A KR890005893 A KR 890005893A
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KR
South Korea
Prior art keywords
manufacturing
semiconductor substrate
semiconductor device
forming
insulating film
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KR1019880011337A
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Korean (ko)
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KR920004913B1 (en
Inventor
마사아키 기누가와
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR890005893A publication Critical patent/KR890005893A/en
Application granted granted Critical
Publication of KR920004913B1 publication Critical patent/KR920004913B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음No content

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 MOS 트랜지스터의 게이트 길이와 게이트 문턱전압의 상관관계도.1 is a correlation diagram of a gate length and a gate threshold voltage of a MOS transistor.

제2도(A)∼제 2 도(D)는 본 발명에 따른 반도체 장치의 제조공정을 나타낸 단면도.2A to 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.

제3도는 본 발명에 다른 실시예에 따른 도랑굴착형 캐패시터의 제조공정중 한 공정을 나타낸 단면도.Figure 3 is a cross-sectional view showing one step of the manufacturing process of the trench excavation capacitor according to another embodiment of the present invention.

Claims (9)

반도체 기판(1)의 전면에 불순물이 확산되기 어려운 절연막(7,34)을 형성하는 공정과, 이 절연막(7,34)의 일부를 제거하는 공정, 상기 반도체 기판(1)의 위와 상기 절연막(7,34)의 위에 불순물 확산원으로 되는 금속박막(8.35)을 형성하는 공정 및, 상기 반도체 기판(1)을 열어닐링처리하는 공정을 구비한 반도체 장치의 제조방법.A step of forming insulating films 7 and 34 in which impurities are hardly diffused on the entire surface of the semiconductor substrate 1, a step of removing a part of the insulating films 7 and 34, a top of the semiconductor substrate 1 and the insulating film ( And a step of forming a metal thin film (8.35) serving as an impurity diffusion source on 7,34) and a step of open annealing the semiconductor substrate (1). 제 1 항에 있어서, 상기 절연막(7)을 형성하는 공정이 MOS 트랜지스터의 게이트 전극(5)을 형성한후에 시행되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the insulating film (7) is performed after forming the gate electrode (5) of the MOS transistor. 제 1 항에 있어서, 상기 절연막(7)의 일부를 제거하는 공정이 MOS 트랜지스터의 게이트 전극(5)을 형성한후 형성되는 상기 MOS 트랜지스터의 소오스 영역 형성예정부 및 드레인 영역 형성예정부의 반도체 기판(1)부분을 노출시키는 공정인 것을 특징으로 하는 반도체 장치의 제조방법.The semiconductor substrate according to claim 1, wherein the step of removing a part of the insulating film 7 is performed after forming the gate electrode 5 of the MOS transistor. 1) A method of manufacturing a semiconductor device, characterized in that the step of exposing portions. 제 1 항에 있어서, 상기 금속박막(8,35)을 형성하는 공정이 진공증착법에 의한 것임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the metal thin films (8,35) is by vacuum deposition. 제 1 항에 있어서, 상기 반도체 기판(1)에 형성된 도랑(32)의 내표면상 및 상기 반도체 기판(1)상의 절연막(34)상에 진공증착법으로 상기 금속박막(35)을 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.2. The metal thin film 35 according to claim 1, wherein the metal thin film 35 is formed on the inner surface of the trench 32 formed in the semiconductor substrate 1 and on the insulating film 34 on the semiconductor substrate 1 by vacuum deposition. A manufacturing method of a semiconductor device. 제 1 항에 있어서, 상기 반도체 기판(1)을 열어닐링처리 하는 공정이 MOS 트랜지스터의 소오스 영역형성 예정부 및 드레인 영역형성 예정부의 반도체 기판(1)으로 불순물을 확산시키는 공정인 것을 특징으로 하는 반도체 장치의 제조방법.2. The semiconductor according to claim 1, wherein the step of open annealing the semiconductor substrate 1 is a step of diffusing impurities into the semiconductor substrate 1 of the source region forming portion and the drain region forming portion of the MOS transistor. Method of manufacturing the device. 제 1 항에 있어서, 상기 절연막(7,34)을 실리콘산화막으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said insulating film (7,34) is formed of a silicon oxide film. 제 1 항에 있어서, 상기 절연막(7,34)을 실리콘질화막으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.A method according to claim 1, wherein the insulating film (7, 34) is formed of a silicon nitride film. 제 1 항에 있어서, 상기 금속박막(8,35)을 금속보론박막으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the metal thin film (8,35) is formed of a metal boron thin film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880011337A 1987-09-04 1988-09-02 Manufacturing method of semiconductor device KR920004913B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP87-221411 1987-09-04
JP62-221411 1987-09-04
JP62221411A JPH0644559B2 (en) 1987-09-04 1987-09-04 Method for manufacturing semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
KR890005893A true KR890005893A (en) 1989-05-17
KR920004913B1 KR920004913B1 (en) 1992-06-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880011337A KR920004913B1 (en) 1987-09-04 1988-09-02 Manufacturing method of semiconductor device

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EP (1) EP0305977A3 (en)
JP (1) JPH0644559B2 (en)
KR (1) KR920004913B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100404169B1 (en) * 1996-01-26 2004-07-01 엘지전자 주식회사 Method for fabricating semiconductor device to reduce fabricating cost and increase yield

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086016A (en) * 1990-10-31 1992-02-04 International Business Machines Corporation Method of making semiconductor device contact including transition metal-compound dopant source
US5605861A (en) * 1995-05-05 1997-02-25 Texas Instruments Incorporated Thin polysilicon doping by diffusion from a doped silicon dioxide film

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522165A (en) * 1975-06-23 1977-01-08 Mitsubishi Electric Corp Method of thermally diffusing selectively aluminum of semiconductor su bstrate
GB2130793B (en) * 1982-11-22 1986-09-03 Gen Electric Co Plc Forming a doped region in a semiconductor body
JPS60138974A (en) * 1983-12-27 1985-07-23 Fuji Electric Corp Res & Dev Ltd Manufacture of insulated gate type field effect transistor
US4569701A (en) * 1984-04-05 1986-02-11 At&T Bell Laboratories Technique for doping from a polysilicon transfer layer
JPS61156858A (en) * 1984-12-28 1986-07-16 Nec Corp Manufacture of cmos fet
JPH0722138B2 (en) * 1985-09-30 1995-03-08 株式会社東芝 Method for manufacturing semiconductor device
JPS62266829A (en) * 1986-05-14 1987-11-19 Sharp Corp Formation of shallow junction layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100404169B1 (en) * 1996-01-26 2004-07-01 엘지전자 주식회사 Method for fabricating semiconductor device to reduce fabricating cost and increase yield

Also Published As

Publication number Publication date
EP0305977A2 (en) 1989-03-08
EP0305977A3 (en) 1990-11-22
JPH0644559B2 (en) 1994-06-08
KR920004913B1 (en) 1992-06-22
JPS6464315A (en) 1989-03-10

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