JPS61156858A - Manufacture of cmos fet - Google Patents

Abstract

PURPOSE:To obtain the titled device in which elements are refined by a simple process, by a method wherein silica containing a required concentration of impurity is applied to the substrate and heat-treated. CONSTITUTION:A P-well 2 is formed in the N-type Si substrate 1, and an oxide film 3 for element isolation is grown; then, a gate oxide film 4 and a gate electrode poly Si 5 are grown. Next, the substrate surface 6 of the source and drain is exposed by etching the poly Si 5 and the gate oxide film 4, and silica 7 containing an N-type impurity at a concentration of 1X10<20>cm<-3> or more is applied. The silica 7 is selectively removed by excluding the NMOS region, and the whole is coated with a silica 8 containing a P-type impurity at a concentration of 1X10<20>cm<-3> or more. On irradiation with e.g. halogen lamp light and heat treatment at 900 deg.C or more for 90sec or less, the source-drain donor diffused layers 9 of the NMOSFET and its source-drain acceptor diffused layers 10 are formed out of the silicas 7 and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a complementary MOS field effect transistor.

(Prior art) Conventionally, when manufacturing a CMOS type O8 transistor, a P-channel MOS transistor (PMOS) is formed after forming a gate electrode.
The donor and acceptor regions were masked and implanted with donor and acceptor ions, respectively.

(Problems to be Solved by the Invention) However, this requires two 7-otoline graph steps to selectively mask the PMOS region or the NMOS region. Furthermore, when a photoresist is used as a mask material during ion implantation, there is a problem in that gas is generated from the photoresist during ion implantation and the degree of vacuum in the ion implantation apparatus is deteriorated. Furthermore, if M or the like is used instead of photoresist as a mask material, it is disadvantageous in terms of device miniaturization. Furthermore, from the point of view of device miniaturization, it is necessary to make the source/drain impurity diffusion layers shallow. Therefore, various methods have been proposed in which the annealing time is shortened and the annealing temperature is lowered so that the impurities are not re-diffused during the annealing after ion implantation. However, with this method, it is impossible to form a diffusion layer shallower than that during ion implantation. Further, even if the implantation energy during ion implantation is reduced, there is a problem in that there is a limit in terms of the capacity of the ion implanter and the productivity.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, realize a shallow diffusion layer through a simpler process, and create a complementary MOS suitable for device miniaturization.
An object of the present invention is to provide a method for manufacturing a field effect transistor.

(Means for Solving the Problems) A method for manufacturing a complementary MOS field effect transistor of the present invention includes a step of forming a well of an opposite conductivity type in a semiconductor substrate of one conductivity type, and a step of forming a well of an opposite conductivity type on a semiconductor substrate of one conductivity type, and a step of forming a gate electrode on the surface of the semiconductor substrate; a step of exposing the surface of the well and regions of the semiconductor substrate other than the well that will become the source/drain; a step of forming a first insulating film containing impurities of one conductivity type (or an opposite conductivity type); and a step of selectively removing the first insulating film so as to leave it only on the well (or other than the well). , a step of forming a second insulating film containing impurities of opposite conductivity type (or one conductivity type) at a concentration of 1×10 cm or more over the entire surface, and heat treatment at 900° C. or higher for 90 seconds or less to form source/drain regions on the semiconductor substrate. The method includes a step of forming a region.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIGS. 1(a) to 1(b) are cross-sectional views shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in Figure 1 (JL), the impurity concentration is 1×1.
o N-type silicon substrate 1 of about 15C-'''S, NM
The surface impurity concentration is 1× only in the area where the OSFET is formed.
A P well 2 of approximately 10 cm to 1×10 cm is formed.

Next, as shown in Figure 1), a thick oxide film 3 for element isolation is grown by selective oxidation, etc., several hundred layers of gate oxide film 4, and several thousand layers of polysilicon 5 for gate electrodes. do.

Next, as shown in FIG. 1(e), after patterning a gate pattern by photolithography, the polysilicon 5 and gate oxide film 4 are removed by etching to expose the substrate surface 6 of the source and drain.

Next, as shown in FIG. 1(d), for example, a concentration of 1×lQ
Silica 7 containing an N-type impurity of at least 1 cm 2 , preferably about 1×10 cm 2 , is coated.

Next, as shown in FIG. 1(e), all the silica 7 except for the NMOS region is selectively removed by photophosphorography.

Next, as shown in FIG. 1(f), for example, the concentration I is applied to the entire surface.
Silica 8 containing P-type impurities is preferably coated to a thickness of about 1×10 cm or more.

Next, as shown in FIG.
N-type impurities and P impurities are removed from silica 7 and 8 by heat treatment for 0 seconds or less, preferably at 1000°C for about 10 seconds.
Type impurities are diffused into the substrate 1 to form the source/drain/donor diffusion layer 9 of the NMOSFET and the source/drain/acceptor diffusion layer 10 of the PMOSFET.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

The steps shown in FIG. 1(a) to FIG. 1(e) are performed in the same manner as in the first embodiment. After forming the gate electrode as shown in FIG. 1(e), as shown in FIG.
×i o20cm-3 or more, preferably 0"cm-
Apply silica 21 containing P-type impurity of about 3 to
It is selectively removed except for the S region. Next, for example, the concentration I
X10cm or more, preferably 1x1022cm
If silica 22 containing N-type impurities is applied and heat treated, the same results as in the first embodiment can be obtained.

In the first and second examples above, silica was applied, but
It goes without saying that similar results can be obtained even if an insulating film containing impurities is formed by a method such as vapor phase growth. Further, in the first and second embodiments, irradiation with tungsten halogen lamp light was used as a method for heat treatment at 900° C. or higher and for 90 seconds or less, but the same results can of course be obtained by other methods.

(Effects of the Invention) As explained above, according to the present invention, it is possible to form a shallower drain impurity diffusion layer in a simpler process than in the past, and to manufacture a complementary MOS field effect transistor suitable for device miniaturization. be able to.

[Brief explanation of the drawing]

FIGS. 1(a) to (g) are cross-sectional views showing the process order for explaining the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the second embodiment of the present invention.
FIG. 1...-Nfi silicon substrate, 2...P
well, 3... oxide film, 4... gate oxide film, 5... polysilicon, 6-...
Surface, 7, 8...7 Rica, 9...N-type impurity diffusion layer, 10...P-type impurity diffusion layer, 2
1.22...Silica. 1 (Representative Patent Attorney Uchihara CIl 1 line 1 figure

Claims (2)

[Claims] (1) A step of forming a well of an opposite conductivity type on a semiconductor substrate of one conductivity type, a step of forming a gate electrode on the surface of the well and a surface of the semiconductor substrate other than the well, and a step of forming the well and the semiconductor substrate other than the well. A step of exposing the surface of the region that will become the source/drain on the surface, and a step of exposing the surface of the region that will become the source/drain; a step of forming a first insulating film, a step of selectively removing the first insulating film so as to leave it only on the well (or other than the well), and a step of selectively removing the first insulating film so as to leave it only on the well (or other than the well); A second containing impurities of three or more opposite conductivity types (or one conductivity type)
A complementary MO comprising the steps of: forming an insulating film; and forming source/drain regions on the semiconductor substrate by performing heat treatment at 900° C. or higher for 90 seconds or less.
A method for manufacturing an S field effect transistor. (2) A method for manufacturing a complementary MOS field effect transistor according to claim (1), wherein the heat treatment is performed by light irradiation.