KR970053910A - MOS transistor - Google Patents

MOS transistor Download PDF

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Publication number
KR970053910A
KR970053910A KR1019950065966A KR19950065966A KR970053910A KR 970053910 A KR970053910 A KR 970053910A KR 1019950065966 A KR1019950065966 A KR 1019950065966A KR 19950065966 A KR19950065966 A KR 19950065966A KR 970053910 A KR970053910 A KR 970053910A
Authority
KR
South Korea
Prior art keywords
gate electrode
spacer
mos transistor
sidewalls
stacked
Prior art date
Application number
KR1019950065966A
Other languages
Korean (ko)
Inventor
안경호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950065966A priority Critical patent/KR970053910A/en
Publication of KR970053910A publication Critical patent/KR970053910A/en

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

샐리사이드 공정으로 제조된 모스 트랜지스터에 대해 기재되어 있다. 이는 다결정 실리콘층과 금속 실리사이드층이 적층된 구조의 게이트 전극, 상기 게이트 전극 측벽에 형성된 제1스페이서, 상기 제1스페이서와 게이트 전극 사이에 형성된 제2스페이서를 구비한다. 따라서, 게이트 전극과 소오스/드레인과의 단락을 방지할 수 있다.A MOS transistor made by the salicide process is described. The gate electrode includes a gate electrode having a structure in which a polycrystalline silicon layer and a metal silicide layer are stacked, a first spacer formed on sidewalls of the gate electrode, and a second spacer formed between the first spacer and the gate electrode. Therefore, a short circuit between the gate electrode and the source / drain can be prevented.

Description

모스 트랜지스터MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 샐리사이드 공정에 따라 제조된 모스 트랜지스터를 도시한 단면도이다.2 is a cross-sectional view of a MOS transistor manufactured according to the salicide process of the present invention.

Claims (3)

다결정 실리콘층과 금속 실리사이드층이 적층된 구조의 게이트 전극; 상기 게이트 전극 측벽에 형성된 제1스페이서; 상기 제1스페이서와 게이트 전극 사이에 형성된 제2스페이서를 구비하는 것을 특징으로 하는 모스 트랜지스터.A gate electrode having a structure in which a polycrystalline silicon layer and a metal silicide layer are stacked; A first spacer formed on sidewalls of the gate electrode; And a second spacer formed between the first spacer and the gate electrode. 제1항에 있어서, 상기 제1스페이서는 질화물로, 상기 제2스페이서는 산화물로 형성된 것을 특징으로 하는 모스 트랜지스터.The MOS transistor according to claim 1, wherein the first spacer is formed of nitride and the second spacer is formed of oxide. 제1항에 있어서, 상기 제1 및 제2스페이서는 모두 산화물로 형성된 것을 특징으로 하는 모스 트랜지스터.The MOS transistor of claim 1, wherein both of the first and second spacers are formed of an oxide. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065966A 1995-12-29 1995-12-29 MOS transistor KR970053910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065966A KR970053910A (en) 1995-12-29 1995-12-29 MOS transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065966A KR970053910A (en) 1995-12-29 1995-12-29 MOS transistor

Publications (1)

Publication Number Publication Date
KR970053910A true KR970053910A (en) 1997-07-31

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ID=66622796

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065966A KR970053910A (en) 1995-12-29 1995-12-29 MOS transistor

Country Status (1)

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KR (1) KR970053910A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460074B1 (en) * 1998-12-11 2005-02-02 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460074B1 (en) * 1998-12-11 2005-02-02 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

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