KR970024156A - Step improvement method between cell area and peripheral circuit area - Google Patents

Step improvement method between cell area and peripheral circuit area Download PDF

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Publication number
KR970024156A
KR970024156A KR1019950039015A KR19950039015A KR970024156A KR 970024156 A KR970024156 A KR 970024156A KR 1019950039015 A KR1019950039015 A KR 1019950039015A KR 19950039015 A KR19950039015 A KR 19950039015A KR 970024156 A KR970024156 A KR 970024156A
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South Korea
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type
region
forming
drain
source
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KR1019950039015A
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Korean (ko)
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남인호
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김광호
삼성전자 주식회사
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Priority to KR1019950039015A priority Critical patent/KR970024156A/en
Publication of KR970024156A publication Critical patent/KR970024156A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

셀 영역과 주변회로 영역 사이의 단차를 개선하는 방법에 대해 기재되어 있다. 이는 셀 영역, 제1형 모스들이 형성되는 제1영역 및 제2형 모스들이 형성될 제1영역의 반도체기판 상에 셀 트랜지스터들, 제1형 모스들 및 제2형 모스들의 게이트 전극을 형성하는 단계, 게이트 전극8이 형성되어 있는 반도체기판 전면에 제1절연막을 형성하는 단계, 셀 영역의 제1절연막을 이방성식각함으로써 게이트 전극의 측벽에 제1스페이서를 형성하는 단계, 셀 영역에 불순물 이온을 주입함으로써 셀 트랜지스터의 소오스/드레인을 형성하는 단계, 셀 트랜지스터의 소오스/드레인에 접속되는 소오스/드레인 전극을 형성하는 단계, 제1영역의 제1절연막을 이방성식각함으로서 제1형 모스의 게이트 전극의 측벽에 제2스페이서를 형성하는 단계, 제1영역에 제1도전형의 불순물 이온을 주입함으로써 제1형 모스의 소오스/드레인을 형성하는 단계, 제2영역의 제1절연막을 이방성식각함으로써 제2형 모스의 게이트 전극의 측벽에 제3스페이서를 형성하는 단계 및 제2영역에 제2도전형의 불순물 이온을 주입함으로써 제2형 모스의 소오스/드레인을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of improving the step between the cell region and the peripheral circuit region is described. This forms a gate electrode of the cell transistors, the first type MOSs and the second type MOSs on the semiconductor substrate of the cell region, the first region in which the first type MOSs are formed and the first region in which the second type MOSs are formed. Forming a first spacer on the entire surface of the semiconductor substrate on which the gate electrode 8 is formed; forming a first spacer on the sidewall of the gate electrode by anisotropically etching the first insulating layer on the cell region; Forming a source / drain of the cell transistor by implanting, forming a source / drain electrode connected to the source / drain of the cell transistor, and anisotropically etching the first insulating film of the first region to Forming a second spacer on the sidewall, forming a source / drain of the first type MOS by implanting impurity ions of the first conductivity type into the first region, and a second region Forming a third spacer on the sidewall of the gate electrode of the second type MOS by anisotropically etching the first insulating film and forming a source / drain of the second type MOS by implanting impurity ions of the second conductivity type into the second region. Characterized in that it comprises a step.

Description

셀영역과 주변회로 영역 사이의 단차 개선방법Step improvement method between cell area and peripheral circuit area

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2G도는 본 발명에 의한 셀 영역과 주변회로 영역 사이의 단차개선방법을 설명하기 위해 도시한 단면도들이다.2A to 2G are cross-sectional views illustrating a method for improving a step between a cell region and a peripheral circuit region according to the present invention.

Claims (4)

셀 영역, 제1형 모스들이 형성되는 제1영역 및 제2형 모스들이 형성될 제1영역의 반도체기판 상에 셀 트랜지스터들, 제1형 모스들 및 제2형 모스들의 게이트 전극을 형성하는 제1단계; 상기 게이트 전극이 형성되어 있는 반도체기판 전면에 제1절연막을 형성하는 제2 단계; 상기 셀 영역의 제1절연막을 이방성식각함으로써 상기 게이트 전극의 측벽에 제1 스페이서를 형성하는 제3단계; 상기 셀 영역에 불순물 이온을 주입함으로써 셀 트랜지스터의 소오스/드레인을 형성하는 제4단계; 셀 트랜지스터의 소오스/드레인에 접속되는 소오스/드레인 전극을 형성하는 제5단계; 상기 제1영역의 제1절연막을 이방성식각함으로서 제1형 모스의 게이트 전극의 측벽에 제2스페이서를 형성하는 제6단계; 상기 제1영역에 제1도전형의 불순물 이온을 주입함으로써 제1형 모스의 소오스드레인을 형성하는 제7단계; 상기 제2영역의 제1절연막을 이방성식각함으로써 제2형 모스의 게이트 전극의 측벽에 제3스페이서를 형성하는 제8단계; 및 상기 제2영역에 제2도전형의 불순물 이온을 주입함으로써 제2형 모스의 소오스/드레인을 형성하는 제9단계를 포함하는 것을 특징으로 하는 셀 영역과 주변회로 영역 사이의 단차개선방법.Forming gate electrodes of the cell transistors, the first type MOSs, and the second type MOSs on the semiconductor substrate in the cell region, the first region in which the first type Morse is formed, and the first region in which the second type Morse is formed. Stage 1; Forming a first insulating layer on the entire surface of the semiconductor substrate on which the gate electrode is formed; A third step of forming a first spacer on a sidewall of the gate electrode by anisotropically etching the first insulating layer in the cell region; A fourth step of forming a source / drain of a cell transistor by implanting impurity ions into the cell region; A fifth step of forming a source / drain electrode connected to the source / drain of the cell transistor; Forming a second spacer on the sidewall of the gate electrode of the first type MOS by anisotropically etching the first insulating layer in the first region; A seventh step of forming a source drain of the first type MOS by implanting impurity ions of a first conductivity type into the first region; An eighth step of forming a third spacer on a sidewall of the gate electrode of the second type MOS by anisotropically etching the first insulating layer in the second region; And a ninth step of forming a source / drain of the second type Morse by implanting impurity ions of the second conductivity type into the second area. 제1항에 있어서, 상기 제1절연막은 산화물로 형성되는 것을 특징으로 하는 셀 영역과 주변회로 영역 사이의 단차개선방법.The method of claim 1, wherein the first insulating layer is formed of an oxide. 제1항에 있어서, 상기 셀 트랜지스터의 소오스/드레인은 실리콘으로 형성되는 것을 특징으로 하는 셀 영역과 주변회로 영역 사이의 단차개선방법.The method of claim 1, wherein the source / drain of the cell transistor is formed of silicon. 제1항에 있어서, 상기 제1형 모스는 NMOS이고, 상기 제2형 모스는 PMOS이며, 상기 제1도전형의 불순물 이온은 N형 불순물이온이고, 상기 제2도전형의 불순물이온은 P형 불순물 이온인 것을 특징으로 하는 셀 영역과 주변회로 영역 사이의 단차개선방법.The method of claim 1, wherein the first type of moss is NMOS, the second type of moss is PMOS, the impurity ions of the first conductivity type are N-type impurity ions, and the impurity ions of the second conductivity type are P-type. A method for improving a step between a cell region and a peripheral circuit region, characterized in that the impurity ion. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950039015A 1995-10-31 1995-10-31 Step improvement method between cell area and peripheral circuit area KR970024156A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100398571B1 (en) * 2001-04-24 2003-09-19 주식회사 하이닉스반도체 Method of manufacturing merged memory and logic device
KR100465857B1 (en) * 1997-12-30 2005-05-18 주식회사 하이닉스반도체 Semiconductor device manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465857B1 (en) * 1997-12-30 2005-05-18 주식회사 하이닉스반도체 Semiconductor device manufacturing method
KR100398571B1 (en) * 2001-04-24 2003-09-19 주식회사 하이닉스반도체 Method of manufacturing merged memory and logic device

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