KR19980033987A - CMOS transistor and manufacturing method thereof - Google Patents

Abstract

The present invention has been described with respect to a CMOS transistor and a method of manufacturing the same. This includes: a first conducting MOS transistor having a source and a drain having an LDD structure; The source and drain have an LED structure, and the HALO structure surrounds the channel-side end of the LED structure with a first conductivity type impurity region identical to the low concentration source and drain regions of the LED structure of the first conductivity-type MOS transistor. And a second conductivity type MOS transistor. Therefore, according to the present invention, it is possible to optimize the electrical characteristics of the PMOS transistor, for example, the source-drain breakdown voltage, and improve the current driving capability without deteriorating the electrical characteristics of the NMOS transistor.

Description

CMOS transistor and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a CMOS transistor and a method for manufacturing the same which can improve electrical characteristics of a PMOS transistor and an NMOS transistor.

As semiconductor manufacturing technology is advanced and circuit speed is constantly being demanded, the channel lengths of transistors constituting CMOS have been changed from sub-micron to sub-half micron. Onwards, it's getting smaller at sub-quarter micron.

As the miniaturization of CMOS transistors is accelerated, problems due to short channel effects occur. As high frequency products are introduced, gate speed is also a problem.

Problems in the current CMOS manufacturing process are as follows.

First, since the process is being developed by targeting the NMOS transistor, the speed of the PMOS transistor is inferior to that of the NMOS transistor. Second, with the introduction of low-voltage products, the breakdown voltage level required for transistors is decreasing, and the breakdown voltage of most CMOS transistors in use is high. Thus, there is a loss of effort to manufacture it. Third, the saturation current difference between the NMOS transistor and the PMOS transistor is large.

The CMOS currently used is usually composed of an LDMOS structure, an NMOS transistor with HALO ion implantation, and a general PMOS transistor, and the difference in electrical characteristics of the two transistors is as described above. At this time, halo ion implantation technology is introduced for the purpose of improving the source-drain breakdown voltage of the transistor, and LDD structure is introduced for the purpose of improving the drive current.

An object of the present invention is to form an NMOS and a PMOS transistor in an LDD structure, and at the same time to introduce a halo ion implantation technology in forming an NMOS transistor CMOS transistor capable of improving the electrical characteristics of the PMOS transistor without deteriorating the electrical characteristics of the NMOS transistor To provide.

Another object of the present invention is to provide a manufacturing method most suitable for manufacturing the CMOS transistor.

In order to achieve the above object, the CMOS transistor according to the present invention comprises: a first conductivity type MOS transistor in which a source and a drain have an LDD structure; The source and drain have an LED structure, and the HALO structure surrounds the channel-side end of the LED structure with a first conductivity type impurity region identical to the low concentration source and drain regions of the LED structure of the first conductivity-type MOS transistor. And a second conductivity type MOS transistor.

In this case, it is preferable that the second conductive diffusion layer of the second conductive MOS transistor is an LED structure having a low concentration second conductivity type diffusion layer and a high concentration second conductivity type diffusion layer.

According to another aspect of the present invention, there is provided a CMOS transistor manufacturing method comprising: forming a first conductive well and a second conductive well in a semiconductor substrate; Forming first and second gate electrodes on the first and second conductivity type wells, and then forming a first ion implantation prevention layer to cover the second conductivity type wells; The second conductivity type diffusion layer having a first concentration in the first conductivity type wells on both sides of the first gate electrode by implanting impurity ions of the second conductivity type in the first concentration on the entire surface of the resultant substrate in which the first ion implantation prevention film is formed. Forming a; After the first ion implantation prevention film is removed, a first conductivity type of a second concentration is formed to surround the second conductivity type diffusion layer having the first concentration by implanting impurity ions of the first conductivity type into the second concentration on the entire surface of the resultant substrate. Forming a first conductivity type diffusion layer having a second concentration in a second conductivity type well on both the halo layer and the second gate electrode; Forming a spacer on sidewalls of the first and second gate electrodes; Forming a second ion implantation prevention layer to cover the second conductivity type well; Forming a second conductive diffusion layer having a third concentration in the first conductive diffusion layer having a second concentration by implanting impurity ions of a second conductivity type into the resulting substrate at a third concentration; Removing the second ion implantation prevention film, and then forming a third ion implantation prevention film to cover the first conductivity type well; And forming a first conductivity type diffusion layer having a fourth concentration in the second conductivity type wells on both sides of the second gate electrode by implanting impurity ions of the first conductivity type into the resultant substrate at a fourth concentration. do.

In this case, it is preferable that the first conductivity type is P type, the second conductivity type is N type, the first concentration is lower than the third concentration, and the second concentration is lower than the fourth concentration. It is preferable.

The first conductivity type halo layer having the second concentration may be formed to surround the second conductivity type diffusion layer having the first concentration and the second conductivity type diffusion layer having the third concentration. The first conductive diffusion layer and the first conductive diffusion layer having a fourth concentration are preferably formed so as to form an LED structure.

Therefore, according to the CMOS transistor and the manufacturing method thereof according to the present invention, it is possible to optimize the electrical characteristics of the PMOS transistor, for example, the breakdown voltage between the source and the drain, and to improve the current driving capability without deteriorating the electrical characteristics of the NMOS transistor.

1 is a cross-sectional view showing a CMOS transistor according to the present invention.

2 to 7 are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to an exemplary embodiment of the present invention, for each process sequence.

Hereinafter, with reference to the accompanying drawings, it will be described in more detail the present invention.

1 is a cross-sectional view showing a CMOS transistor according to the present invention.

An NMOS transistor is formed in the NMOS region, and a PMOS transistor is formed in the PMOS region. The NMOS transistor is composed of a source and drain 48 having a lightly doped drain (LDD) structure and a halo layer 36 and a first gate electrode 24 formed by a halo ion implantation technique. The drain 54 and the second gate electrode 26 are formed.

In this case, the NMOS transistor and the PMOS transistor are formed in the P well 12 and the N well 14, respectively.

In the present invention, the source and drain of the NMOS and PMOS transistors are formed in the LDD structure, and the halo layer is formed by the halo ion implantation technology in the source and drain formation regions of the NMOS transistor while maintaining the electrical characteristics of the existing NMOS transistors. The electrical characteristics of the PMOS transistor can be improved. Forming the source and the drain of the PMOS transistor in the LDD structure not only improves the current driving capability of the PMOS transistor, but also makes it possible to optimize the source-drain breakdown voltage.

1, which is not described in FIG. 1, represents a semiconductor substrate, 16 represents a device isolation film, 18 represents a gate oxide layer, 40 represents a first spacer, 42 represents a second spacer, 55 represents an interlayer insulating layer, and 56 represents an NMOS. A source electrode and a drain electrode of the transistor, and 58 represents a source electrode and a drain electrode of the PMOS transistor.

2 to 7 are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to the present invention for each process order.

First, the P well 12 and the N well 14 are formed on the semiconductor substrate 10 in a conventional manner, and then the NMOS region and the PMOS region are separated by a LOCal Oxidation of Silicon method. Thereafter, after the nitride film and the pad oxide film used in the partial oxidation method are removed, the gate oxide film 18 is formed on the entire surface of the semiconductor substrate 10. Subsequently, an ion implantation process for adjusting the threshold voltage of the transistor is performed on the entire semiconductor substrates of the NMOS region and the PMOS region, and the polysilicon layer 20 and the tungsten silicide layer 22 are formed on the entire surface of the resultant substrate subjected to the ion implantation process. To form (FIG. 2).

Subsequently, the polycrystalline silicon layer and the tungsten silicide layer (reference numerals 20 and 22 of FIG. 2) are patterned by a conventional photolithography process to form an NMOS gate electrode 24 in the NMOS region, and in the PMOS region. The gate electrode 26 of the PMOS is formed. Thereafter, after forming the first ion implantation prevention film 28 covering the PMOS region, the first concentration of the N-type impurity ions 30 is implanted into the semiconductor substrates on both sides of the NMOS gate electrode 24 to form a first concentration. An N type diffusion layer 32 is formed (FIG. 3).

Subsequently, the first ion implantation prevention film 28 is removed, and the P-type halo layer 36 having the second concentration is formed in the NMOS region by implanting the P-type impurity ions 34 in the second concentration on the entire surface of the resulting substrate. In the PMOS region, a P-type diffusion layer 38 having a second concentration is formed. At this time, the P-type halo layer 36 of the second concentration is formed to surround the N-type diffusion layer 32 of the first concentration (Fig. 4).

Thereafter, an oxide film is formed on the entire surface of the resultant substrate in which the second concentration P-type halo layer 36 and the second concentration P-type diffusion layer 38 are formed, and then anisotropically etch the NMOS gate electrode ( A first spacer 40 is formed on the sidewall of the 24, and a second spacer 42 is formed on the sidewall of the PMOS gate electrode 26 (FIG. 5).

Subsequently, after forming the second ion implantation prevention film 44 covering the PMOS region, the source and drain 48 of the LDD structure is implanted into the NMOS region by implanting N-type impurity ions 46 at a third concentration on the entire surface of the resultant substrate. To form. At this time, one side (gate electrode side) of the source and drain 48 is still surrounded by the halo layer 36 (FIG. 6).

Subsequently, the second ion implantation prevention film is removed, and a third ion implantation prevention film 50 covering the NMOS region is formed, and then the P-type impurity ions 52 are injected into the PMOS region at the fourth concentration on the entire surface of the resultant substrate. A source and a drain 54 of the LDD structure are formed (FIG. 7).

In the above, the source and drain 48 of the NMOS transistor is composed of an N-type diffusion layer having a first concentration and an N-type diffusion layer having a third concentration, wherein the third concentration is greater than the first concentration. In addition, the source and drain 54 of the PMOS transistor are composed of a P-type diffusion layer having a second concentration and a P-type diffusion layer having a fourth concentration, wherein the fourth concentration is greater than the second concentration.

Accordingly, according to the CMOS transistor and the method of manufacturing the same, the PMOS transistor is formed without deteriorating the electrical characteristics of the NMOS transistor by introducing a halo ion implantation technique in forming the NMOS transistor and the PMOS transistor in the LDD structure and forming the NMOS transistor. It can improve the electrical characteristics of, for example, the source-drain breakdown voltage characteristics and the current driving ability.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (7)

A first conductivity type MOS transistor having a source and a drain having an LDD structure; The source and drain have an LED structure, and the HALO structure surrounds the channel-side end of the LED structure with a first conductivity type impurity region identical to the low concentration source and drain regions of the LED structure of the first conductivity-type MOS transistor. And a second conductivity type MOS transistor. The CMOS transistor according to claim 1, wherein the second conductivity type diffusion layer of the second conductivity type MOS transistor has an LED structure comprising a low concentration second conductivity type diffusion layer and a high concentration second conductivity type diffusion layer. Forming a first conductivity type well and a second conductivity type well in the semiconductor substrate; Forming first and second gate electrodes on the first and second conductivity type wells, and then forming a first ion implantation prevention layer to cover the second conductivity type wells; The second conductivity type diffusion layer having a first concentration in the first conductivity type wells on both sides of the first gate electrode by implanting impurity ions of the second conductivity type in the first concentration on the entire surface of the resultant substrate in which the first ion implantation prevention film is formed. Forming a; After the first ion implantation prevention film is removed, a first conductivity type of a second concentration is formed to surround the second conductivity type diffusion layer having the first concentration by implanting impurity ions of the first conductivity type into the second concentration on the entire surface of the resultant substrate. Forming a first conductivity type diffusion layer having a second concentration in a second conductivity type well on both the halo layer and the second gate electrode; Forming a spacer on sidewalls of the first and second gate electrodes; Forming a second ion implantation prevention layer to cover the second conductivity type well; Forming a second conductive diffusion layer having a third concentration in the first conductive diffusion layer having a second concentration by implanting impurity ions of a second conductivity type into the resulting substrate at a third concentration; Removing the second ion implantation prevention film, and then forming a third ion implantation prevention film to cover the first conductivity type well; And forming a first conductivity type diffusion layer having a fourth concentration in the second conductivity type wells on both sides of the second gate electrode by implanting impurity ions of the first conductivity type into the resultant substrate at a fourth concentration. CMOS transistor manufacturing method. 4. The method of claim 3, wherein the first conductivity type is P type and the second conductivity type is N type. The method of claim 4, wherein the first concentration is lower than the third concentration, and the second concentration is lower than the fourth concentration. 4. The seed according to claim 3, wherein the first conductivity type halo layer of the second concentration is formed to surround the second conductivity type diffusion layer of the first concentration and the second conductivity type diffusion layer of the third concentration. MOS transistor manufacturing method. 4. The method of claim 3, wherein the first conductive diffusion layer having a second concentration and the first conductive diffusion layer having a fourth concentration are formed such that they have an LED structure.