CN111354792A - LDMOS device and forming method thereof, and forming method of semiconductor device - Google Patents

LDMOS device and forming method thereof, and forming method of semiconductor device Download PDF

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CN111354792A
CN111354792A CN201811567232.XA CN201811567232A CN111354792A CN 111354792 A CN111354792 A CN 111354792A CN 201811567232 A CN201811567232 A CN 201811567232A CN 111354792 A CN111354792 A CN 111354792A
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doping
breakdown
forming
substrate
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CN111354792B (en
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王孝远
王刚宁
彭坤
辜良智
蒲贤勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention provides an LDMOS device and a forming method thereof, and a forming method of a semiconductor device, wherein the LDMOS device comprises: a drain region located within the drift region; the substrate is exposed out of the surface of the source region, the source region is close to the gate structure, and the doping type of the source region is the same as that of the drain region; the body contact region is positioned in the body region and is next to the source region, the substrate exposes the surface of the body contact region, and the doping type of the body contact region is the same as that of the body region; and the breakdown adjusting doped region is positioned in the body region and below the body contact region, the doping type of the breakdown adjusting doped region is the same as that of the body region, and the breakdown adjusting doped region is suitable for improving the punch-through resistance between the body region and the drift region. According to the invention, the breakdown adjusting doped region is arranged between the body contact region and the body region, so that the anti-punch-through capability between the body region and the drift region is improved.

Description

LDMOS device and forming method thereof, and forming method of semiconductor device
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a forming method thereof, and a forming method of a semiconductor device.
Background
Miniaturization and integration of power electronic systems are important research directions of power semiconductor devices. The intelligent Power Integrated Circuit (SPIC) or the High Voltage Integrated Circuit (HVIC) can integrate the low voltage Circuit and the Power device on the same chip, wherein the low voltage Circuit can realize the functions of protection, control, detection or driving, etc., thus not only reducing the system volume, but also improving the system reliability.
The power device mainly comprises two types of field effect transistors, namely a Vertical Double-Diffused MOSFET (VDMOST) and a Lateral Double-Diffused MOSFET (LDMOS). Among other advantages, lateral double diffused fets have many advantages over vertical double diffused fets, such as better thermal and frequency stability, higher gain and endurance, lower feedback capacitance and thermal resistance, constant input impedance, and simpler bias current circuit for LDMOS devices.
However, the electrical performance of the LDMOS device in the prior art still needs to be improved.
Disclosure of Invention
The invention aims to provide an LDMOS device, a forming method thereof and a forming method of a semiconductor device, which solve the problem of punch through breakdown (punch through breakdown) of the LDMOS device and improve the electrical performance of the LDMOS device.
To solve the above problems, the present invention provides an LDMOS device, comprising: the device comprises a substrate, a grid structure and a grid electrode, wherein the grid electrode structure is formed on the substrate; the drift region is positioned in the substrate on one side of the grid structure, and the doping type of the drift region is P-type doping or N-type doping; the drain region is positioned in the drift region, the doping type of the drain region is the same as that of the drift region, and the substrate is exposed out of the surface of the drain region; the body region is positioned in the substrate on the other side of the gate structure, and the doping type of the body region is different from that of the drift region; the substrate is exposed out of the surface of the source region, the source region is close to the gate structure, and the doping type of the source region is the same as that of the drain region; the body contact region is positioned in the body region and is next to the source region, the substrate exposes the surface of the body contact region, and the doping type of the body contact region is the same as that of the body region; and the breakdown adjusting doped region is positioned in the body region and below the body contact region, the doping type of the breakdown adjusting doped region is the same as that of the body region, and the breakdown adjusting doped region is suitable for improving the punch-through resistance between the body region and the drift region.
The invention also provides a method for forming the LDMOS device, which comprises the following steps: providing a substrate, wherein a gate structure is formed on the substrate, a drift region is formed in the substrate on one side of the gate structure, a body region is formed in the substrate on the other side of the gate structure, the doping type of the drift region is P-type doping or N-type doping, and the doping type of the body region is different from that of the drift region; forming a drain region in the drift region, wherein the doping type of the drain region is the same as that of the drift region; forming a source region in the body region, wherein the source region is close to the gate structure, and the doping type of the source region is the same as that of the drain region; forming a body contact region next to the source region in the body region, wherein the doping type of the body contact region is the same as that of the body region; and forming a breakdown adjusting doped region in the body region, wherein the breakdown adjusting doped region is positioned below the body contact region, the doping type of the breakdown adjusting doped region is the same as that of the body region, and the breakdown adjusting doped region is suitable for improving the anti-punch-through capability between the body region and the drift region.
The invention also provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises an LDMOS (laterally diffused metal oxide semiconductor) area, a first transistor area and a second transistor area, the first transistor area is an area where a first transistor is to be formed, the second transistor area is an area where a second transistor is to be formed, the working voltage of the first transistor is higher than that of the second transistor, a first gate structure is formed on the LDMOS area substrate, a second gate structure is formed on the first transistor area substrate, a third gate structure is formed on the first transistor area substrate, a first well area is formed in the second transistor area substrate, and a body area is formed in the LDMOS area substrate on one side of the first gate structure; forming a first lightly doped region in the substrate of the first transistor region at two sides of the second gate structure; forming a drift region in the LDMOS region substrate on the other side of the first gate structure, wherein the drift region and the body region are respectively positioned on two opposite sides of the first gate structure; forming a first source drain doped region in the first lightly doped region; forming a drain region in the drift region; forming second lightly doped regions in the substrate of the second transistor region at two sides of the third gate structure, and forming breakdown adjusting doped regions in the body region simultaneously in the process step of forming the second lightly doped regions; forming a second source drain doped region in the second lightly doped region; forming a source region next to the first gate structure in the body region; a body contact region is formed in the body region adjacent to a sidewall of the source region, and the breakdown-adjusting doping region is located below the body contact region.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the invention provides an LDMOS device with excellent structural performance, which comprises a drift region, a body region, a source region, a drain region and a body contact region, wherein a breakdown adjusting doped region is arranged below the body contact region in the body region, the doping type of the breakdown adjusting doped region is the same as that of the body region, and the breakdown adjusting doped region can improve the anti-punch-through capability between the body region and the drift region and improve the electrical performance of the LDMOS device.
In an alternative scheme, the concentration of the doping ions of the breakdown adjusting doping region is equal to that of the doping ions of the body region, so that the influence of the arrangement of the breakdown adjusting doping region on the conducting resistance of the LDMOS device is small, and the breakdown voltage of the LDMOS device is improved under the condition that the conducting resistance is not increased.
According to the technical scheme of the forming method of the semiconductor device, the high-voltage transistor and the low-voltage transistor in the LDMOS device and the logic device are formed, the second lightly doped region in the low-voltage transistor is formed, and meanwhile the breakdown adjusting doped region is formed in the body region of the LDMOS device.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of an LDMOS device provided in an embodiment of the present invention;
fig. 2 to fig. 6 are schematic structural diagrams corresponding to steps in a method for forming an LDMOS device according to an embodiment of the invention;
fig. 7 to fig. 11 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As is known from the background art, the performance of the LDMOS device in the prior art needs to be improved.
Analysis shows how to improve the Breakdown Voltage (Breakdown Voltage) of the LDMOS device without increasing the on-resistance Ron, which is one of the important research points of the LDMOS device. For this purpose, three improvements are proposed, including: firstly, optimizing the ion implantation process condition of the LDMOS drain doped region; secondly, performing an additional body region ion implantation process step on one side of the LDMOS source doped region; thirdly, performing an additional well region ion implantation process step at the side where the LDMOS source doped region is located.
However, the above-described improvement still has problems such as an increase in on-resistance or a complicated process.
In order to solve the problems, the invention provides an LDMOS device, which is used for improving the transverse breakdown problem of the LDMOS device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic cross-sectional structure diagram of an LDMOS device provided in an embodiment of the present invention.
Referring to fig. 1, the LDMOS device provided in this embodiment includes: a substrate 100, wherein a gate structure is formed on the substrate 100; a Drift Region (Drift Region)101 located in the substrate 100 on one side of the gate structure, wherein the doping type of the Drift Region 101 is P-type doping or N-type doping; a Drain region (Drain Area)102 located in the drift region 101, wherein the Drain region 102 has the same doping type as the drift region 101, and the substrate 100 exposes the Drain region surface 102; a Body Region (Body Region)104 located in the substrate 100 at the other side of the gate structure, wherein the doping type of the Body Region 104 is different from that of the drift Region 101; a Source region (Source Area)105 located in the body region 104, the substrate 100 exposing a surface of the Source region 105, the Source region 105 being adjacent to the gate structure, a doping type of the Source region 105 being the same as a doping type of the drain region 102; a Body contact region (Body contact region)106 located in the Body region 104 and next to the source region 105, wherein the substrate 100 exposes a surface of the Body contact region 106, and a doping type of the Body contact region 106 is the same as a doping type of the Body region 104; a breakdown-adjusting doped region 107 located within the body region 104 and below the body contact region 106, the breakdown-adjusting doped region 107 having a doping type that is the same as the doping type of the body region 104, the breakdown-adjusting doped region 107 being adapted to improve punch-through resistance between the body region 104 and the drift region 101.
The LDMOS device is an N-type device and will be described in detail below with reference to the accompanying drawings.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, silicon germanium, gallium arsenide, indium gallium or silicon on insulator.
In this embodiment, the Substrate 100 is a P-type Substrate (P-type Substrate), and P-type ions are doped in the Substrate 100. In other embodiments, when the LDMOS device is a P-type device, the substrate is an N-type substrate, and correspondingly, N-type ions are doped in the substrate.
The gate structure comprises a gate dielectric layer 111 and a gate electrode layer 112 located on the surface of the gate dielectric layer 111. The gate dielectric layer 111 is made of silicon oxide, silicon nitride or silicon oxynitride, and the gate dielectric layer 111 may also be made of a high-k gate dielectric material, such as HfO2Or Al2O3(ii) a The gate electrode layer 112 is made of polysilicon or metal, and the metal may be copper, aluminum, or tungsten.
In this embodiment, the gate structure further includes a sidewall 113 covering the sidewalls of the gate dielectric layer 111 and the gate electrode layer 112. The side walls 113 protect the side walls of the gate dielectric layer 111 and the gate electrode layer 112, and the side walls 113 further define the positions of the drain region 102 and the source region 105.
The drift region 101 is beneficial to improving the breakdown voltage between the active region and the drain region 102, reducing the parasitic capacitance between the active region and the drain region 102 and improving the frequency characteristic; in addition, the drift region 101 plays a role in buffering between the channel and the drain region 102, which is beneficial to weakening the short-channel effect of the LDMOS device.
The doping type of the drift region 101 is P-type doping or N-type doping. In this embodiment, the LDMOS device is an N-type device, and correspondingly, the doping type of the drift region 101 is N-type doping, and the doping ion of the N-type doping is P, As or Sb.
The drift region 101 is a high resistance layer, so that the concentration of the doped ions in the drift region 101 is small, and the concentration of the doped ions in the drift region 101 is smaller than that in the drain region 102.
The drain region 102 serves as the drain of the LDMOS device. In this embodiment, the substrate 100 exposes a top surface of the drain region 102, and a doping type of the drain region 102 is N-type doping. In other embodiments, when the LDMOS device is a P-type device, the doping type of the drain region is P-type doping.
The LDMOS device further comprises: be located drain region 102 with field oxide 103 between the gate structure, field oxide 103 top is higher than the basement 100 surface, perhaps, field oxide 103 top with basement 100 surface flushes.
In this embodiment, the material of the field oxide layer 103 is silicon oxide. In other embodiments, the material of the field-like layer may also be silicon nitride-like or silicon oxycarbonitride.
The doping type of the body region 104 is N-type doping or P-type doping, and the doping type of the body region 104 is different from the doping type of the drift region 101. In this embodiment, the doping type of the body region 104 is P-type doping, and the doping ions used for the P-type doping are B, Ga or In.
In this embodiment, the doping ion concentration of the body region 104 is 1012atom/cm3～8×1013atom/cm3。
The source region 105 serves as the source of the LDMOS device. The doping type of the source region 105 is the same as the doping type of the drain region 102. In this embodiment, the concentration of the dopant ions in the source region 105 is the same as the concentration of the dopant ions in the drain region 102.
The doping type of the body contact region 106 is the same as the doping type of the body region 104, and the doping ion concentration of the body contact region 106 is greater than the doping ion concentration of the body region 104, so the resistance of the body contact region 106 is smaller.
In this embodiment, the sidewall of the body contact region 106 contacts the sidewall of the source region 105, the doped ions of the body contact region 106 are P-type ions, and the concentration of the doped ions is 1015atom/cm3～5×1018atom/cm3。
The doping type of the breakdown adjustment doping region 107 is the same as the doping type of the body region 104, and since the breakdown voltage adjustment region 107 is further arranged between the body contact region 106 and the body region 104, the breakdown voltage adjustment region 107 is beneficial to increasing the doping ion concentration of the body region 104 close to the drift region 101, so that the probability of lateral punch-through between the body region 104 and the drift region 101 is reduced, and the breakdown voltage between the body region 104 and the drift region 101 is increased.
Therefore, the breakdown adjusting doping region 107 can improve the punch-through resistance between the body region 104 and the drift region 101. As an explanation, the mechanism by which the breakdown adjusting doping region 107 can improve the punch-through resistance includes: when the LDMOS device is subjected to the annealing process, the dopant ions in the body region 104 will diffuse towards the drift region 101, so that the dopant ion concentration in the body region 104 close to the drift region 101 decreases, and therefore the dopant ion concentration difference between the drift region 101 and the body region 104 close to the drift region 101 becomes large, which will increase the probability of lateral breakdown between the body region 104 and the drift region 101; due to the fact that the breakdown adjusting doping 107 is arranged between the body contact region 106 and the body region 104, when the LDMOS device is subjected to annealing treatment, doping ions in the breakdown adjusting doping region 107 diffuse into the body region 104 close to the drift region 101, so that the problem of reduction of the concentration of the doping ions in the body region 104 close to the drift region 101 is solved or offset, the doping ions in the body region 104 close to the drift region 101 still have a large concentration, a proper concentration difference of the doping ions between the body region 104 and the drift region 101 is guaranteed, the probability of lateral punch-through between the body region 104 and the drift region 101 is reduced, the breakdown voltage of the LDMOS device is increased, and the electrical performance of the LDMOS device is improved.
In this embodiment, the top of the breakdown adjusting doping region 107 is in contact with the bottom of the body contact region 106, and the sidewall of the breakdown adjusting doping region 107 is flush with the sidewall of the body contact region 106. In other embodiments, the breakdown-adjusting doping region may also be located below a portion of the source region, that is, the breakdown-adjusting doping region sidewall is located below the source region.
The concentration of the dopant ions of the breakdown adjusting dopant region 107 is less than the concentration of the dopant ions of the body contact region 106, and the concentration of the dopant ions of the breakdown adjusting dopant region 107 is greater than or equal to the concentration of the dopant ions of the body region 104.
In this embodiment, the doping type of the breakdown adjustment doping region 107 is P-type doping, and the doping ion concentration of the breakdown adjustment doping region 107 is not too small or too large. If the concentration of the dopant ions in the breakdown adjustment doping region 107 is too small, the breakdown adjustment doping region 107 has a weak ability to suppress lateral punch-through; if the concentration of the dopant ions in the breakdown adjusting dopant region 107 is too high, the amount of dopant ions in the breakdown adjusting dopant region 107 diffusing into the body region 104 is too high.
For this reason, in the present embodiment, the concentration of the dopant ion in the breakdown adjusting dopant region 107 is 1012atom/cm3～5×1013atom/cm3。
In other embodiments, when the doping type of the breakdown adjustment doping region is N-type doping, the doping ion concentration range of the breakdown adjustment doping region is 1012atom/cm3～5×1013atom/cm3。
In this embodiment, the distance between the bottom of the breakdown adjusting doping region 107 and the bottom of the body region 104 is 0.1 μm to 0.5 μm, for example, 0.2 μm, 0.3 μm, and 0.4 μm.
The LDMOS device further comprises: a guard ring (guard ring) structure, the guard ring structure comprising a guard ring well region 109 adjacent to the body region 104, the doping type of the guard ring well region 109 being different from the doping type of the body region 104, a guard ring contact region 110 located in the guard ring well region 109, and the surface of the guard ring contact region 110 being exposed from the substrate 100. The doping type of the guard ring contact region 110 is the same as the doping type of the guard ring well region 109, and the doping ion concentration of the guard ring contact region 110 is greater than the doping ion concentration of the guard ring well region 109.
The LDMOS device further comprises: an isolation structure 108 within the substrate 100, the isolation structure 108 electrically isolating the guard ring structure from the body contact region 106. In this embodiment, the isolation structure 108 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
Table one is a table comparing the performance of the LDMOS device provided in this embodiment with the performance of the existing LDMOS device, specifically comparing the performance of the N-type LDMOS device with the 40V operating voltage.
Watch 1
Figure BDA0001913108170000081
As can be seen from table one, the on-resistance Ron of the conventional LDMOS device is 31.6 Ω, and the on-resistance R of the LDMOS device in this embodiment isonIs 32 omega, the conduction resistance of the LDMOS device in this embodiment is increased by only 1.2% compared to the conventional LDMOS device. At a voltage V applied to the gate structureGUnder the condition of 5V, the direct current breakdown voltage BV in the prior artonThe breakdown voltage BV of the LDMOS device of this embodiment is 55VonIs 65V, so the direct current breakdown voltage BV of the LDMOS device in this embodiment is compared with that of the conventional LDMOS deviceonThe voltage is increased by 10V; at a voltage V applied to the gate structureGAt 5V, the breakdown voltage BV of the prior artonThe breakdown voltage BV of the LDMOS device in this embodiment is 48VonIs 66V, therefore, compared with the prior art, the alternating current breakdown voltage BV of the LDMOS device in this embodiment isonThe increase is 18V.
Therefore, the LDMOS device with excellent structural performance is provided, the breakdown performance of the LDMOS device is obviously improved under the condition of little influence on the conducting resistance, and the breakdown voltage of the LDMOS device is improved.
In the technical scheme of the LDMOS device provided by this embodiment, the breakdown adjusting doped region 107 is disposed in the body region 104 below the body contact region 106, and the breakdown adjusting doped region 107 is beneficial to improving the breakdown voltage between the body region 104 and the drift region 101, reducing the probability of lateral punch-through between the body region 104 and the drift region 101, and not significantly increasing the on-resistance of the LDMOS device, thereby improving the electrical performance of the LDMOS device.
Correspondingly, the embodiment of the invention also provides a forming method for forming the LDMOS device. Fig. 2 to fig. 6 are schematic structural diagrams corresponding to steps in a method for forming an LDMOS device according to an embodiment of the present invention. The following describes a method for forming an LDMOS device according to an embodiment of the present invention in detail with reference to the accompanying drawings.
In this embodiment, a substrate is provided, a gate structure is formed on the substrate, a drift region is formed in the substrate on one side of the gate structure, a body region is formed in the substrate on the other side of the gate structure, the doping type of the drift region is P-type doping or N-type doping, and the doping type of the body region is different from the doping type of the drift region. Specifically, the forming step of the drift region and the body region includes:
referring to fig. 2, a substrate 100 is provided, and a gate structure is formed on the substrate 100.
In this embodiment, the substrate 100 is made of silicon. The gate structure comprises a gate dielectric layer 111 and a gate electrode layer 112 located on the surface of the gate dielectric layer 111, and the gate structure further comprises a side wall 113 covering the side wall of the gate dielectric layer 111 and the side wall of the gate electrode layer 112.
Before the gate structure is formed, the method further comprises the following steps: form isolation structure 108 in the basement 100 form field oxide layer 103 in the basement 100, just field oxide layer 103 top is higher than basement 100 surface.
In this embodiment, the gate structure is formed to cover the sidewall and a portion of the top surface of the field oxide layer 103.
Referring to fig. 3, a drift region 101 is formed in the substrate 100 on one side of the gate structure, and the doping type of the drift region 101 is P-type doping or N-type doping; and forming a body region 104 in the substrate 100 on the other side of the gate structure, wherein the doping type of the body region 104 is different from that of the drift region 101.
In this embodiment, the formed LDMOS device is an N-type device as an example.
The drift region 101 is formed by an ion implantation process. Specifically, the process steps for forming the drift region 101 include: forming a first mask layer on the surface of the substrate 100, wherein the first mask layer exposes the surface of the substrate 100 on one side of the gate structure; doping the substrate 100 exposed by the first mask layer by adopting an ion implantation process to form the drift region 101; and removing the first mask layer.
Accordingly, the body region 104 is formed by an ion implantation process.
In this embodiment, before forming the drift region 101 and the body region 104, the method further includes the steps of: doping the substrate 100 on one side of the isolation structure 108 to form a guard ring well region 109, where the guard ring well region 109 and the body region 104 are respectively located on two opposite sides of the isolation structure 108.
The guard ring well region 109 has a doping type different from the doping type of the body region 104.
The subsequent process steps comprise: forming a drain region in the drift region 101, wherein the doping type of the drain region is the same as that of the drift region 101; forming a source region in the body region 104, wherein the source region is adjacent to the gate structure, and the doping type of the source region is the same as that of the drain region; forming a body contact region next to the source region in the body region 104, and the doping type of the body contact region is the same as that of the body region 104; and forming a breakdown adjusting doped region in the body region 104, wherein the breakdown adjusting doped region is positioned below the body contact region, the doping type of the breakdown adjusting doped region is the same as that of the body region 104, and the breakdown adjusting doped region is suitable for improving the punch-through resistance between the body region 104 and the drift region 101.
In this embodiment, a source region and a drain region are formed first, and the breakdown adjustment doped region is formed subsequently as an example. It should be noted that, in other embodiments, the breakdown adjustment doping region may be formed first, and then the source region and the drain region may be formed.
The formation steps of the source region, the drain region, the body contact region, and the breakdown-adjusting doping region will be described with reference to fig. 4 to 6.
Referring to fig. 4, a first photoresist layer 121 having a first opening is formed on the substrate 100; the first photoresist layer 121 is used as a mask to perform a first doping on the body region 104 under the first opening, so as to form an initial doped region 117.
The initial doped region 117 provides a process basis for the subsequent formation of the breakdown-adjusting doped region, the subsequent doping treatment is performed on a part of the depth of the initial doped region 117 to form a body contact region, and the remaining initial doped region 117 serves as the breakdown-adjusting doped region.
Therefore, the initial doping region 117 has the same dopant ion concentration as that of the breakdown adjustment doping region to be formed later.
In this embodiment, the initial doping region 117 is formed by an ion implantation process. The process parameters for forming the initial doped region 117 include: the injection energy is 50 to 100kev, and the injection dose is 1012atom/cm2～5×1013atom/cm2。
After the formation of the initial doping region 117, the first photoresist layer 121 is removed.
Referring to fig. 5, a drain region 102 is formed in the drift region 101, and the doping type of the drain region 102 is the same as that of the drift region 101; a source region 105 is formed in the body region 104, the source region 105 is adjacent to the gate structure, and the doping type of the source region 105 is the same as that of the drain region 102.
In this embodiment, the process steps for forming the drain region 102 and the source region 105 include: forming a third mask layer 122 on the substrate 100, wherein the third mask layer 122 covers the surface of the initial doping region 117, and the third mask layer 122 exposes parts of the substrate 100 on two sides of the gate structure; doping the drift region 101 and the body region 104 using the third mask layer 122 as a mask to form the source region 105 and the drain region 102.
In this embodiment, the sidewall of the third mask layer close to the initial doped region 117 is flush with the sidewall of the initial doped region 117, so that the sidewall of the breakdown adjustment doped region formed subsequently is flush with the sidewall of the source region 105. It should be noted that, in other embodiments, the sidewall of the third mask layer close to the initial doped region may also be located above the initial doped region, and the corresponding subsequently formed breakdown-adjusting doped region is located below the body contact region and also below the partial source region.
It should be noted that, in the present embodiment, in the process step of forming the source region 102 and the drain region 105, doping treatment is further performed on the guard ring well region 109, a guard ring contact region 110 is formed in the guard ring well region 109, and the guard ring contact region 110 and the guard ring well region 109 jointly form a guard ring structure.
After the source region 105 and the drain region 102 are formed, the third mask layer 122 is removed.
Referring to fig. 6, a second photoresist layer 123 having a second opening is formed on the substrate 100; the initial doped region 117 (refer to fig. 5) under the second opening is second doped by using the second photoresist layer 123 as a mask to form the body contact region 106, and the initial doped region 117 under the body contact region 106 is used as the breakdown-adjusting doped region 107.
Accordingly, the top of the breakdown adjusting doping region 107 is formed to contact the bottom of the body contact region 106.
In this embodiment, the position of the second opening is consistent with the position of the first opening, the sidewall of the corresponding formed breakdown adjusting doping region 107 is flush with the sidewall of the body contact region 106, and the width dimension of the second opening is equal to the width dimension of the first opening in the direction parallel to the surface of the substrate 100.
Since the position of the second opening is consistent with the position of the first opening, unnecessary doping on the source region 105 can be avoided, and the conductivity of the source region 105 can be prevented from being affected.
In this embodiment, after the source region 105 and the drain region 102 are formed, the body contact region 106 and the breakdown adjustment doping region 107 are formed; in other embodiments, the body contact region and the breakdown-adjusting doping region may be formed first, and then the source region and the drain region may be formed.
In the technical scheme of the method for forming the LDMOS device provided by this embodiment, the breakdown adjusting doping region 107 is formed in the body region 104, the breakdown adjusting doping region 107 is located below the body contact region 106, and the presence of the breakdown adjusting doping region 107 is beneficial to improving the breakdown voltage between the body region 104 and the drift region 101 of the LDMOS device and improving the punch-through resistance of the LDMOS device.
In addition, in the present embodiment, the initial doping region 117 is formed in the body region 104, then the body contact region 106 is formed by doping a part of the initial doping region 117, and the remaining initial doping region 117 is used as the breakdown adjustment doping region 107, so that the process steps are simple.
An embodiment of the present invention further provides a method for forming a semiconductor device including the LDMOS device, and fig. 7 to 11 are schematic structural diagrams corresponding to steps of the method for forming a semiconductor device according to the embodiment of the present invention. A method for forming a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 7, a substrate 200 is provided, where the substrate 200 includes an LDMOS region L, a first transistor region I and a second transistor region II, the first transistor region I is a region where a first transistor is to be formed, the second transistor region II is a region where a second transistor is to be formed, a working voltage of the first transistor is higher than a working voltage of the second transistor, a first gate structure 11 is formed on the substrate 200 of the LDMOS region L, a second gate structure 12 is formed on the substrate 200 of the first transistor region I, a third gate structure 13 is formed on the substrate 200 of the second transistor region II, a first well region 31 is formed in the substrate 200 of the first transistor region I, and a body region 204 is formed in the substrate 200 of the LDMOS region L on one side of the first gate structure 11.
The semiconductor device formed by the embodiment comprises the LDMOS device and the logic device, and the LDMOS device is formed by utilizing the formation process of the logic device.
Wherein the first transistor is a high voltage transistor in the logic device, the second transistor is a low voltage transistor in the logic device, and the high voltage and the low voltage referred to herein are compared with respect to the operating voltage of the first transistor and the second transistor.
The first transistor is an NMOS device or a PMOS device, the second transistor is an NMOS device or a PMOS device, and the types of the first transistor and the second transistor are different; the LDMOS region L is a region where an LDMOS device is to be formed, and the LDMOS device is an N-type or P-type device.
In this embodiment, the first transistor is an NMOS device, the second transistor is a PMOS device, and the LDMOS device is an N-type device.
Specifically, the first well region 31 and the body region 204 are formed by using the same mask and the same ion implantation process.
Further comprising: an isolation structure 208 is formed in the substrate 200, wherein the isolation structure 208 is used for electrically isolating the LDMOS region, the first transistor region I, and the second transistor region II.
The first gate structure 11 includes: the first gate dielectric layer and the first gate electrode layer can also comprise a first side wall; the second gate structure 12 includes: the second gate dielectric layer and the second gate electrode layer can also comprise a second side wall; the third gate structure 13 includes: the third gate dielectric layer and the third gate electrode layer may further include a third sidewall.
In this embodiment, a field oxide layer (not labeled) is further formed in the LDMOS region L substrate 200, and the first gate structure covers a portion of the top and the sidewall of the field oxide layer.
Referring to fig. 8, first lightly doped regions 301 are formed in the first transistor region I substrate 200 at both sides of the second gate structure 12; a drift region 201 is formed in the LDMOS region L substrate 200 on the other side of the first gate structure 11, and the drift region 201 and the body region 204 are respectively located on two opposite sides of the first gate structure 11.
In this embodiment, the first lightly doped region 301 and the drift region 201 are formed by using the same mask and the same ion implantation process, which is beneficial to reducing the process cost and saving the process steps.
In this embodiment, the process steps for forming the first lightly doped region 301 and the drift region 201 include: forming a first photoresist layer 401 on the substrate 200; performing first ion implantation on the first transistor area I substrate 200 at two sides of the second gate structure 12 and performing first ion implantation on the LDMOS area L substrate 200 at one side of the first gate structure 11 to form the first lightly doped area 301 and the drift area 201 by using the first photoresist layer 401 as a mask; the first photoresist layer 401 is removed.
In this embodiment, the implanted ions used in the first ion implantation process are N-type ions.
In the process of forming the drift region 201, a guard ring well region (not shown) is further formed in the LDMOS region L substrate 200, and the guard ring well region is used for forming a guard ring structure of an LDMOS device.
Referring to fig. 9, a first source/drain doped region 302 is formed in the first lightly doped region 301; forming a drain region 203 in the drift region 201; source regions 205 are formed next to first gate structures 11 within body regions 204.
The substrate 200 exposes the surfaces of the first source-drain doped region 302, the source region 205 and the drain region 203.
In this embodiment, in order to save the process cost and reduce the process steps, the first source-drain doped region 302, the source region 205, and the drain region 203 are formed under the same photomask and in the same ion implantation process.
In this embodiment, the process steps for forming the first source-drain doped region 302, the source region 205, and the drain region 203 include: forming a second photoresist layer 402 on the substrate 200; performing second ion implantation on the first lightly doped region 301, the drift region 201 and the body region 204 with partial thickness by using the second photoresist layer 402 as a mask to form the first source-drain doped region 302, the source region 205 and the drain region 203; the second photoresist layer 402 is removed.
In this embodiment, the implanted ions used in the second ion implantation process are N-type ions.
In the process step of forming the source region 205 and the drain region 203, a guard ring contact region (not shown) is further formed in the guard ring well region, and the guard ring contact region and the guard ring well region together form a guard ring structure.
Referring to fig. 10, second lightly doped regions 311 are formed in the substrate 200 of the second transistor region II on both sides of the third gate structure 13, and in the process step of forming the second lightly doped regions 311, breakdown adjusting doped regions 207 are simultaneously formed in the body regions 204.
In this embodiment, the second lightly doped region 311 and the breakdown adjusting doped region 207 are formed under the same mask by using the same ion implantation process. That is, the punch-through adjustment doping region 207 may be formed by directly using a logic device forming process without providing an additional mask forming process and an additional ion implantation process.
The process steps for forming the second lightly doped region 311 and the breakdown adjusting doped region 207 include: forming a third photoresist layer 403 on the substrate 200, where the third photoresist layer 302 exposes the surface of the substrate 200 on both sides of the second gate structure 12 and also exposes the surface of the body region 204 exposed by the source region 205; performing ion implantation on the substrate 200 on both sides of the second gate structure 12 and the body region 204 exposed by the source region 205 by using the third photoresist layer 403 as a mask to form the second lightly doped region 311 and the breakdown adjustment doped region 207; the third photoresist layer 403 is removed.
In this embodiment, the sidewall of the third photoresist layer 403 close to the source region 205 is flush with the sidewall of the source region 205, and correspondingly, the sidewall of the breakdown-adjusting doping region 207 is flush with the sidewall of the source region 205.
The doping type of the second lightly doped region 311 is P-type doping. The ion implantation process parameters for forming the second lightly doped region 311 and the breakdown adjustment doped region 207 include: the injection energy is 50 to 100kev, and the injection dose is 1012atom/cm2～5×1013atom/cm2。
Since the breakdown adjustment doping region 207 and the second lightly doped region 311 are formed by using the same ion implantation process, the bottom of the breakdown adjustment doping region 207 and the bottom of the second lightly doped region 311 are flush with each other.
Referring to fig. 11, a second source/drain doped region 312 is formed in the second lightly doped region 311; a body contact region 206 is formed within body region 204 next to the sidewalls of source region 205 and breakdown-adjusting doped region 207 is located below body contact region 206.
In this embodiment, the second source/drain doped region 312 and the body contact region 206 are formed under the same mask by using the same ion implantation process.
In the process step of forming the body contact region 206, a doping treatment is performed on a partial thickness of the breakdown-modifying doped region 207 to convert the partial thickness of the breakdown-modifying doped region 207 into the body contact region 206. To this end, after the body contact region 206 is formed, the bottom of the body contact region 206 is in contact with the top of the breakdown-adjusting doping region 207.
In this embodiment, the process steps for forming the second source-drain doped region 312 and the body contact region 206 include: forming a fourth photoresist layer 404 on the substrate 200, wherein the fourth photoresist layer 304 exposes the surface of the second lightly doped region 311 and also exposes the surface of the breakdown adjustment doped region 207; performing ion implantation on the second lightly doped region 311 and the breakdown adjusting doped region 207 with partial thickness by using the fourth photoresist layer 304 as a mask to form the second source-drain doped region 312 and the body contact region 206; the fourth photoresist layer 404 is removed.
In the method for forming the semiconductor device provided by the embodiment, the breakdown adjusting doping region for improving the lateral punch-through problem in the LDMOS device is formed by using the process for forming the lightly doped region in the low-voltage transistor in the logic device, so that the LDMOS device with high breakdown voltage can be formed without an additional photomask and an ion implantation process, and the process cost and the production period are not increased while the performance of the formed semiconductor device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. An LDMOS device, comprising:
the device comprises a substrate, a grid structure and a grid electrode, wherein the grid electrode structure is formed on the substrate;
the drift region is positioned in the substrate on one side of the grid structure, and the doping type of the drift region is P-type doping or N-type doping;
the drain region is positioned in the drift region, and the doping type of the drain region is the same as that of the drift region;
the body region is positioned in the substrate on the other side of the gate structure, and the doping type of the body region is different from that of the drift region;
the source region is positioned in the body region and is close to the gate structure, and the doping type of the source region is the same as that of the drain region;
the body contact region is positioned in the body region and is next to the source region, the substrate exposes the surface of the body contact region, and the doping type of the body contact region is the same as that of the body region;
and the breakdown adjusting doped region is positioned in the body region and below the body contact region, the doping type of the breakdown adjusting doped region is the same as that of the body region, and the breakdown adjusting doped region is suitable for improving the punch-through resistance between the body region and the drift region.
2. The LDMOS device of claim 1, wherein a top portion of the breakdown tuning doped region contacts a bottom portion of the body contact region.
3. The LDMOS device of claim 2, wherein a sidewall of the breakdown tuning doped region is flush with a sidewall of the body contact region.
4. The LDMO device of claim 2 wherein the breakdown adjusting doping region is also located below a portion of the source region.
5. The LDMOS device of claim 1, wherein the breakdown adjusting doped region has a dopant ion concentration that is less than a dopant ion concentration of the body contact region, and the breakdown adjusting doped region has a dopant ion concentration that is greater than or equal to a dopant ion concentration of the body region.
6. The LDMOS device of claim 5, wherein a doping type of the breakdown tuning doping region is a P-type doping; the concentration range of the doped ions of the breakdown adjusting doped region is 1012atom/cm3～5×1013atom/cm3。
7. The LDMOS device of claim 5, wherein a doping type of the breakdown tuning doping region is N-type doping; the concentration range of the doped ions of the breakdown adjusting doped region is 1012atom/cm3～5×1013atom/cm3。
8. The LDMOS device of claim 1, wherein a distance between a bottom of the breakdown adjusting doped region and a bottom of the body region ranges from 0.1 μm to 0.5 μm.
9. A method for forming an LDMOS device, comprising:
providing a substrate, wherein a gate structure is formed on the substrate, a drift region is formed in the substrate on one side of the gate structure, a body region is formed in the substrate on the other side of the gate structure, the doping type of the drift region is P-type doping or N-type doping, and the doping type of the body region is different from that of the drift region;
forming a drain region in the drift region, wherein the doping type of the drain region is the same as that of the drift region;
forming a source region in the body region, wherein the source region is close to the gate structure, and the doping type of the source region is the same as that of the drain region;
forming a body contact region next to the source region in the body region, wherein the doping type of the body contact region is the same as that of the body region;
and forming a breakdown adjusting doped region in the body region, wherein the breakdown adjusting doped region is positioned below the body contact region, the doping type of the breakdown adjusting doped region is the same as that of the body region, and the breakdown adjusting doped region is suitable for improving the anti-punch-through capability between the body region and the drift region.
10. The method of forming of claim 9, wherein a top of the breakdown adjusting doping region is in contact with a bottom of the body contact region; the process steps for forming the body contact region and the breakdown tuning doping region include:
forming a first photoresist layer with a first opening on the substrate;
performing first doping on the body region below the first opening by taking the first photoresist layer as a mask to form an initial doped region;
after the initial doped region is formed, removing the first photoresist layer;
forming a second photoresist layer with a second opening on the substrate;
performing second doping on the initial doping region below the second opening by taking the second photoresist layer as a mask to form the body contact region, wherein the initial doping region below the body contact region is used as the breakdown adjustment doping region;
and removing the second photoresist layer.
11. The method of forming of claim 10, in which a sidewall of the breakdown tuning doped region is formed flush with a sidewall of the body contact region; the width dimension of the second opening is equal to the width dimension of the first opening in a direction parallel to the substrate surface.
12. The method of forming of claim 10, wherein the process step of forming the source region comprises: forming a mask layer on the substrate, wherein the side wall of the mask layer close to the initial doping area is flush with the side wall of the initial doping area; doping the body region by taking the mask layer as a mask to form the source region; and removing the mask layer.
13. The method of claim 10, wherein the initial doped region is formed using an ion implantation process.
14. The method of forming of claim 13, wherein the dopant ions of the breakdown voltage adjusting dopant region are P-type ions; the process parameters for forming the initial doped region comprise: the injection energy is 50 to 100kev, and the injection dose is 1012atom/cm2～5×1013atom/cm2。
15. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an LDMOS (laterally diffused metal oxide semiconductor) region, a first transistor region and a second transistor region, the first transistor region is a region in which a first transistor is to be formed, the second transistor region is a region in which a second transistor is to be formed, the working voltage of the first transistor is higher than that of the second transistor, a first gate structure is formed on the LDMOS region substrate, a second gate structure is formed on the first transistor region substrate, a third gate structure is formed on the second transistor region substrate, a first well region is formed in the first transistor region substrate, and a body region is formed in the LDMOS region substrate on one side of the first gate structure;
forming a first lightly doped region in the substrate of the first transistor region at two sides of the second gate structure;
forming a drift region in the LDMOS region substrate on the other side of the first gate structure, wherein the drift region and the body region are respectively positioned on two opposite sides of the first gate structure;
forming a first source drain doped region in the first lightly doped region;
forming a drain region in the drift region;
forming second lightly doped regions in the substrate of the second transistor region at two sides of the third gate structure, and forming breakdown adjusting doped regions in the body region simultaneously in the process step of forming the second lightly doped regions;
forming a second source drain doped region in the second lightly doped region;
forming a source region next to the first gate structure in the body region;
a body contact region is formed in the body region adjacent to a sidewall of the source region, and the breakdown-adjusting doping region is located below the body contact region.
16. The method of claim 15, wherein the second lightly doped region and the punch through adjustment doped region are formed under a same mask and using a same ion implantation process.
17. The method of forming of claim 16, wherein in the process step of forming the body contact region, a doping process is performed on a portion of the thickness of the breakdown-modifying doped region to convert the portion of the thickness of the breakdown-modifying doped region into the body contact region.
18. The method of forming of claim 16, wherein the process steps of forming the second lightly doped region and the breakdown tuning doped region comprise: forming a photoresist layer on the substrate, wherein the side wall of the photoresist layer close to the source region is flush with the side wall of the source region; taking the photoresist layer as a mask, and performing ion implantation on the substrate on two sides of the second gate structure and the body region exposed from the source to form a second lightly doped region and a breakdown adjusting doped region; and removing the third photoresist layer.
19. The method of claim 17, wherein the doping type of the second lightly doped region is P-type doping; the ion implantation process parameters for forming the second lightly doped region and the breakdown adjustment doped region comprise: implantation energy50 to 100kev, and the injection dosage is 1012atom/cm2～5×1013atom/cm2。
20. The method of claim 15, wherein the first well region and the body region are formed under a same mask and in a same ion implantation process; the first lightly doped region and the drift region are formed under the same photomask by using the same ion implantation process; the first source-drain doped region, the source region and the drain region are formed under the same photomask by using the same ion implantation process; the second source drain doping area and the body contact area are formed under the same photomask by using the same ion implantation process.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022016659A1 (en) * 2020-07-21 2022-01-27 苏州华太电子技术有限公司 High-mobility p-type polysilicon gate ldmos device and manufacturing method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102306661A (en) * 2011-09-20 2012-01-04 上海先进半导体制造股份有限公司 LDMOS (laterally diffused metal oxide semiconductor) transistor structure and formation method thereof
CN105448979A (en) * 2014-06-12 2016-03-30 中芯国际集成电路制造(上海)有限公司 Lateral double-diffusion field effect transistor and forming method therefor
CN107564816A (en) * 2016-06-30 2018-01-09 中芯国际集成电路制造(上海)有限公司 Ldmos transistor and forming method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102306661A (en) * 2011-09-20 2012-01-04 上海先进半导体制造股份有限公司 LDMOS (laterally diffused metal oxide semiconductor) transistor structure and formation method thereof
CN105448979A (en) * 2014-06-12 2016-03-30 中芯国际集成电路制造(上海)有限公司 Lateral double-diffusion field effect transistor and forming method therefor
CN107564816A (en) * 2016-06-30 2018-01-09 中芯国际集成电路制造(上海)有限公司 Ldmos transistor and forming method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022016659A1 (en) * 2020-07-21 2022-01-27 苏州华太电子技术有限公司 High-mobility p-type polysilicon gate ldmos device and manufacturing method therefor

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