TWI398951B - Vertical type mosfet device structure with split gates and method for manufacturing the same - Google Patents

Description

Split gate vertical type gold-oxygen semi-transistor element structure and manufacturing method thereof

The present invention relates to a gold oxide half field effect transistor, and more particularly to a power vertical type double diffused gold oxide half field effect transistor.

Metal-Oxide-Semiconductor Field Effect Electrode (MOSFET) is a field effect transistor (field) that can be widely used in analog circuits and digital circuits. -effect transistor). MOSFETs can be divided into N-type and P-type MOSFETs according to the polarity of their "channels". They are also commonly referred to as NMOSFETs and PMOSFETs. Others include NMOS FETs, PMOS FETs, nMOSFETs, and pMOSFETs.

The first figure is a cross-sectional structural view of a typical power vertical type gold oxide half field effect transistor 10. There are significant differences in the structure between the power vertical MOSFET and the aforementioned MOSFET component. The MOSFETs in general integrated circuits are planar structures, while the power vertical MOSFETs are vertical structures that allow components to withstand both high voltage and high current operating conditions. The voltage that a power vertical MOSFET can withstand is a function of the doping concentration of the dopant and the thickness of the epitaxial layer, and the current that can pass is related to the channel width of the component. The wider the channel, the more current can be accommodated. . For a planar MOSFET, the amount of current that can be tolerated and the amount of breakdown voltage are related to the length and width of its channel. For a vertical MOSFET, the area of the component is approximately proportional to the current it can hold, and the thickness of the epitaxial layer is proportional to its breakdown voltage (positive correlation).

The typical power vertical type MOS field-effect transistor 10 shown in the first figure is constructed on an N ⁺ -type substrate 12 using an N ^- type epitaxial layer 14, wherein the gate 16 and the source 18 are constructed at the N ^- type epitaxial layer 14 above. U.S. Patent No. 7,019,358 also discloses a power vertical type MOS field effect transistor having a structure substantially the same as that of the first figure. The on-resistance of the power vertical type MOS field-effect transistor 10 is a function of the voltage rating of the material of the N ^- type epitaxial layer 14, that is, a higher rated voltage causes a higher voltage. On-resistance. Further, the N ^- type epitaxial layer based rated voltage of the 14 N ^- type doping concentration (doping concentration) and its function of the thickness of the epitaxial layer 14. The on-resistance of the power vertical type MOS field-effect transistor 10 is typically varied by adjusting the thickness of the N ^- type epitaxial layer 14 at a given doping concentration.

In addition, DMOS is an abbreviation for double-diffused MOSFET, since most power vertical MOSFETs are fabricated in this way. Therefore, the power vertical double-diffused gold-oxygen half field effect transistor can be simply referred to as a Power VDMOSFET (Power Vertical Double-Diffused MOSFET). The VDMOSFET, such as the power vertical type MOS field-effect transistor 10 shown in the first figure, is mostly used as a switch in applications, particularly in high frequency systems, so to increase the component switching speed, the gate charge must be reduced. The so-called gate charge is the charge required to charge the element parasitic capacitance (such as the insulating layer) in order to change the element from the off state to the on state, and in particular, the area where the element gate is overlapped is proportional to the charging area of the parasitic capacitor. Therefore, the gate charge is generally reduced by shortening or removing the area of the gate pad overlap. The split gate structure is thus proposed to reduce the gate charge and increase the switching speed, but the split gate structure induces a high electric field region on the surface, causing the component to collapse early and causing reliability problems.

The second and third figures show the gate charge conduction action diagram and the component parasitic capacitance distribution diagram. The gate charge has a direct effect on the switching action of the component. Excessive gate charge increases the switching time and switching loss, which will limit the frequency of component operation. The action of the gate charge can be explained by the following analysis:

The second graph is divided into four sections, and the third interval (t _C ~t _D ) is the Q _gd portion of the component until the on current reaches I _D(MAX) and the drain is shorted to the source. In this interval, since the bungee-to-gate feedback passes through the capacitance between the gate and the source, that is, the capacitance of the depletion region generated at the bottom of the well region, the voltage is almost constant in this interval. Therefore, the gate voltage in this interval is in a horizontal state. Since the drain voltage of the interval component is not immediately short-circuited with the source to make the component fully conductive, the switching speed of the component will be determined by the length of time of the interval. In addition, since the on-current of the interval has reached the maximum value and the component is not immediately turned on, power loss is generated, which is generally referred to as switching loss, and the magnitude is also determined by the length of time in the interval, so that the switching speed of the component is known. And the operating loss is affected by the gate and the drain. According to the parasitic capacitance distribution in the third figure, the size of the gate-drain capacitor (C _GD ) determines the amount of gate-drain charge (Q _GD ). Since C _GD belongs to the plate capacitor, Reducing the capacitance by reducing the area of the parallel plate, that is, the reduction of Q _GD can be achieved by reducing the gate area of the element, so a split gate structure is usually used to reduce the amount of Q _GD . However, the split gate structure can reduce the Q _GD and increase the switching speed, but the end thereof induces a high electric field region, which leads to a decrease in the withstand voltage of the component and reliability.

Accordingly, it would be desirable to provide an improved structure having a split gate vertical MOS transistor structure to overcome the above-described deficiencies.

The invention provides a structure of a split gate vertical type MOS transistor, which is combined with a pair of floating N-type/P-type shallow doped well regions in the structure thereof, and the gate charge can be reduced by the device structure of the invention In turn, the component switching rate is increased and the switching loss is reduced, and at the same time, the structural design of the floating N-type/P-type shallow doping well region is adopted to prevent a drop in the breakdown voltage and an increase in the on-resistance value of the suppression element.

The invention provides a manufacturing method for a structure of a split gate vertical type MOS transistor, which uses a same mask to define a source, a separate gate structure and a floating N-type/P in different process steps. The location of the shallow doped well zone simplifies process steps and reduces manufacturing costs.

According to the above, the present invention provides a structure of a split gate vertical type MOS transistor, comprising: a first conductivity type substrate; and a second conductivity type floating shallow doping well region formed in the In the substrate, wherein the second conductivity type is electrically opposite to the first conductivity type; a first conductivity type floating shallow doping well region is formed under the second conductivity type doping well region and surrounds the a second conductive type floating shallow doped well region; a split gate vertical type gold oxide semi-transistor formed on the substrate, wherein the split gate vertical type gold oxide semi-transistor comprises: a pair Separating gates are respectively formed on opposite sides of the second conductive floating shallow doping well region above the substrate and partially overlapping the second conductive floating shallow doping well region and a pair of first conductive type source Formed on each of the gates below the side of the second conductive type floating shallow doping well region, a pair of gate oxide layers are respectively formed between the respective gates and the substrate and a pair of first Conductive channel regions are respectively located in the respective first conductivity type source and the second channel Between the floating-type lightly doped well region; and a pair of second doped well region of the first conductivity type, respectively formed on the individual lines of the first conductivity type beneath the source and a first conductivity type surrounding the source.

The invention provides a method for fabricating a structure of a split gate vertical type MOS transistor comprising: providing a first conductive type substrate; forming a gate oxide layer over the substrate; forming a conductive gate layer Formed above the gate oxide layer; forming a pair of second conductivity type first doped well regions respectively The conductive gate layer is opposite to the opposite side, wherein the electrical conductivity of the second conductivity type is opposite to the electrical conductivity of the first conductivity type; forming a patterned photoresist layer over the gate oxide layer and the substrate; forming a And the first conductive type source is respectively disposed in the second conductive type first doping well region corresponding to the lower side of the opposite side of the conductive gate layer; the conductive gate layer and the gate oxide layer are patterned and etched to form a pair of split gates between the pair of first conductivity type sources; forming a second conductivity type floating shallow doping well region below the pair of split gates, and the second conductive The floating shallow doped well region overlaps with the individual gate portions respectively; forming a first conductive floating shallow doped well region below the second conductive floating shallow doped well region and surrounding the first a two-conductivity floating shallow doped well region; and removing the patterned photoresist layer.

In another aspect, the present invention provides another method for fabricating a structure of a split gate vertical type MOS transistor, which is characterized in that the first conductive type floating shallow doped well region and the second conductive type float shallow The formation steps of the doped well regions are interchanged, and the remaining steps are the same as those of the above manufacturing method steps.

The fourth figure is a schematic cross-sectional view of an embodiment of the structure of the split gate vertical type MOS transistor element of the present invention. 4A to 4G are schematic cross-sectional structural views respectively corresponding to the respective process stages of the structure of the split gate vertical type MOS transistor of the fourth embodiment of the present invention. The following is a detailed description of the structure of the split gate vertical type MOS transistor element and the method of manufacturing the same according to the fourth and fourth A to fourth G drawings.

Please refer to the fourth figure, which shows a cross-sectional view of an N-channel split gate vertical MOS device structure 40, including an N ⁺ type <100> substrate 400; an N ^- type epitaxial a layer 402 is formed on the N ⁺ type <100> substrate 400; a P ^- type floating shallow doping well region 414 is formed in the N ^- type epitaxial layer 402; an N ^- type floating shallow doping a well region 416 formed under the P ^- type floating shallow doping well region 414 and covering the P ^- type floating shallow doping well region 414; and a separate gate vertical type gold oxide semi-transistor Formed above the N ⁺ type <100> substrate 400. The split gate vertical MOS transistor comprises: a pair of separated polysilicon gates 406 respectively formed over the N ⁺ -type <100> substrate 400, the P ^- type floating shallow doped well region 414 is opposite The P ^- type floating shallow doped well region 414 is laterally and partially overlapped; a pair of N ⁺ -type source electrodes 412 are respectively formed on the respective polycrystalline germanium gates 406 with respect to the P ⁻ -type floating shallow doped well region 414 A pair of gate oxide layers 404 are respectively formed between the individual polysilicon gates 406 and the N ^- type epitaxial layer 402; a pair of P ^- type doping well regions 408 are formed separately The N ⁺ -type source 412 is underneath and covers the N ⁺ -type source 412 ; and a pair of P ⁺ -type doped well regions 420 are respectively formed on the N ⁺ -type source 412 and the P ⁻ -type doping Between well regions 408, and the P ^- type doped well region 408 encapsulates the P ⁺ type doped well region 420. A pair of N-type channel regions are respectively located between the respective N ⁺ -type source 412 and the P ^- type floating shallow doped well region 414. In the structure of the present invention, the channel layer is formed only under the gate oxide layer 404. The surface of the P ^- type doped well region 408.

Additionally, a borophosphorus bismuth (BPSG) layer 418 is overlying the pair of separated polysilicon gates 406 to provide electrical isolation between the pair of separated polysilicon gates 406 and the pair of N ⁺ source 412. A source metal layer 422 overlies the borophosphon glass (BPSG) dielectric layer 418 and contacts the pair of N ⁺ source 412 to provide electrical communication between the pair of N ⁺ source 412 and the outside. Furthermore, a drain metal layer (not shown) is located below the N ⁺ type <100> substrate 400. In the present invention, the N ⁺ -type <100> substrate 400 is used as a drain of the split gate vertical MOS transistor, and the drain metal layer provides electricity between the drain and the outside. Sexual conduction.

The above-described split gate vertical MOS device structure 40 provided by the present invention overlaps the portion of the gate (ie, the N ⁺ type <100> substrate 400) by removing the polysilicon gate 406 The region is formed to form the aforementioned split gate structure, thereby reducing the interpole charge, thereby shortening the switching time of the component and reducing the loss of power during the switching process. In addition, the present invention avoids electric field concentration at the edge of the split gate structure by forming the P ^- type floating shallow doped well region 414 under the split gate structure, and further forms the N ^- type floating shallow A doped well region 416 is below the P ^- type floating shallow doped well region 414 and covers the P ^- type floating shallow doped well region 414 to suppress an increase in the on-resistance value of the device.

The foregoing split gate vertical type MOS transistor structure 40 provided by the invention can increase the component switching rate, reduce the power loss during the switching process, suppress the breakdown voltage drop, and rapidly increase the on-resistance value of the component, thereby making the present invention The above-described split gate vertical type MOS semi-transistor element can be applied to a high frequency system.

On the other hand, although the present invention is exemplified by the above-described N-channel split gate vertical MOS transistor structure 40, the present invention can also provide a P-channel split gate vertical type MOS. The transistor component structure; wherein the P channel has a split gate vertical type MOS transistor structure and the conductive structure of each region structure corresponding to the N channel has a split gate vertical MOS transistor structure 40 Sex lines are opposite each other.

The following is a detailed description of the manufacturing method of the N-channel split gate vertical MOS transistor structure 40 of the fourth figure.

Please refer to FIG. A fourth manufacturing method of the present invention is first prepared a line N ⁺ type <100> substrate 400, the N ⁺ type <100> substrate 400 may be a semiconductor material such as silicon carbide (SiC) or a silicon, germanium Or a bismuth composition (SiGe) material; then a low doping concentration N ^- type epitaxial layer 402 such as tantalum carbide (SiC) or germanium (SiGe) material is grown on the N ⁺ type <100> substrate 400. A high voltage resistant body is then thermally oxidized to form an oxide layer 404 over the low doping concentration N ^- type epitaxial layer 402 and a polysilicon layer 406 is deposited over the oxide layer 404. The oxide layer 404 is subsequently provided as a gate oxide layer having a dielectric constant of 3.9. In addition, the present invention may also use a material having a dielectric constant greater than 3.9 such as tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (HfO _x ), or tantalum nitride (Si ₃ N ₄ ) and hafnium oxide (HfO _x ). The oxide layer 404 is replaced by a stacked insulating layer structure for subsequent supply of a gate oxide layer. Referring to FIG. 4B, the gate oxide layer 404 and the polysilicon gate 406 are formed by etching using a photomask, and then a pair of P ^- type doped well regions 408 are formed by implanting boron (Boron) ions. The low doping concentration N ^- type epitaxial layer 402 is respectively below the opposite side of the polysilicon gate 406. Referring to FIG. 4C, a patterned photoresist layer 410 is formed over the gate oxide layer 404 and the N ⁺ type <100> substrate 400 to implant Arsenic ions and temper to form a pair of N ⁺ Type source 412 is respectively in the P ^- -type doped well region 408 below the opposite side of the polysilicon gate 406. At this time, the patterned photoresist layer 410 simultaneously defines a discrete gate structure position, that is, the portion of the polysilicon gate 406 and the gate oxide layer 404 are removed by dry etching to form a separate gate structure. As shown in the fourth D picture. Referring to FIG. 4E, boron ions are implanted in the low doping concentration N ^- type epitaxial layer 402 between the pair of split gates 406 and appropriately driven to form a pair of floating contacts. ^- type lightly doped well region 414, and the floating P ^- doped type shallow well region 414 and 406 partially overlap the respective gate. Next, phosphorus ions are doped under the floating P ^- -type shallow doped well region 414 to form a floating N ^- -type shallow doped well region 416 and the floating P ^- -type shallow doped well region 414 is coated. Thereafter, the patterned photoresist layer 410 is removed. When the dopant implantation step of forming the floating P ^- -type shallow doping well region 414 and the floating N ^- -type shallow doping well region 416 is performed, the dopant enters the P ^- -type doping well region 408 at the same time. And the N ⁺ -type source 412, but the concentration of the floating P ^- -type shallow doped well region 414 and the floating N ^- -type shallow doped well region 416 is lower than the P ^- -type doped well region 408 and The N ⁺ -type source 412 does not affect the characteristics of the N-channel split gate vertical MOS transistor 41 of the present invention. Referring to the fourth F diagram, a boron phosphide glass (BPSG) layer 418 is deposited over the foregoing split gate structure as an electrode insulating layer. Please refer to the fourth G picture, and then use a patterned photoresist layer as a mask to form a pair of high-concentration P ⁺ -type doping well regions 420 at the high-temperature implanted boron ions, respectively, and the N ⁺ -type source 412 and The P ^- type doped well region 408 is between and the P ^- type doped well region 408 encapsulates the high concentration P ⁺ type doped well region 420. Finally, aluminum is deposited to form a source metal layer 422 over the borophosphon glass (BPSG) layer 418. In this way, the main structure of the N-channel split gate vertical MOS transistor 41 of the present invention is completed.

The method for manufacturing the split gate vertical MOS transistor structure 40 provided by the present invention can use the same patterned photoresist layer 410 to define a source and a separate gate structure in different process steps. The position of the shallow doped N-type/P-type well region is floated, which simplifies the process steps and reduces manufacturing costs.

Further, according to another embodiment of the manufacturing method of the present invention, in the fourth E diagram, the steps of forming the floating P ^- -type shallow doping well region 414 and the floating N ^- -type shallow doping well region 416 are mutually reversed. The remaining process steps are the same as those of the above manufacturing method.

In addition, another embodiment of the manufacturing method according to the present invention can also be applied to an insulated gate bipolar transistor (IGBT) device, as shown in the sixth figure, wherein the N ⁺ type is <100. The substrate 400 is replaced by a P ⁺ type <100> substrate 600, and the insulating gate bipolar transistor element structure fabrication steps are the same as those illustrated in the fourth A to fourth G diagrams and variations thereof.

The fifth A diagram is an internal electric field diagram of a conventional vertical type power MOS field effect transistor element. The fifth B diagram is an internal electric field diagram of the split gate vertical type power MOS field effect transistor device of the present invention. It can be seen from the fifth A diagram and the fifth B diagram that the electric field distribution of the split gate vertical type power metal oxide half field effect transistor of the present invention is averaged during operation, and there is no induction between the separated individual gates. The problem of high electric field, in addition to effectively reducing the gate charge, can maintain the breakdown voltage and improve component reliability. The fifth C diagram corresponds to the surface structure of the fifth structure and the fifth B diagram, respectively. The surface electric field curve of the structure of the invention extends along the horizontal direction of the surface of the epitaxial layer, and it can be seen that two separate gates are adjacent in the structure of the present invention. The electric field at a corner of a floating P ^- type shallow doped well/N ^- type shallow doped well is similar to that of the conventional one, and no high electric field is induced.

The description of the present invention can be applied to a field effect transistor structure using N-type (N-channel) or P-type (P-channel) as a substrate, and those skilled in the art can appropriately modify the present invention without departing from the present invention. The spirit and scope of the invention. In addition, the above description is only for the specific embodiments of the present invention, and is not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications that do not depart from the spirit of the present invention should be included. It is within the scope of the following patent application.

10. . . Power vertical type gold oxide half field effect transistor

16. . . Gate

18. . . Source

12. . . N ⁺ type substrate

14. . . N ^- type epitaxial layer

40‧‧‧N-channel with split gate vertical galvanic semi-transistor element structure

400‧‧‧N ⁺ type <100> substrate

402‧‧‧N ^- type epitaxial layer

404‧‧‧ gate oxide layer

406‧‧‧ gate

408‧‧‧P ^- type doping well area

410‧‧‧ patterned photoresist layer

412‧‧‧N ⁺ source

414‧‧‧Floating P ^- type shallow doped well area

416‧‧‧Floating N ^- type shallow doped well area

418‧‧‧Boron phosphate glass layer

420‧‧‧P ⁺ type doping well area

422‧‧‧ source metal layer

The first figure is a schematic cross-sectional view of a conventional vertical type power MOS field effect transistor structure.

The second figure is a gate charge conduction operation diagram of a conventional vertical type power MOS field effect transistor.

The third figure is a component parasitic capacitance distribution diagram of a conventional vertical type power MOS field effect transistor.

The fourth figure is a schematic cross-sectional view showing the structure of a split gate vertical type gold-oxygen half field effect transistor element according to an embodiment of the present invention.

The fourth to fourth G diagrams are schematic cross-sectional views of the manufacturing method of the separate gate vertical type gold-oxygen half field effect transistor element structure of the fourth embodiment of the present invention.

The fifth A diagram is an internal electric field diagram of a component of a conventional vertical type power MOS field effect transistor.

Figure 5B is an internal electric field diagram of a component of the split gate vertical type power MOS field effect transistor of the present invention.

The fifth C diagram corresponds to the surface electric field curve of the structure of the present invention extending along the horizontal direction of the surface of the epitaxial layer, respectively, corresponding to the conventional structure of the fifth A diagram and the fifth B diagram.

Figure 6 is a schematic cross-sectional view of an insulated gate bipolar transistor (IGBT) device in accordance with an embodiment of the present invention.

40. . . N channel with separate gate sagging type MOS semi-transistor element structure

400. . . N ⁺ type <100> substrate

402. . . N ^- type epitaxial layer

404. . . Gate oxide layer

406. . . Gate

408. . . P ^- type doping well area

412. . . N ⁺ source

414. . . Floating ^- P ^- type shallow doping well area

416. . . Floating ^- N ^- type shallow doping well area

418. . . Boron phosphate glass layer

420. . . P ⁺ type doping well area

422. . . Source metal layer

Claims (27)

A structure of a split gate vertical type MOS transistor, comprising: a first conductivity type substrate; a second conductivity type floating shallow doping well region formed in the substrate, wherein the second The conductive type is opposite to the first conductivity type; a first conductive type floating shallow doping well region is formed under the second conductive floating shallow doped well region and surrounds the second conductive type Floating shallow doped well region; a separate gate vertical type MOS transistor formed above the substrate, wherein the split gate vertical MOS transistor comprises: a pair of separated gates Forming on the opposite side of the second conductive type floating shallow doping well region above the substrate and partially overlapping the second conductive floating shallow doping well region, and forming a pair of first conductive type sources respectively The gate electrode is formed below the side of the second conductive type floating shallow doping well region, and a pair of gate insulating layers are respectively formed between the gate and the substrate and a pair of first conductive type channel regions. Each of the first conductive type source and the second conductive type are shallowly doped Between the region; and a pair of second conductivity type first doped well region below the electrode lines were formed in the respective first conductivity type and source of the first conductivity type cladding source. The structure of the split gate vertical type MOS device according to claim 1, wherein the first conductive type epitaxial layer is formed on the substrate and the vertical gate type gold Between oxygen and semi-transistors. The structure of the split gate vertical type MOS transistor according to claim 1, wherein the second conductive type second doping region is formed in each of the first conductivity types. Between the source and the corresponding first doped well region of the second conductivity type, wherein the second doped well region is doped The concentration is higher than the dopant concentration of the first doped well region. The split gate vertical type MOS transistor structure as described in claim 2, further comprising a pair of second conductivity type second doped well regions respectively formed on the respective first conductivity type Between the source and the corresponding second doped well region of the second conductivity type, wherein the dopant concentration of the second doped well region is higher than the dopant concentration of the first doped well region. The split gate vertical type MOS transistor structure according to claim 1, wherein the first conductivity type electrical system is either N-type conductivity or P-type conductivity. The split gate vertical MOS transistor structure according to the second aspect of the invention, wherein the first conductivity type electrical system is any one of N-type conductivity and P-type conductivity. The method of claim 1 , wherein the second conductivity type floating shallow doping well region has a lower dopant concentration than the second conductivity type The doping concentration of a doped well region. The method of claim 2, wherein the second conductivity type floating shallow doping well region has a lower dopant concentration than the second conductivity type The doping concentration of a doped well region. The method of claim 3, wherein the second conductivity type floating shallow doping well region has a lower dopant concentration than the second conductivity type The doping concentration of a doped well region. The method of claim 4, wherein the second conductivity type floating shallow doping well region has a dopant concentration lower than the second conductivity type. The doping concentration of a doped well region. The method of claim 1, wherein the first conductivity type floating shallow doping well region has a lower dopant concentration than the first conductivity type source; Extreme dopant concentration. The method of claim 2, wherein the first conductivity type floating shallow doping well region has a lower dopant concentration than the first conductivity type source Extreme dopant concentration. The structure of the split gate vertical type MOS transistor according to claim 1, wherein the gate insulating layer is a ruthenium dioxide layer, a tantalum nitride (Si ₃ N ₄ ) layer, and an oxide layer. A cross-layer stacked structural layer of a hafnium (HfO _x ) layer or a tantalum nitride (Si ₃ N ₄ ) layer/yttria (HfO _x ) layer. An insulated gate bipolar transistor component includes: a first conductivity type substrate; a first conductivity type floating shallow doped well region formed in the substrate; and a second conductivity type floating shallow doping a well region formed under the first conductive floating shallow doped well region and surrounding the first conductive floating shallow doped well region, wherein the second conductive type is electrically opposite to the first conductive type a separate gate vertical MOS transistor formed over the substrate, wherein the split gate vertical MOS transistor comprises: a pair of separate gates formed over the substrate The first conductive type floats on opposite sides of the shallow doped well region and partially overlaps the first conductive floating shallow doped well region, and a pair of second conductive type sources are respectively formed on the respective gates relative to A pair of first insulating type floating shallow doping well regions, a pair of gate insulating layers are respectively formed between the respective gates and the substrate, and a pair of second conductive type channel regions are respectively located at the respective ones a second conductive source between the first conductive type floating shallow doped well region; and a Doping a first conductive type first well region under the electrode lines were formed on the respective second conductivity type and source of the second conductivity type cladding source. The insulated gate bipolar transistor device of claim 14, further comprising a second conductivity type epitaxial layer formed between the substrate and the separate gate vertical MOS transistor . Insulated gate bipolar electric as described in claim 14 a crystal element, further comprising a pair of first conductivity type second doping well regions respectively formed between the respective second conductivity type source and the corresponding first conductivity type first doping well region, wherein the The dopant concentration of the second doped well region is higher than the dopant concentration of the first doped well region. The insulated gate bipolar transistor component of claim 14, wherein the first conductivity type is P-type. A method for manufacturing a split gate vertical type MOS transistor comprises: providing a first conductive type substrate; forming a gate insulating layer over the substrate; forming a conductive gate layer on the gate a pair of second conductive type first doping well regions respectively formed below the opposite sides of the conductive gate layer, wherein the electrical conductivity of the second conductivity type is opposite to the electrical conductivity of the first conductivity type; Forming a patterned photoresist layer over the gate oxide layer and the substrate; forming a pair of first conductivity type source respectively corresponding to the second conductivity type first doping well below the opposite side of the conductive gate layer a pattern etching the conductive gate layer and the gate oxide layer to form a pair of separate gates between the pair of first conductivity type sources; forming a second conductivity type floating shallow doping a well region is below the pair of split gates, and the second conductive type floating shallow doped well region overlaps the individual gate portions respectively; forming a first conductivity type floating shallow doping The well region is below the second conductivity type floating shallow doped well region and is coated Floating a second conductivity type lightly doped well region; and removing the patterned photoresist layer. [19] The method for manufacturing a split gate vertical type MOS transistor according to claim 18, wherein the gate is formed A first conductive epitaxial layer is formed over the substrate before the edge layer. The method for manufacturing a split gate vertical type MOS transistor according to claim 18, comprising forming a pair of second conductivity type second doping regions respectively for the respective first conductive The source is between the corresponding first doped well region of the second conductivity type. The method for manufacturing a split gate vertical type MOS transistor according to claim 19, comprising forming a pair of second conductivity type second doping regions respectively for the respective first conductive The source is between the corresponding first doped well region of the second conductivity type. The method for manufacturing a split gate vertical type MOS transistor according to claim 18, wherein the gate insulating layer is composed of a ruthenium dioxide layer and a tantalum nitride (Si ₃ N ₄ ) layer. Any of the yttrium oxide (HfO _x ) layer or the tantalum nitride (Si ₃ N ₄ ) layer/yttria (HfO _x ) layer cross-layer stack structure layer. A method for manufacturing a split gate vertical type MOS transistor comprises: providing a first conductive type substrate; forming a gate insulating layer over the substrate; forming a conductive gate layer on the gate a pair of second conductive type first doping well regions respectively formed below the opposite sides of the conductive gate layer, wherein the electrical conductivity of the second conductivity type is opposite to the electrical conductivity of the first conductivity type; Forming a patterned photoresist layer over the gate oxide layer and the substrate; forming a pair of first conductivity type source respectively corresponding to the second conductivity type first doping well below the opposite side of the conductive gate layer Forming and etching the conductive gate layer and the gate oxide layer to form a pair of separate gates between the pair of first conductivity type sources; forming a first conductivity type floating shallow doping a well area below the pair of separate gates; Forming a second conductive floating shallow doped well region in the first conductive floating shallow doped well region, and the second conductive floating shallow doped well region and the respective gate portion respectively Overlapping; and removing the patterned photoresist layer. The method for manufacturing a split gate vertical type MOS transistor according to claim 23, comprising forming a first conductivity type epitaxial layer on the substrate before forming the gate insulating layer. Above. The method for manufacturing a split gate vertical type MOS transistor according to claim 23, comprising forming a pair of second conductivity type second doping regions respectively for the respective first conductive The source is between the corresponding first doped well region of the second conductivity type. The method for manufacturing a split gate vertical type MOS transistor according to claim 24, comprising forming a pair of second conductivity type second doping regions respectively for the respective first conductive The source is between the corresponding first doped well region of the second conductivity type. The method for manufacturing a split gate vertical type MOS transistor according to claim 23, wherein the gate insulating layer is composed of a ruthenium dioxide layer and a tantalum nitride (Si ₃ N ₄ ) layer. Any of the yttrium oxide (HfO _x ) layer or the tantalum nitride (Si ₃ N ₄ ) layer/yttria (HfO _x ) layer cross-layer stack structure layer.