201034188 六、發明說明： 【發明所屬之技術領域】 本發明係關於金氧半場效電晶體，尤其係關於功率垂 直型雙擴散金氧半場效電晶體。 【先前技術】 金屬-氧化層-半導體-場效電晶體，簡稱金氧半場效電 晶體（Metal-Oxide-Semiconductor Field-Effect Transistor, φ mosfet)是一種可以廣泛使用在模擬電路與數字電路的場 效電晶體（field-effect transistor)。MOSFET 依照其「通道」 的極性不同，可分為N-type與P-type的MOSFET，通常又 稱為NMOSFET與PMOSFET，其他簡稱尚包括NMOS FET、PMOS FET、nMOSFET、pMOSFET 等。 第一圖係一典型功率垂直型金氧半場效電晶體1〇的截 面結構圖。功率垂直型MOSFET和前述的MOSFET元件在 結構上就有著顯著的差異。一般積體電路裡的MOSFET都 是平面式（planar)的結構，而功率垂直型MOSFET則是垂 • 直式（vertical)的結構，讓元件可以同聘承受高電壓與高 電流的工作環境。一個功率垂直型MOSFET能耐受的電壓 是掺質掺雜濃度與遙晶層（epitaxial layer)厚度的函數，而 能通過的電流則和元件的通道寬度有關，通道越寬則能容 納越多電流。對於一個平面結構的MOSFET而言，能承受 的電流以及崩潰電壓的多寡都和其通道的長寬大小有關。 對垂直結構的MOSFET來說，元件的面積和其能容納的電 流大約成正比，蠢晶層厚度則和其崩潰電壓成正比（正相 關）。 第一圖所示的典型功率垂直型金氧半場效電晶體1〇係 4 201034188 在一 N+型基板12上使用N-型磊晶層14建構出來，其中閘 極16及源極18係建構在該N-型磊晶層14上方。美國專利 第7,019,358號也揭露出主要結構相同於第一圖的功率垂直 型金氧半場效電晶體。該功率垂直型金氧半場效電晶體1〇 的開啟電阻(on-resistance)係該N-型磊晶層丨4材質的額定電 壓(voltage rating)的函數，亦即較高的額定電壓會造成較高 的開啟電阻(on-resistance)。再者，該N-型磊晶層η的額定 電壓係該Ν型遙晶層14摻雜濃度(doping concentration)與 籲其厚度的函數。通常在給定的摻雜濃度下，藉由調整該Ν-型磊晶層14的厚度來改變該功率垂直型金氧半場效電晶體 . 1〇 的開啟電阻（on-resistance)。 此外 ’ DMOS 是雙重擴散 MOSFET (double-Diffused MOSFET)的縮寫，由於大部分的功率垂直型MOSFET都 是採用這種製作方式完成的。所以功率垂直型雙重擴散金 氧半場效電晶體可簡稱為power VDMOSFET(Power201034188 VI. Description of the Invention: [Technical Field] The present invention relates to a gold-oxygen half field effect transistor, and more particularly to a power vertical type double-diffused gold-oxygen half field effect transistor. [Prior Art] Metal-oxide-semiconductor-field effect transistor, referred to as Metal-Oxide-Semiconductor Field-Effect Transistor (φ mosfet) is a field that can be widely used in analog circuits and digital circuits. Field-effect transistor. MOSFETs are classified into N-type and P-type MOSFETs according to the polarity of their "channels". They are also commonly referred to as NMOSFETs and PMOSFETs. Others include NMOS FETs, PMOS FETs, nMOSFETs, and pMOSFETs. The first figure is a cross-sectional structure diagram of a typical power vertical type gold-oxygen half field effect transistor. There are significant differences in the structure between the power vertical MOSFET and the aforementioned MOSFET component. The MOSFETs in general integrated circuits are planar, while the power vertical MOSFETs are vertically vertical, allowing components to withstand high voltage and high current operating conditions. The voltage that a power vertical MOSFET can withstand is a function of the doping concentration of the dopant and the thickness of the epitaxial layer, and the current that can pass is related to the channel width of the component. The wider the channel, the more current can be accommodated. . For a planar MOSFET, the amount of current that can be tolerated and the amount of breakdown voltage are related to the length and width of its channel. For a vertically structured MOSFET, the area of the component is approximately proportional to the current it can hold, and the thickness of the doped layer is proportional to its breakdown voltage (positive correlation). The typical power vertical type MOS field-effect transistor 1 34 4 201034188 shown in the first figure is constructed on an N+ type substrate 12 using an N-type epitaxial layer 14, wherein the gate 16 and the source 18 are constructed. Above the N-type epitaxial layer 14. U.S. Patent No. 7,019,358 also discloses a power vertical type MOS field effect transistor having a structure substantially the same as that of the first figure. The on-resistance of the power vertical type MOS field-effect transistor is a function of the voltage rating of the N-type epitaxial layer ,4 material, that is, a higher rated voltage causes Higher on-resistance. Furthermore, the rated voltage of the N-type epitaxial layer η is a function of the doping concentration of the germanium-type crystal layer 14 and the thickness thereof. The on-resistance of the power vertical type MOS field effect transistor is usually changed by adjusting the thickness of the Ν-type epitaxial layer 14 at a given doping concentration. In addition, 'DMOS is an abbreviation for double-diffused MOSFET, since most of the power vertical MOSFETs are fabricated in this way. Therefore, the power vertical type double-diffused MOS half-field effect transistor can be referred to as power VDMOSFET (Power).
Vertical Double-Diffused MOSFET)。VDMOSFET 例如第一 圖所示的功率垂直型金氧半場效電晶體10在應用上多半做 ❿ 為開關使用，特別是在高頻系統中，因此為增加元件切換 速度’則必須減少閘極電荷。所謂的閘極電·荷是為了將元 件由關閉態轉為導通態而對元件寄生電容(如絕緣層）充電 所需的電街’特別是元件閘j：及極重疊的面積與該寄生電容 充電面積成正比。因此通常利用縮短或移除閘汲極重疊的 面積的方式來降低閘極電荷。分離式閘極結構因而被提出 降低閘極電荷，提高切換速度，但分離式閘極結構卻會在 表面感應一高電場區域，使元件提早崩潰並造成可靠度問 題。 第二圖及第三圖所示分別為閘極電荷導通動作圖及元 件寄生電容分佈圖。閘極電荷對元件之切換動作有直接影 201034188 響，過多的閘極電荷會增加切換時間及 元件操作的頻率。而對於閘極電荷之 、將限制 來解釋： 乍，可以下列分析 將第二圖分為四個區間，第三區 達ID(MAX)開始’到汲極與源極短路為止C，：為：3電流到 部分。在此區間内’由於汲極到 2通二：Q: 源極間的，，也就是井區底部所產生的空 此使得電壓在此區·現幾乎為定值 j 間之閘極電壓呈現水平狀態。由於此 ^此在此區 並非立即與源極短路使元件完全導通，；此元 度將由此區間的時間長度所決定。此外，由 通電流已達最大值，且元件並非立即導通，因 率損耗，-般稱其為切換損耗，此大小亦受 = 長度所蚊，因此可知元件的切換速度及操 閘極及汲極的影響。由第三圖之寄㈣容分佈可知 (gate-drain capacitor, CGD) ^ ^ (gate-dram charge, QGD)的量，由於cgd屬於平板電容， 藉由減少平行板面積來降低電容值’亦即知的降低Vertical Double-Diffused MOSFET). The VDMOSFET, for example, the power vertical type MOS field-effect transistor 10 shown in the first figure is mostly used for switching, especially in high-frequency systems, so the gate charge must be reduced in order to increase the component switching speed. The so-called gate electric charge is the electric street required to charge the parasitic capacitance (such as the insulating layer) of the component from the off state to the on state, especially the area of the element gate j: and the pole overlap and the parasitic capacitance. The charging area is proportional. Therefore, the gate charge is usually reduced by shortening or removing the area of the gate pad overlap. The split gate structure has therefore been proposed to reduce the gate charge and increase the switching speed, but the split gate structure induces a high electric field on the surface, causing the component to collapse early and causing reliability problems. The second and third figures show the gate charge conduction action diagram and the component parasitic capacitance distribution diagram. The gate charge has a direct impact on the switching action of the component. 201034188, excessive gate charge increases the switching time and the frequency of component operation. For the gate charge, the limit will be explained: 乍, the second graph can be divided into four sections by the following analysis. The third zone reaches the ID (MAX) start 'to the drain of the drain and the source C, C: 3 current to the part. In this interval, 'because of the bungee to the 2nd pass: Q: between the sources, that is, the space generated at the bottom of the well, this makes the voltage in this area. The gate voltage is now almost constant j. status. Since this is not immediately short-circuited with the source in this region, the component is fully turned on; this factor will be determined by the length of time in this interval. In addition, since the current has reached the maximum value and the component is not immediately turned on, the rate loss is generally referred to as the switching loss. This size is also affected by the length of the mosquito, so the switching speed of the component and the gate and the drain are known. Impact. The amount of gate-drain capacitor (CGD) ^ ^ (gate-dram charge, QGD) is known from the third diagram. Since cgd belongs to the plate capacitor, the capacitance value is reduced by reducing the parallel plate area. Reduced knowledge
=1件之問極面積來達成’因此通常利用分離式閑極 、、·。構來減QGD的4。然而分離相極結構雖可減 而提高切換速度，但其末端卻會感應出高 D 件耐壓的降低及可靠度問題。 & 據此，亟待提供一種改良的具分離式 半電晶體元件結構’以克服上述之缺失。？ ^ + ^'金氧 【發明内容】 本發明提供-種具分離式閘極垂直型 件結構，係結合一對浮接 6 201034188 藉本發明元件結構可減少閘極電荷，進而增加元件切換速 率並降低切換損耗，同時藉由前述浮接N型/P型淺摻雜井 區的結構設計’以防止崩潰電壓的下降及抑制元件導通電 阻值的增加。 本發明提供一種具分離式閘極垂直型金氧半電晶體元 件結構的製造方法，其係使用同一光罩在不同製程步驟分 別定義出源極、分離式閘極結構及浮接N型/P型淺摻雜井 區的位置，可簡化製程步驟並降低製造費用。 據上述，本發明提供的一種具分離式閘極垂直型金氧 ® 半電晶體元件結構，係包括：一第一導電型基板；一第二 導電型浮接摻雜井區，係形成於該基板中，其中該第二導 電型電性相反於該第一導電型電性；一第一導電型浮接摻 雜井區，係形成於該第二導電型摻雜井區下方並包圍該第 二導電型浮接摻雜井區；一具分離式閘極垂直型金氧半電 晶體，形成於該基板上方，其中該具分離式閘極垂直型金 氧半電晶體包含：一對分離的閘極分別形成於該基板上方 的該第二導電型浮接摻雜井區相對側並部份重疊該第二導 φ 電型浮接摻雜井區、一對第一導電型源極分別形成於個別 的該閘極相對於該第二導電型浮接摻雜井區一側下方、一 對閘極氧化層分別形成於個別的該閘極與該基板之間及一 對第一導電型通道區分別位於個別的該第一導電型源極與 該第二導電型浮接摻雜井區之間；及一對第二導電型第一 摻雜井區，係分別形成於個別的該第一導電型源極下方並 包圍該第一導電型源極。 本發明提供的一種具分離式閘極垂直型金氧半電晶體 元件結構的製造方法包括：提供一第一導電型基板；形成 一閘極氧化層於該基板上方；形成一導電性閘極層於該閘 極氧化層上方；形成一對第二導電型第一摻雜井區分別於 201034188 該導電性閘極層相對側下方，其中該第二導電型的電性相 反於該第一導電型的電性；形成一圖案化光阻層於該閘極 氧化層及該基板上方；形成一對第一導電型源極分別於該 導電性閘極層相對侧下方對應的該第二導電型第一摻雜井 區中；圖案蝕刻該導電性閘極層及該閘極氧化層，以形成 一對分離式閘極於該對第一導電型源極之間的上方；形成 一第二導電型浮接摻雜井區於該對分離式閘極之間的下 方，並且該第二導電型浮接摻雜井區分別與個別的該閘極 部份重疊；形成一第一導電型浮接摻雜井區於該第二導電 型浮接摻雜井區下方並且包圍該第二導電型浮接摻雜井區 板；及移除該圖案化光阻層。 另一方面，本發明提供另一種具分離式閘極垂直型金 氧半電晶體元件結構的製造方法，其係將前述第一導電型 浮接摻雜井區及第二導電型浮接摻雜井區的形成步驟互 換，其餘步驟與上述製造方法步驟相同。 【實施方式】 第四圖係本發明的具分離式閘極垂直型金氧半電晶體 元件結構的一種實施例的截面結構示意圖。第四A圖至第 四G圖係本發明第四圖的具分離式閘極垂直型金氧半電晶 體元件結構的各製程階段分別對應的截面結構示意圖。下 文係配合第四圖及第四A圖至第四G圖對於本發明具分離 式閘極垂直型金氧半電晶體元件結構及其製造方法的詳細 說明。 請參考第四圖，其係顯示一種N通道具分離式閘極垂 直型金氧半電晶體元件結構40的截面示意圖，係包括一 N+ 型<100>基板400;—：ΝΓ型磊晶層402,形成於該N+型<100> 基板400上；一 P·型浮接淺摻雜井區414，形成於該1ST型 201034188 磊晶層402中；一 N-型浮接淺 型浮接淺摻雜井區414 τ方並包=形成於該p-414;及-具分離式閘極垂直型全型洋接淺摻雜井區 型<ι·基板_上i。該=晶體，形成於該N+ <刚> 基板彻上方的肝型二二^形成於該心 部份重疊該Ρ·型浮㈣料并^ =摻雜井區414相對側並 分別,接換雜井& 4 ;—對N+型源極412=1 pieces of the polar area to achieve 'therefore, usually use separate idle poles, . Constructed to reduce QGD 4. However, the separation of the phase structure can reduce the switching speed, but the end of the structure will induce high voltage resistance and reliability. & Accordingly, there is a need to provide an improved structure having a split-type semi-transistor element to overcome the above-described deficiency. ? ^ + ^ '金氧 [Invention] The present invention provides a separate gate vertical type structure, combined with a pair of floating junctions 6 201034188 by the device structure of the invention can reduce the gate charge, thereby increasing the component switching rate and The switching loss is reduced while the structure design of the floating N-type/P-type shallow doping well region is used to prevent a drop in the breakdown voltage and an increase in the on-resistance value of the suppression element. The invention provides a manufacturing method for a structure of a split gate vertical type MOS transistor, which uses a same mask to define a source, a separate gate structure and a floating N-type/P in different process steps. The location of the shallow doped well zone simplifies process steps and reduces manufacturing costs. According to the above, the present invention provides a split gate vertical type gold oxide® semi-transistor element structure, comprising: a first conductive type substrate; and a second conductive type floating doping well region formed in the In the substrate, wherein the second conductivity type is electrically opposite to the first conductivity type; a first conductivity type floating doping well region is formed under the second conductivity type doping well region and surrounds the first a two-conducting floating-type doped well region; a split-gate vertical-type gold-oxygen semi-transistor formed on the substrate, wherein the split-gate vertical-type gold-oxygen semi-transistor comprises: a pair of separated The gates are respectively formed on opposite sides of the second conductive type floating doping well region above the substrate and partially overlap the second conductive φ electric floating doping well region, and a pair of first conductive type sources are respectively formed A pair of gate oxides are formed between the gate and the substrate and a pair of first conductive channels respectively under the side of the second conductive floating contact doping region The regions are respectively located in the respective first conductive type source and the second lead An electrically floating floating doped well region; and a pair of second conductivity type first doped well regions are respectively formed under the respective first conductivity type source and surrounding the first conductivity type source. The invention provides a method for fabricating a structure of a split gate vertical type MOS transistor comprising: providing a first conductive type substrate; forming a gate oxide layer over the substrate; forming a conductive gate layer Forming a pair of second conductivity type first doping well regions under the opposite sides of the conductive gate layer respectively in 201034188, wherein the second conductivity type is electrically opposite to the first conductivity type Electrically forming a patterned photoresist layer over the gate oxide layer and the substrate; forming a pair of first conductivity type sources respectively corresponding to the second conductivity type below the opposite sides of the conductive gate layer a doped well region; pattern etching the conductive gate layer and the gate oxide layer to form a pair of separate gates between the pair of first conductivity type sources; forming a second conductivity type Floating the doped well region below the pair of split gates, and the second conductive type floating doped well region overlaps with the individual gate portions respectively; forming a first conductive type floating connection The second well type floating surface Heteroaryl well region and surrounding the bottom of the second conductivity type well region doped floating plate; and removing the patterned photoresist layer. In another aspect, the present invention provides another method for fabricating a structure of a split gate vertical type MOS transistor, which is characterized in that the first conductive type floating doping well region and the second conductive type floating doping are doped. The formation steps of the well zone are interchanged, and the remaining steps are the same as those of the above manufacturing method. [Embodiment] FIG. 4 is a schematic cross-sectional view showing an embodiment of a structure of a split gate vertical type MOS transistor of the present invention. 4A to 4G are schematic cross-sectional structural views respectively corresponding to the respective process stages of the structure of the split gate vertical type metal oxide semi-electric crystal element of the fourth embodiment of the present invention. The following is a detailed description of the structure of the split gate vertical MOS transistor element and the method of manufacturing the same according to the fourth and fourth A to fourth G drawings. Please refer to the fourth figure, which is a cross-sectional view showing an N-channel split gate vertical MOS transistor structure 40, including an N+ type <100> substrate 400; -: ΝΓ type epitaxial layer 402, formed on the N+ type <100> substrate 400; a P· type floating shallow doping well region 414 formed in the 1ST type 201034188 epitaxial layer 402; an N-type floating shallow floating connection The shallow doped well region 414 τ square is included in the p-414; and - has a split gate vertical full-type ocean-connected shallow doped well region type <ι·substrate_上i. The crystal, the liver type formed on the N+ <just> substrate, is formed on the core portion overlapping the Ρ· type floating (four) material and ^=the opposite side of the doping well region 414 and respectively Change well &4; - for N+ source 412
別的該多晶娜406相對於該P-型浮接淺 日7側下方；一對閘極氧化層4。4分別形成於 別的該夕曰曰石夕閘極406與該N-型蟲晶層4〇2之間；一對 ㈣雜井區4〇8，係分別形成於個別的該n+型源極412 方並包覆該N+型源極412 ;及一對P+型掺雜井區42〇， 係分別形成於該N+型源極412與該F型摻雜井區4〇8之 間，並且該P型摻雜井區408包覆該p+型摻雜井區42〇。 一對N型通道區係分別位於個別的該N+型源極412與該p_ 型浮接淺摻雜井區414之間，本發明結構中通道層只形成 於閘極氧化層404下方該P-型摻雜井區4〇8的表面。 此外，一硼磷矽玻璃(BPSG)層418係覆蓋於該對分離 的多晶矽閘極406上方，以提供該對分離的多晶石夕閘極4〇6 與該對N+型源極412之間的電絕緣。一源極金屬層422係 覆蓋於該棚磷石夕玻璃(BPSG)介電層418上方並接觸該對n+ 型源極412，以提供該對N+型源極412與外界的電性導通。 再者，一汲極金屬層（未示出）係位於該N+型<1〇〇>基板400 下方。在本發明中’該N+型<100>基板400係供做該具分離 式閘極垂直塑金氧半電晶體的汲極，而該汲極金屬層提供 該汲極與外界之間的電性導通。 本發明提供的前述具分離式閘極垂直型金氧半電晶體 元件結構40係藉由移除該多晶矽閘極406與該汲極（即該 9 201034188 N+型<100>基板400)的部份重疊區 極結構，藉以減少閘極電荷，而 》成刖述分離式閘 降低切換過程功率的損耗。此的切；時間並 式閘極結構下方形成該p-型浮錢摻』^由在刖述分離 分離式閘極結構邊緣產生電場隹區414來避免該 浮接淺摻雜賴楊賴步形成該N_型 包覆該P_型浮接淺摻雜====井^4下方並 的增加。 札414肖財卩制兀件導通電阻值 元件前，分離式閘極垂直型金氧半電晶體 件^=〇可增加％件切換速率、降低切換過程的功率 朋潰電壓下降及元件導通電阻值的快速增加，而 具分離式閘極垂直型金氧半電晶體元件可 方面’本發明雖以前述N通道具分離式閘極垂直 金氧半電晶體兀件結構40做一舉例說明，但本發明同樣 2供:種p通道具分離式閘㈣直型錢半電晶體元件 、、α構，/、中該P通道具分離式閘極垂直型金氧半電晶體元 件結構與前述Ν通道具分離式閘極垂直型金氧半電晶體元 件結構40相對應的各區域結構的導電性係互相相反。 】以下就第四圖的該Ν通道具分離式閘極垂直型金氧半 電晶體元件結構40的製造方法做一詳細說明。 請參考第四Α圖，本發明之製造方法係首先準備一 Ν+ 型<1〇〇>基板400，該Ν+型<100>基板400可由—半導體材 ，紅成，例如碳化石夕（SiC)或s夕、錯或石夕鍺組合物（siGe)材 料；接著在該N+型<100>基板400上成長一低摻雜濃度N-型磊晶層402例如碳化矽（SiC)或矽鍺(SiGe)材料做為耐高 電壓之主體，然後以熱氧化方式成長一氧化層404於該2 摻雜濃度Ν—型磊晶層402上方，並沉積一多晶矽層4〇6"於 201034188 該氧化層404上。該氧化層404係於後續供做閘極氧 其介電係數為3.9。此外，本發明亦可使用介電係數大於θ， 的材料例如氮化矽（Si^4)或氧化铪（Hf〇x)，或者产^ 3·9 (SigN4)與氧化铪(HfOx)相互穿插堆疊的絕緣層結構==矽 氧化層402’以於後續供做閘極氧化層。請參考&四/罔該 接著，使用光罩並利用蝕刻方式形成該閘極氧化層切/ 多晶矽閘極406，接著以佈植硼(B〇r〇n)離子方式曰形 P_型摻雜井區408分別於該多晶矽閘極4〇6相對側^ f 摻雜濃度N-型磊晶層402中。請參考第四c圖，形二闰 案化光阻層410於該閘極氧化層4〇4及該N+s<；^〇> θ 400上方’以佈植砷(Arsenic)離子並回火形成—對ν+ ς j =多晶珍祕406相對侧下方該Γ型摻雜井區 Λ圖案化光阻層41G同日找義出—分離式閘極 lit 著利用乾㈣方式移除部份的該多晶石夕閘 ==:;4°4，以形成分離式閉極結構’= 之圖’接著，於該對分離式閘極406 做雜濃度N••型蟲晶層術中佈植娜子並 接ri淺#雜^ —對洋接P型淺摻雜井區414，並且該浮 ί著分別與個別的該閘極4G6部分重疊。 成一浮接5j^ P型淺摻雜井區414下方再摻雜雜子形 區4Μ接之1逐捧雜井自416並包覆該浮接Ρ·型淺摻雜井 浮接r㈣除該圖案化光阻層410。本發明形成前述 質植入步驟井區414及浮接N_型淺摻雜井區416的摻 及該nO原換質同時會進入該r型摻雜井區408 浮接N-都嘭妓12，但由於該洋接F型淺摻雜井區414及 及該矿型源極::區農，於該Ρ·型摻雜井區4〇8 式閘極垂朗金^ 對本發明㈣通道具分離 、虱半電晶體元件40的特性造成影響。請參 11 201034188 考第四F圖’在前述分離式閘極結構上方沉積—爛碟秒玻 璃(BPSG)層418作為電極絕緣層。請參考第四g圖，接著 使用一圖案化光阻層做為遮罩，以高溫佈植硼離子方式形 成一對高濃度P+型摻雜井區420分別於該N+型源極412 ^ 該Γ型摻雜井區408之間，並且該P-型摻雜井區4〇8包覆 該尚'濃度P型摻雜井區420。最後，沉積銘以形成—源極金 屬層422於該硼磷矽玻璃(BPSG)層418上方。如此一來1 即完成本發明該N通道具分離式閘極垂直型金氧半電晶體 元件40的主要結構。 版 本發明提供的前述具分離式閘極垂直型金氧半電晶體 元件結構40的製造方法，係可使用同一圖案化光阻層二1〇 在不同製程步驟分別定義出源極、分離式閘極結構及浮接 淺摻雜N型/P型井區的位置，故可簡化製程步驟並降低製 造費用。 _衣 此外，根據本發明製造方法的另一實施例，係在第四E 圖中，浮接F型淺摻雜井區414及浮接Ν'型淺摻雜井區416 的形成步驟互相對調，而其餘製程步驟則與上述製造方法 的實施例相同。 此外’根據本發明製造方法的另一實施例，亦可應用 在絕緣閘極雙極性電晶體（Insulated Gate BipolarThe other polycrystalline 406 is lower than the P-type floating shallow 7 side; a pair of gate oxide layers 4. 4 are respectively formed on the other sinus sluice gate 406 and the N-type insect Between the crystal layers 4〇2; a pair of (four) well regions 4〇8, respectively formed on the respective n+ source 412 side and covering the N+ source 412; and a pair of P+ doping well regions 42〇 is formed between the N+ source 412 and the F-type well region 4〇8, respectively, and the P-type well region 408 covers the p+-type doped well region 42〇. A pair of N-type channel regions are respectively located between the respective N+-type source 412 and the p-type floating shallow doped well region 414. In the structure of the present invention, the channel layer is formed only under the gate oxide layer 404. Type doping the surface of the well region 4〇8. In addition, a boron phosphide glass (BPSG) layer 418 is overlying the pair of separated polysilicon gates 406 to provide a separation between the pair of separated polycrystalline gates 4 〇 6 and the pair of N + -type sources 412 Electrical insulation. A source metal layer 422 is over the shed phosphor glass (BPSG) dielectric layer 418 and contacts the pair of n+ source 412 to provide electrical communication between the pair of N+ source 412 and the outside. Further, a drain metal layer (not shown) is located under the N+ type <1〇〇> substrate 400. In the present invention, the N+ type <100> substrate 400 is used as a drain of the split gate vertical plastic oxy-halide transistor, and the drain metal layer provides electricity between the drain and the outside. Sexual conduction. The split gate vertical MOS device structure 40 provided by the present invention is provided by removing the polysilicon gate 406 and the drain (ie, the 9 201034188 N+ type <100> substrate 400) The overlapping region pole structure is used to reduce the gate charge, and the separation gate reduces the power loss during the switching process. The p-type floating money is formed under the time-and-close gate structure. The electric field 414 region 414 is generated at the edge of the separation and separation gate structure to avoid the floating shallow doping of Lai Yang Lai step formation. The N_ type covers the P_ type floating shallow doping ==== the increase below the well ^4. Before the 414 Xiaocai 卩 导 导 导 导 , , , , , , 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离 分离The rapid increase of the resistance value, and the separate gate vertical type MOS semi-transistor element can be described as an example of the present invention, which uses the N-channel split gate vertical MOS transistor structure 40 as an example. However, the present invention is equally applicable to: a p-channel split gate (four) straight-type semi-transistor element, an alpha structure, /, a P-channel with a split gate vertical type MOS micro-transistor element structure and the foregoing Ν The conductivity of each of the corresponding regions of the channel with the split gate vertical MOS transistor structure 40 is opposite to each other. The following is a detailed description of the manufacturing method of the split gate vertical MOS device structure 40 of the Ν channel of the fourth figure. Referring to the fourth diagram, the manufacturing method of the present invention first prepares a Ν+type <1〇〇> substrate 400, which may be a semiconductor material, red, such as carbon fossil. a Si (Si) material or a SiGe material (siGe) material; then a low doping concentration N-type epitaxial layer 402 such as tantalum carbide (SiC) is grown on the N+ type <100> substrate 400 Or a germanium (SiGe) material as a high voltage resistant body, and then thermally oxidizing an oxide layer 404 over the 2 doping concentration germanium-type epitaxial layer 402 and depositing a poly germanium layer 4〇6" On the oxide layer 404 at 201034188. The oxide layer 404 is subsequently supplied as a gate oxygen having a dielectric constant of 3.9. In addition, the present invention may also use a material having a dielectric constant greater than θ, such as tantalum nitride (Si^4) or hafnium oxide (Hf〇x), or a tantalum of tantalum oxide (HgOx). The stacked insulating layer structure == tantalum oxide layer 402' is used for subsequent gate oxide layer. Please refer to &4/罔. Then, the gate oxide/cut polysilicon gate 406 is formed by etching using a photomask, and then implanted with boron (B〇r〇n) ions. The well region 408 is respectively doped in the N-type epitaxial layer 402 on the opposite side of the polysilicon gate 4〇6. Referring to the fourth c-figure, the patterned photoresist layer 410 is disposed on the gate oxide layer 4〇4 and the N+s<;^〇> θ 400 to implant Arsenic ions and back Fire formation—for ν+ ς j = polycrystalline treasure 406 opposite side of the Γ-type doping well region Λ patterned photoresist layer 41G the same day to find out - separate gate pole lit using dry (four) way to remove parts The polycrystalline stone gate ==:; 4°4 to form a separate closed-pole structure'=Fig. Next, the pair of split gates 406 are implanted in a mixed concentration N•• worm layer Nazi is connected to ri shallow #杂^—the pair of P-type shallow doped well regions 414, and the floating portions are partially overlapped with the individual gates 4G6, respectively. Into a floating 5j^ P-type shallow doping well region 414 under the doped hetero-sub-region 4 Μ 1 of the hand-held well from 416 and covered the floating Ρ · type shallow doping well floating r (four) in addition to the pattern The photoresist layer 410 is formed. The method of forming the foregoing mass implantation step well region 414 and the floating N_type shallow doping well region 416 is mixed with the nO original metamorphism and enters the r-type doping well region 408 to float N-Tudor 12 However, since the ocean is connected to the F-type shallow doping well region 414 and the mineral source source:: region agriculture, the 〇-type doping well region 4〇8-type gate pole 朗朗金^ to the present invention (four) channel The characteristics of the split, germanium semi-transistor element 40 are affected. Referring to FIG. 4, 201034188, the fourth F-picture is deposited as a electrode insulating layer on the above-mentioned split gate structure by depositing a stripper-second glass (BPSG) layer 418. Please refer to the fourth g diagram, and then use a patterned photoresist layer as a mask to form a pair of high-concentration P+ doping well regions 420 at a high temperature implanted boron ion, respectively, at the N+ source 412 ^ The type of doped well region 408 is between, and the P-type doped well region 4〇8 coats the 'concentration P-type doped well region 420. Finally, a deposit is formed to form a source metal layer 422 over the borophosphon glass (BPSG) layer 418. Thus, the main structure of the N-channel split gate vertical MOS transistor 41 of the present invention is completed. The method for fabricating the above-described split gate vertical MOS device structure 40 provided by the invention can use the same patterned photoresist layer to define the source and the separate gate in different process steps. The structure and the position of the floating shallow doped N-type/P-type well region simplify the process steps and reduce manufacturing costs. In addition, in another embodiment of the manufacturing method of the present invention, in the fourth E diagram, the steps of forming the floating F-type shallow doping well region 414 and the floating tantalum-type shallow doping well region 416 are mutually adjusted. The remaining process steps are the same as the embodiment of the above manufacturing method. Further, another embodiment of the manufacturing method according to the present invention can also be applied to an insulated gate bipolar transistor (Insulated Gate Bipolar)
Transistor，IGBT)元件，如第六圖所示，其中係將該N+型 <100>基板400改以P+型<1〇〇>基板600代替，而該絕緣閉 極雙極性電晶體元件結構製造步驟相同於第四A圖至第四 G圖所例示及其變化例。 第五A圖係一傳統垂直型功率金氧半場效電晶體元件 内部電場圖。第五B圖係本發明具分離式閘極垂直型功率 金氧半場效電晶體元件内部電場圖。從第五A圖及第五b 圖中可看出，本發明具分離式閘極垂直型功率金氧半場效 12 201034188 電;平二’於分離的個別閘極之間 別對應第五A圖傳统社槿及筮石士*第五C圖係分 声表面水平方^ :冓及 圖本备明結構沿著蟲晶 層表面水千方向延伸的表面電場曲線圖，可看出本發明社 構中兩個分^閘極鄰接浮接p_㈣摻料區/n_型淺推^ 井區的角落表面電場與傳統相近，沒有感應出高電場。 本發明之描述可應用於以N-type (N-channel)或P-type ❹ (P-channel)為基板的場效電晶體結構，熟知本技術領域者可 對本發明作適當的修改，然不脫離本發明之精神與範轉。 再者，以上所述僅為本發明之具體實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭示 之精神下所完成之等效改變或修飾，均應包含在下述之申 請專利範圍内。 13 201034188 【圖式簡單說明】 第一圖係一傳統垂直型功率金氧半場效電晶體結構之 截面示意圖。 第二圖係一傳統垂直型功率金氧半場效電晶體之閘極 電荷導通動作圖。 第三圖係一傳統垂直型功率金氧半場效電晶體之元件 寄生電容分佈圖。 第四圖係根據本發明一實施例的分離式閘極垂直型金 氧半場效電晶體元件結構的截面示意圖。 ® 第四A圖至第四G圖係本發明第四圖的分離式閘極垂 直型金氧半場效電晶體元件結構的製造方法各製程階段對 應的結構截面示意圖。 第五A圖係一傳統垂直型功率金氧半場效電晶體之元 件内部電場圖。 第五B圖係一本發明分離式閘極垂直型功率金氧半場 效電晶體之元件内部電場圖。 第五C圖係分別對應第五A圖傳統結構及第五B圖本 _ 發明結構沿著磊晶層表面水平方向延伸的表面電場曲線 圖。 第六圖係根據本發明一實施例的絕緣閘極雙極性電晶 體（Insulated Gate Bipolar Transistor，IGBT)元件的截面示意 圖。 【主要元件符號說明】 10----功率垂直型金氧半場 16----問極 效電晶體 18----源極 12----N+型基板 14----N·型磊晶層 14 201034188 40 N通道具分離式閘極垂 410 圖案化光阻層 垂型金氧半電晶體元件 412 Ν+型源極 結構 414 浮接-ρ-型淺摻雜井區 400 N+型<100>基板 416 浮接_Ν_型淺摻雜井區 402 ：ΝΓ型磊晶層 418 硼磷矽玻璃層 404 閘極氧化層 420 Ρ+型摻雜井區 406 閘極 422 源極金屬層 408 Ρ_型摻雜井區 ❹ 15The Transistor (IGBT) component, as shown in the sixth figure, wherein the N+ type <100> substrate 400 is replaced by a P+ type <1〇〇> substrate 600, and the insulated closed-pole bipolar transistor element The structural manufacturing steps are the same as those illustrated in the fourth to fourth G diagrams and variations thereof. Figure 5A is an internal electric field diagram of a conventional vertical type power MOS field effect transistor. Figure 5B is an internal electric field diagram of a galvanic half-effect transistor device with a split gate vertical type power according to the present invention. It can be seen from the fifth A diagram and the fifth b diagram that the present invention has a split gate vertical type power MOS half-field effect 12 201034188 electric; and a flat A' corresponds to the fifth A diagram between the separated individual gates. The traditional society and the 筮石士* The fifth C picture is the horizontal surface of the sound surface ^ : 冓 and the picture of the surface of the surface of the surface of the surface of the insect layer In the middle two points ^ gates adjacent to the floating p_ (four) doping area / n_ type shallow push ^ the corner surface electric field is similar to the traditional, no high electric field is induced. The description of the present invention can be applied to a field effect transistor structure using N-type (N-channel) or P-type ❹ (P-channel) as a substrate, and those skilled in the art can appropriately modify the present invention, but It is out of the spirit and scope of the present invention. In addition, the above description is only for the specific embodiments of the present invention, and is not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications that do not depart from the spirit of the present invention should be included. It is within the scope of the following patent application. 13 201034188 [Simple description of the diagram] The first diagram is a schematic cross-sectional view of a conventional vertical power MOS field effect transistor structure. The second figure is a diagram of the gate charge conduction action of a conventional vertical type power MOS field effect transistor. The third figure is a parasitic capacitance distribution of components of a conventional vertical power MOS field effect transistor. The fourth figure is a schematic cross-sectional view showing the structure of a split gate vertical type gold-oxygen half field effect transistor element according to an embodiment of the present invention. ® Figs. 4A to 4G are schematic cross-sectional views showing the structure of the separate gate-type vertical MOS field device structure of the fourth embodiment of the present invention. Figure 5A is an internal electric field diagram of a conventional vertical power MOS field effect transistor. Fig. 5B is an internal electric field diagram of a component of the split gate vertical type power MOS field effect transistor of the present invention. The fifth C-picture corresponds to the surface electric field curve of the conventional structure of the fifth A picture and the fifth B picture _ invention structure extending along the horizontal direction of the surface of the epitaxial layer. Fig. 6 is a schematic cross-sectional view showing an insulated gate bipolar transistor (IGBT) element according to an embodiment of the present invention. [Main component symbol description] 10----Power vertical type gold oxide half field 16----Exerent effect transistor 18----Source 12----N+ type substrate 14----N· type Epitaxial layer 14 201034188 40 N channel with separate gate sag 410 patterned photoresist layer vertical MOS transistor 412 Ν + source structure 414 floating - ρ - type shallow doping well 400 N + type <100> Substrate 416 Floating Ν Ν _ type shallow doped well region 402: ΝΓ type epitaxial layer 418 borophosphonium silicate glass layer 404 gate oxide layer 420 Ρ + type doped well region 406 gate 422 source metal Layer 408 Ρ_type doped well region ❹ 15