TWI455318B - High voltage semiconductor device and method for manufacturing the same - Google Patents

Description

High voltage semiconductor device and method of manufacturing same

The present invention relates to a high voltage semiconductor device, and more particularly to a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method of fabricating the same.

The high voltage semiconductor device technology is suitable for the field of high voltage and high power integrated circuits. Conventional high voltage semiconductor devices, such as vertically diffused metal oxide semiconductor (VDMOS) transistors and horizontally diffused metal oxide semiconductor (LDMOS) transistors, are mainly used in component applications above or about 18V. The advantages of high-voltage device technology are cost-effective and easily compatible with other processes, and have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control.

Horizontally diffused metal oxide semiconductor (LDMOS) transistors use gate voltage to create a channel and control the current flowing between the source and the drain. In a conventional horizontally diffused metal oxide semiconductor transistor (LDMOS), in order to prevent a punch-through effect between a source and a drain, it is necessary to lengthen the channel length of the transistor. However, this way increases the size of the wafer area of the device will increase and the transistor ON resistance _{(on-resistance,} R on) rises. Furthermore, since the mobility of the hole is lower than the mobility of the electron, the on-resistance of the P-type diffusion metal oxide semiconductor (PDMOS) transistor is higher than the on-resistance of the N-type diffusion metal oxide semiconductor (NDMOS) transistor. Improvement in the performance of P-type diffusion MOS transistors.

Therefore, it is necessary to find a new high-voltage semiconductor device structure that can solve the above problems.

An embodiment of the invention provides a high voltage semiconductor device comprising: a semiconductor substrate having a high voltage well region therein, the high voltage well region having a first conductivity type; and a gate structure disposed over the semiconductor substrate of the high voltage well region a source doped region and a drain doped region respectively located in a high voltage well region on both sides of the gate structure; and a lightly doped region having a first conductivity type, located in the source doped region and the drain The doped regions are between and relatively adjacent to the source doped regions.

Another embodiment of the present invention provides a high voltage semiconductor device comprising: an epitaxial layer having a first conductivity type formed on a semiconductor substrate, and having a first high voltage well region and a first high voltage in the epitaxial layer The well region has a second conductivity type opposite to the first conductivity type; a gate structure disposed above the epitaxial layer of the first high voltage well region; and an integrated doping region of the first conductivity type, located in the gate structure a first high voltage well region on a first side; a source doped region in the body doped region; a drain doped region on a second side opposite the first side of the gate structure a first high-voltage well region; and a first lightly doped region having a first conductivity type, located in the body doping region and adjacent to the source doping region.

A further embodiment of the present invention provides a method of fabricating a high voltage semiconductor device, comprising: forming an epitaxial layer having a first conductivity type on a semiconductor substrate; forming a phase opposite to the first conductivity type in the epitaxial layer a first high-voltage well region of a second conductivity type; forming an integrally doped region having a first conductivity type in the first high-voltage well region; forming a drain-doped region in the first high-voltage well region; Forming a source doped region in the doped region; forming a gate structure over the epitaxial layer of the first high voltage well region, so that the body doped region and the drain doped region are respectively located on both sides of the gate structure Forming a first lightly doped region having a first conductivity type in the high voltage well region; and forming a body doped region adjacent to the source doping region.

A high voltage semiconductor device according to an embodiment of the present invention will be described below. However, the present invention is to be understood as being limited to the details of the present invention.

Embodiments of the present invention provide a high voltage semiconductor device, such as a horizontally diffused MOS transistor, which utilizes a halo implant region or a pocket implant region to mitigate a breakdown effect and thereby shorten The transistor channel reduces the on-resistance of the transistor and reduces the size of the device.

Referring to FIG. 1, a cross-sectional view of a high voltage semiconductor device 10 in accordance with an embodiment of the present invention is shown. In the present embodiment, the high voltage semiconductor device 10, such as a horizontally diffused MOS transistor, includes a semiconductor substrate 100 having an active region OD defined by an isolation structure 103. In this embodiment, the semiconductor substrate 100 can be a germanium substrate, a germanium telluride (SiGe) substrate, a bulk semiconductor substrate, a compound semiconductor substrate, a silicon on insulator (SOI). A substrate or other conventional semiconductor substrate. Furthermore, the semiconductor substrate 100 can be implanted with a P-type or N-type dopant depending on design requirements. Furthermore, the isolation structure 103 is a local oxidation of silicon (LOCOS). In other embodiments, the isolation structure 103 can be a shallow trench isolation (STI) structure.

A high voltage well region 102 having a first conductivity type is located within the semiconductor substrate 100 of the active region OD.

A gate structure 117 is disposed over the semiconductor substrate 100 of the high voltage well region 102. The gate structure 117 includes a gate dielectric layer 114 in contact with the semiconductor substrate 100, a gate electrode 116 on the gate dielectric layer 114 and coupled to a gate voltage V _G , and a gate on the sidewall of the gate electrode 116. Pole spacer 115.

A source doped region 109 and a drain doped region 113 are respectively located in the high voltage well region 102 on both sides of the gate structure 117. In this embodiment, the source doping region 109 is coupled to a source voltage V _S , including a first heavily doped region 106 having a first conductivity type and adjacent to the first heavily doped region 106 and having A second heavily doped region 108 of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. In an embodiment, the first conductivity type may be an N type, and the second conductivity type is a P type. In another embodiment, the first conductivity type may be a P type, and the second conductivity type is an N type. Furthermore, the gate doping region 113 is coupled to a drain voltage V _D , and includes a double diffusion region 112 having a second conductivity type and a third concentration dopant having a second conductivity type in the double diffusion region 112. Miscellaneous zone 110.

A well region 104 having a second conductivity type is located within the semiconductor substrate 100 and surrounds the high voltage well region 102. The surface of the well region 104 can include a fourth heavily doped region 122 having a second conductivity type coupled to a substrate voltage _Vsub .

A lightly doped region 120 having a first conductivity type is located between the source doping region 109 and the gate doping region 113 and is relatively adjacent to the source doping region 109. In one embodiment, the doping concentration of the lightly doped region 120 is in the range of 10 ⁸ /cm ² to 10 ¹⁶ /cm ² and may be formed by a halo implantation, such that the lightly doped region 120 (ie, the annular implant region) substantially surrounds the source doped region 109 (ie, the first heavily doped region 106 and the second heavily doped region 108). In the present embodiment, in particular, the lightly doped region 120 can effectively reduce the leakage current between the source and the drain due to the breakdown effect.

Referring to FIG. 2, a cross-sectional view of a high voltage semiconductor device 20 according to another embodiment of the present invention is illustrated, wherein the same reference numerals are used for the same portions as those of FIG. 1 and the description thereof is omitted. In the present embodiment, the high voltage semiconductor device 20, such as a horizontally diffused MOS transistor, includes a semiconductor substrate 100 on which an epitaxial layer 101 having a first conductivity type is formed. The conductivity type of the epitaxial layer 101 may be the same as that of the semiconductor substrate 100. Furthermore, the epitaxial layer 101 has an active region OD defined by an isolation structure 103.

A first high voltage well region 202 having a second conductivity type opposite to the first conductivity type is located within the epitaxial layer 101 of the active region OD. In an embodiment, the first conductivity type may be an N type, and the second conductivity type is a P type. In another embodiment, the first conductivity type may be a P type, and the second conductivity type is an N type.

A gate structure 117 is disposed over the epitaxial layer 101 of the first high voltage well region 202 and coupled to a gate voltage V _G . In the present embodiment, the gate electrode 116 of the gate structure 117 may extend over a portion of the isolation structure 103, as shown in FIG.

An integrally doped region 111 having a first conductivity type is located within the first high voltage well region 202 on a first side of the gate structure 117. A source doping region 109 is located in the body doping region 111 and coupled to a source voltage V _S . Furthermore, a first lightly doped region 220 having a first conductivity type is located within the body doped region 111 and adjacent to the source doped region 109. The doping concentration of the first lightly doped region 220 is in the range of 10 ⁸ /cm ² to 10 ¹⁶ /cm ² . In the present embodiment, the source doping region 109 includes a first heavily doped region 106 having a first conductivity type, a second concentration adjacent to the first heavily doped region 106 and having a second conductivity type. The doped region 108 is adjacent to the second heavily doped region 108 and has a second lightly doped region 105 of the second conductivity type. In an embodiment, the first lightly doped region 220 may be formed by pocket implantation such that the first lightly doped region 220 is located below the source doped region 109 or the second lightly doped region 105. The body doped region 111 is adjacent to the second heavily doped region 108. In this embodiment, in particular, the first lightly doped region 220 can effectively reduce the leakage current between the source and the drain due to the breakdown effect.

A drain doped region 113 is located within the first high voltage well region 202 on a second side relative to the first side of the gate structure 117. The drain doping region is coupled to a drain voltage V _D , including a high voltage double diffused region 212 having a second conductivity type and a second conductivity type in the high voltage double diffusion region 212 A third concentrated doped region 110.

A second high voltage well region 204 having the first conductivity type is located within the epitaxial layer 101 and surrounds the first high voltage well region 202. The surface of the second high voltage well region 204 can include a fourth heavily doped region 122 having a first conductivity type coupled to a substrate voltage _Vsub .

3A to 3G are cross-sectional views showing a manufacturing method of the high voltage semiconductor device 20 in Fig. 2. Referring to FIG. 3A, a semiconductor substrate 100 such as a germanium substrate, a germanium telluride (SiGe) substrate, a bulk semiconductor substrate, a compound semiconductor substrate, an insulating layer overlying germanium (SOI) substrate, or other conventional semiconductor substrates is provided. Furthermore, the semiconductor substrate 100 can be implanted with a P-type or N-type dopant depending on design requirements. Next, an epitaxial layer 101 having a first conductivity type is formed on the semiconductor substrate 100, wherein the epitaxial layer 101 can have the same conductivity type as the semiconductor substrate 100, and can be formed by selective epitaxial growth.

Then, a first high voltage well region 202 having a second conductivity type opposite to the first conductivity type is formed in the epitaxial layer 101. In an embodiment, the first conductivity type may be an N type, and the second conductivity type is a P type. In another embodiment, the first conductivity type may be a P type, and the second conductivity type is an N type. In this embodiment, an ion implantation process can be used to implant dopants in the epitaxial layer 101, followed by a thermal diffusion process to form a first high voltage well region 202.

Referring to FIG. 3B, an isolation structure 103, such as a local tantalum oxide layer (LOCOS), is formed on the epitaxial layer 101 to define an active region OD corresponding to the first high voltage well region 202. In other embodiments, the isolation structure 103 can be a shallow trench isolation (STI) structure.

Referring to FIG. 3C, an ion implantation process can be used to implant dopants in the epitaxial layer 101, and then perform a thermal diffusion process and an annealing process to form a first high-voltage well region 202, and have a first A second high pressure well region 204 of conductivity type.

Referring to FIG. 3D, an integrated doping region 111 having a first conductivity type and a high voltage double diffusion region having a second conductivity type are formed in the first high voltage well region 202 by using different ion implantation processes and thermal diffusion processes. 212. The body doped region 111 and the high voltage double diffused region 212 are separated from each other by a predetermined distance.

Referring to FIG. 3E, a gate dielectric layer 114 is formed on the active region OD of the epitaxial layer 101, such as an oxide, a nitride, an oxynitride, a carbon oxide, or a combination thereof or other high dielectric constant material ( High-k, dielectric constant greater than 8), such as alumina (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON) ) or a combination thereof. The gate dielectric layer 114 can be formed using thermal oxidation, chemical vapor deposition (CVD), or other conventional deposition techniques. Next, a gate electrode 116 can be formed on the gate dielectric layer 114 by chemical vapor deposition (CVD) or other conventional deposition techniques. Gate electrode 116 may comprise polysilicon or metal. Thereafter, the gate electrode 116 and the underlying gate dielectric layer 114 are patterned using conventional lithography and etching processes. The patterned gate electrode 116 and the gate dielectric layer 114 are located above the first high voltage well region 202 between the body doped region 111 and the high voltage double diffusion region 212, and the partial cover doping region 111 and the high voltage double diffusion region. 212 and isolation structure 103.

Next, a photoresist pattern layer 119 is formed on the epitaxial layer 101 to expose the high voltage double diffusion region 212 and a portion of the body doped region 111. Thereafter, the ion implantation process is performed in a self-aligned manner to form a lightly doped region 105 having a second conductivity type in the high voltage double diffusion region 212 and the body doped region 111.

Referring to FIG. 3F, after the photoresist pattern layer 119 is removed, the gate spacers 115 are formed on the sidewalls of the patterned gate electrode 116 and the gate dielectric layer 114 to complete the fabrication of the gate structure 117. The gate spacers 115 may include oxides, nitrides, oxynitrides, or combinations thereof, and may be formed using conventional deposition processes and anisotropic etch processes. After forming the gate structure 117, a first heavily doped region 106 having a first conductivity type and a first adjacent thereto having a second conductivity type are formed in the body doping region 111 by using different ion implantation processes. a second heavily doped region 108, a third heavily doped region 110 having a second conductivity type formed in the high voltage double diffusion region 212, and a fourth having a first conductivity type formed on a surface of the second high voltage well region 204 Concentrated doped region 122. The first heavily doped region 106, the second heavily doped region 108, and the lightly doped region 105 form a source doped region 109, and the third heavily doped region 110 and the high voltage double diffused region 212 form a drain. The doped region 113 is such that the body doped region 111 and the drain doped region 113 are respectively located on both sides of the gate structure 117.

Referring to FIG. 3G, a lightly doped region 220 having a first conductivity type (ie, a pocket implant region) may be formed in the body doped region 111 adjacent to the source doping region 109 by using a pocket implantation process. In this way, the fabrication of the high voltage semiconductor device 20 is completed. In an embodiment, the lightly doped region 220 is located within the body doped region 111 below the lightly doped region 105. Furthermore, the lightly doped region 220 is adjacent to the second heavily doped region 108 and has a doping concentration in the range of 10 ⁸ /cm ² to 10 ¹⁶ /cm ² . In addition, in particular, the ion implantation mask used to form the lightly doped region 220 and the ion implantation mask used to form the lightly doped region 105 can be formed by using the same mask for the lithography process, thereby avoiding Additional manufacturing costs.

According to the foregoing embodiments, since the lightly doped region (annular implanted region) 120 and the lightly doped region (pocket implanted region) 220 can effectively reduce the leakage current between the source and the drain due to the breakdown effect, Therefore, the channel lengths of the high voltage semiconductor devices 10 and 20 can be appropriately shortened, thereby reducing the on-resistance and size of the high voltage semiconductor devices 10 and 20.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20. . . Semiconductor device

100. . . Semiconductor substrate

101. . . Epitaxial layer

102. . . High pressure well area

103. . . Isolation structure

104. . . Well area

105, 120, 220. . . Lightly doped area

106. . . First concentrated doping zone

108. . . Second concentrated doping zone

109. . . Source doping region

110. . . Third concentrated doping zone

111. . . Body doped region

112. . . Double diffusion zone

113. . . Bipolar doping zone

114. . . Gate dielectric layer

115. . . Gate spacer

116. . . Gate electrode

117. . . Gate structure

119. . . Photoresist pattern layer

122. . . Fourth concentrated doping zone

202. . . First high pressure well area

204. . . Second high pressure well area

212. . . High pressure double diffusion zone

OD. . . Active zone

V _G . . . Gate voltage

V _D . . . Buckling voltage

V _S . . . Source voltage

V _sub . . . Substrate voltage

1 is a cross-sectional view showing a high voltage semiconductor device in accordance with an embodiment of the present invention.

2 is a cross-sectional view showing a high voltage semiconductor device in accordance with another embodiment of the present invention.

3A to 3G are cross-sectional views showing the manufacturing method of the high voltage semiconductor device in Fig. 2.

10. . . Semiconductor device

100. . . Semiconductor substrate

102. . . High pressure well area

103. . . Isolation structure

104. . . Well area

120. . . Lightly doped area

106. . . First concentrated doping zone

108. . . Second concentrated doping zone

109. . . Source doping region

110. . . Third concentrated doping zone

112. . . Double diffusion zone

113. . . Bipolar doping zone

114. . . Gate dielectric layer

115. . . Gate spacer

116. . . Gate electrode

117. . . Gate structure

122. . . Fourth concentrated doping zone

OD. . . Active zone

V _G . . . Gate voltage

V _D . . . Buckling voltage

V _S . . . Source voltage

V _sub . . . Substrate voltage

Claims (23)

A high voltage semiconductor device comprising: a semiconductor substrate having a high voltage well region therein, the high voltage well region having a first conductivity type; a gate structure disposed over the semiconductor substrate of the high voltage well region; a source a pole doped region and a drain doped region are respectively located in the high voltage well region on both sides of the gate structure; a lightly doped region having the first conductivity type is located in the source doped region and the germanium And a well region between the pole doped regions and adjacent to the source doped region; and a well region having a second conductivity type opposite to the first conductivity type, located in the semiconductor substrate and surrounding the high voltage well region. The high voltage semiconductor device of claim 1, wherein the source doped region comprises a first heavily doped region having the first conductivity type and a first layer adjacent thereto and having the second conductivity type The second heavily doped region includes a double diffusion region having the second conductivity type and a third concentrated doped region having the second conductivity type. The high voltage semiconductor device of claim 1, wherein the surface of the well region comprises a fourth heavily doped region having the second conductivity type. The high voltage semiconductor device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. The high voltage semiconductor device according to claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The high voltage semiconductor device of claim 1, wherein the lightly doped region surrounds the source doped region. The high voltage semiconductor device according to claim 1, wherein the doped concentration of the lightly doped region is in the range of 10 ⁸ /cm ² to 10 ¹⁶ /cm ² . A high voltage semiconductor device comprising: an epitaxial layer having a first conductivity type formed on a semiconductor substrate, wherein the epitaxial layer has a first high voltage well region, and the first high voltage well region has an opposite a second conductivity type of the first conductivity type; a gate structure disposed over the epitaxial layer of the first high voltage well region; and an integrated doping region of the first conductivity type, located in the gate structure a first high voltage well region on a first side; a source doped region in the body doped region; a drain doped region located on the first side of the gate structure a first low-voltage well region having the first conductivity type, located in the body doping region adjacent to the source-doped region; and having the first conductivity type A second high pressure well region is located within the epitaxial layer and surrounds the first high voltage well region. The high voltage semiconductor device of claim 8, wherein the source doped region comprises a first heavily doped region having the first conductivity type and a first layer adjacent thereto and having the second conductivity type The second heavily doped region includes a high voltage double diffusion region having the second conductivity type and a third concentrated doped region having the second conductivity type. The high voltage semiconductor device of claim 9, wherein the source doping region further comprises a second lightly doped region having the second conductivity type, the body above the first lightly doped region The doped region is adjacent to the second heavily doped region. A high voltage semiconductor device according to claim 8 of the patent application, The surface of the second high voltage well region includes a fourth concentrated doped region having the first conductivity type. The high voltage semiconductor device of claim 9, wherein the first lightly doped region is adjacent to the second heavily doped region and the doping concentration is in the range of 10 ⁸ /cm ² to 10 ¹⁶ /cm ² . The high voltage semiconductor device according to claim 8, wherein the doping concentration of the body doped region is in the range of 10 ⁸ /cm ² to 10 ¹⁶ /cm ² . The high voltage semiconductor device according to claim 8, wherein the first conductivity type is an N type and the second conductivity type is a P type. The high voltage semiconductor device according to claim 8, wherein the first conductivity type is a P type and the second conductivity type is an N type. A method of fabricating a high voltage semiconductor device, comprising: forming an epitaxial layer having a first conductivity type on a semiconductor substrate; forming a second conductivity type opposite to the first conductivity type in the epitaxial layer a first high-voltage well region; forming a second high-voltage well region surrounding the first high-voltage well region and having the first conductivity type in the epitaxial layer; forming the first conductive region in the first high-voltage well region a monolithic doped region; forming a drain doped region in the first high voltage well region; forming a source doped region in the bulk doped region; and the epitaxial layer in the first high voltage well region Forming a gate structure thereon, wherein the body doping region and the gate doping region are respectively located in the first high voltage well region on both sides of the gate structure; A first lightly doped region having the first conductivity type is formed in the body doped region adjacent to the source doping region. The method of manufacturing a high voltage semiconductor device according to claim 16, wherein the source doped region comprises a first heavily doped region having the first conductivity type and adjacent thereto and having the second conductivity type And a second heavily doped region, wherein the drain doped region comprises a high voltage double diffusion region having the second conductivity type and a third concentrated doped region having the second conductivity type. The method of fabricating a high voltage semiconductor device according to claim 17, wherein the source doping region further comprises a second lightly doped region having the second conductivity type, above the first lightly doped region. The body doped region is adjacent to the second heavily doped region. The method for manufacturing a high voltage semiconductor device according to claim 16, further comprising forming a fourth heavily doped region having the first conductivity type on a surface of the second high voltage well region. The method of manufacturing a high voltage semiconductor device according to claim 17, wherein the first lightly doped region is adjacent to the second heavily doped region and has a doping concentration of from 10 ⁸ /cm ² to 10 ¹⁶ /cm ² range. The method of manufacturing a high voltage semiconductor device according to claim 16, wherein the doping concentration of the body doped region is in the range of 10 ⁸ /cm ² to 10 ¹⁶ /cm ² . The method of manufacturing a high voltage semiconductor device according to claim 16, wherein the first conductivity type is an N type and the second conductivity type is a P type. As claimed in claim 16 of the high voltage semiconductor device The manufacturing method, wherein the first conductivity type is a P type, and the second conductivity type is an N type.