CN114335156A - Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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Abstract
The embodiment of the invention provides a transverse double-diffusion metal oxide semiconductor field effect transistor and a manufacturing method thereof, belonging to the technical field of chips. The transverse double-diffusion metal oxide semiconductor field effect transistor comprises a semiconductor substrate, a source region, a drain region, a gate region, a shallow slot isolation region, a P-type body region, an N-type well region, a P-type well region and an N-type drift region, wherein the N-type well region, the P-type well region and the N-type drift region are located on the semiconductor substrate, the gate region is a high-dielectric-constant dielectric metal gate, and the shallow slot isolation region is low-dielectric-constant dielectric shallow slot isolation. According to the LDMOSFET, the gate region is a High-dielectric-constant dielectric metal gate, the shallow trench isolation region is a low-dielectric-constant dielectric shallow trench isolation, and the LDMOSFET has a High-KMetalGate process, and is especially compatible with a CMOS process below 28 nm.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a transverse double-diffusion metal oxide semiconductor field effect transistor and a manufacturing method thereof.
Background
Complementary Metal Oxide Semiconductor (CMOS) CMOS is one technique used in the fabrication of large scale integrated circuit chips. CMOS processes at 28nm and below employ High-K dielectric metal gate (High-K gate) processes with Low-K dielectric (Low-K) material as back-end wiring isolation.
In a high-voltage power integrated circuit, a Lateral Double-diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) is adopted, so that the requirements on high voltage resistance, power control and the like can be met.
Usually, the LDMOSFET is integrated with a CMOS process to form a monolithic integrated process (e.g., BCD process or CD process), and the LDMOSFET also requires a High-KMetalGate process. The existing LDMOSFET does not have a High-KMetalGate process.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a High-k dielectric metal gate lateral double diffused metal oxide semiconductor field effect transistor having a High-KMetalGate process.
In order to achieve the above object, an embodiment of the present invention provides a lateral double-diffused metal oxide semiconductor field effect transistor, which includes a semiconductor substrate, a source region, a drain region, a gate region, a shallow trench isolation region, a P-type body region, and an N-type well region, a P-type well region, and an N-type drift region located on the semiconductor substrate, wherein the gate region is a high-k dielectric metal gate, and the shallow trench isolation region is a low-k dielectric shallow trench isolation.
Optionally, the dielectric constant of the low-dielectric-constant dielectric shallow trench isolation is 2.5-3.
Optionally, the high-k dielectric metal gate includes a metal gate and a high-k dielectric layer, wherein the metal gate is connected to the P-type body region and the N-type drift region through the high-k dielectric layer.
Optionally, the dielectric constant of the high-dielectric-constant dielectric layer is 25-30.
Optionally, the lateral double-diffused metal oxide semiconductor field effect transistor further includes an N-type buried layer and a P-type epitaxial layer, wherein the N-type buried layer is located below the N-type well region, and the P-type epitaxial layer is located below the P-type well region.
Optionally, the P-type well region includes a first P-type well region and a second P-type well region, and the first P-type well region and the second P-type well region are respectively located on two sides of the N-type well region and connected to the N-type well region.
Optionally, the P-type body region and the N-type drift region are located above the N-type well region.
Optionally, the N-type drift region includes a first N-type drift region and a second N-type drift region, and the first N-type drift region and the second N-type drift region are respectively located on two sides of the P-type body region.
Optionally, the drain region is located above the N-type drift region, and the source region is located above the P-type body region.
The embodiment of the invention also provides a manufacturing method of the transverse double-diffusion metal oxide semiconductor field effect transistor, which comprises the following steps: forming an N-type well region and a P-type well region in a selected region of a semiconductor substrate; forming a low-dielectric constant dielectric shallow trench isolation region; forming a P-type body region and an N-type drift region in a selected region of the semiconductor substrate; and forming a high-dielectric-constant dielectric metal gate region above the P-type body region and the N-type drift region, forming a drain region above the N-type drift region, and forming a source region above the P-type body region.
Optionally, the forming a high-k dielectric metal gate region above the P-type body region and the N-type drift region includes: forming a high dielectric constant dielectric layer over the P-type body region and the N-type drift region by atomic deposition; a metal gate is formed by physical vapor deposition over the high-permittivity dielectric layer.
Optionally, before forming the N-type well region and the P-type well region in the selected region of the semiconductor substrate, the method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor further includes: and forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate, wherein the N-type buried layer is positioned below the N-type trap area, and the P-type epitaxial layer is positioned below the P-type trap area.
The embodiment of the invention also provides a transverse double-diffusion metal oxide semiconductor field effect transistor which comprises a semiconductor substrate, a source region, a drain region, a gate region, a shallow groove isolation region, a P-type body region, an N-type well region, a P-type well region and an N-type drift region, wherein the N-type well region, the P-type well region and the N-type drift region are positioned on the semiconductor substrate, the transverse double-diffusion metal oxide semiconductor field effect transistor further comprises a low dielectric constant dielectric layer, the gate region is a high dielectric constant dielectric medium metal gate, and the low dielectric constant dielectric layer is positioned between the high dielectric constant dielectric medium metal gate and the N-type drift region.
Optionally, the dielectric constant of the low-dielectric-constant dielectric layer is 2.5-3, and the dielectric constant of the shallow trench isolation region is 3.9-4.
Optionally, the high-k dielectric metal gate includes a metal gate and a high-k dielectric layer, wherein the metal gate is connected to the P-type body region and the N-type drift region through the high-k dielectric layer.
Optionally, the dielectric constant of the high-dielectric-constant dielectric layer is 25-30.
Optionally, the lateral double-diffused metal oxide semiconductor field effect transistor further includes an N-type buried layer and a P-type epitaxial layer, wherein the N-type buried layer is located below the N-type well region, and the P-type epitaxial layer is located below the P-type well region.
Optionally, the P-type well region includes a first P-type well region and a second P-type well region, and the first P-type well region and the second P-type well region are respectively located on two sides of the N-type well region and connected to the N-type well region.
Optionally, the P-type body region and the N-type drift region are located above the N-type well region.
Optionally, the N-type drift region includes a first N-type drift region and a second N-type drift region, and the first N-type drift region and the second N-type drift region are respectively located on two sides of the P-type body region.
Optionally, the drain region is located above the N-type drift region, and the source region is located above the P-type body region.
The embodiment of the invention also provides a manufacturing method of the transverse double-diffusion metal oxide semiconductor field effect transistor, which comprises the following steps: forming an N-type well region and a P-type well region in a selected region of a semiconductor substrate; forming a shallow groove isolation region; forming a low dielectric constant dielectric layer above the N-type drift region; forming a P-type body region and an N-type drift region in a selected region of the semiconductor substrate; and forming a high-dielectric-constant dielectric metal gate region above the P-type body region and the low-dielectric-constant dielectric layer, forming a drain region above the N-type drift region, and forming a source region above the P-type body region.
Optionally, the forming a high-k dielectric metal gate region above the P-type body region and the N-type drift region includes: forming a high dielectric constant dielectric layer over the P-type body region and the N-type drift region by atomic deposition; a metal gate is formed by physical vapor deposition over the high-permittivity dielectric layer.
Optionally, before forming the N-type well region and the P-type well region in the selected region of the semiconductor substrate, the method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor further includes: and forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate, wherein the N-type buried layer is positioned below the N-type trap area, and the P-type epitaxial layer is positioned below the P-type trap area.
Through the technical scheme, the gate region of the LDMOSFET is the High-dielectric-constant dielectric metal gate, the shallow-trench isolation region is the low-dielectric-constant dielectric shallow-trench isolation, and the LDMOSFET has a High-KMetalGate process, and is especially compatible with a CMOS process below 28 nm.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a schematic structural diagram of a lateral double-diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for fabricating a lateral double-diffused mosfet according to an embodiment of the present invention;
FIGS. 3a-3e are schematic structural diagrams of respective manufacturing steps of the LDMOSFET shown in FIG. 1;
fig. 4 is a schematic structural diagram of another ldmos fet according to an embodiment of the present invention;
FIG. 5 is a schematic flow chart of another method for fabricating a lateral double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;
fig. 6a-6c are schematic structural diagrams of respective manufacturing steps of the LDMOSFET shown in fig. 4.
Description of the reference numerals
100-semiconductor substrate, 101-gate region, 102-source region, 103-drain region,
104-P type body region, 105a/105b-N type drift region, 106-N type well region,
107a/107 b-a P-type well region, 108-an N-type buried layer, 109-a P-type epitaxial layer,
110-shallow trench isolation region, 111-low dielectric constant dielectric layer.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic structural diagram of a lateral double-diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention, and referring to fig. 1, the lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET may include a semiconductor substrate 100, a source region 102, a drain region 103, a gate region 101, a shallow trench isolation region 110, a P-type body region 104, and an N-type well region 106, a P-type well region (107 a/107 b), and an N-type drift region (105 a/105 b) on the semiconductor substrate 100.
The gate region 101 is a high-k dielectric metal gate, and the shallow trench isolation region 110 is a low-k dielectric shallow trench isolation.
The dielectric constant of the low-K dielectric shallow trench isolation 110 (i.e., the low-K dielectric) preferred in the embodiments of the present invention may be 2.5 to 3.
The LDMOSFET provided by the embodiment of the invention has a High-KMetalGate process, and particularly can be compatible with a CMOS process below 28 nm.
A preferred high-k dielectric metal gate of an embodiment of the present invention comprises a metal gate and a high-k dielectric layer, wherein the metal gate is connected to the P-type body region 104 and above the N-type drift region (105 a/105 b) through the high-k dielectric layer.
The dielectric constant of the high-K dielectric layer (i.e. high-K dielectric) may be 25-30.
Preferably, the LDMOSFET may further include an N-type buried layer 108 and a P-type epitaxial layer 109, wherein the N-type buried layer 108 is located below the N-type well region 106, and the P-type epitaxial layer 109 is located below the P-type well region (107 a/107 b).
The P-type well region (107 a/107 b) preferred in the embodiment of the present invention may include a first P-type well region (e.g., 107 a) and a second P-type well region (e.g., 107 b), where the first P-type well region 107a and the second P-type well region 107b are respectively located at two sides of the N-type well region 106 and connected to the N-type well region 106.
Further, the P-type body region 104 and the N-type drift region are located above the N-type well region (105 a/105 b). The N-type drift regions (105 a/105 b) may include a first N-type drift region (e.g., 105 a) and a second N-type drift region (e.g., 105 b), the first N-type drift region 105a and the second N-type drift region 105b being respectively located at both sides of the P-type body region 104. The drain region 103 is located over the N-type drift regions (105 a/105 b) and the source region 102 is located over the P-type body region 104.
Fig. 2 is a schematic flow chart of a method for manufacturing a lateral double-diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention. The method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor can be used for manufacturing the LDMOSFET shown in fig. 1, fig. 3a to 3e are schematic structural diagrams of respective manufacturing links of the LDMOSFET shown in fig. 1, and with reference to fig. 2 and fig. 3a to 3e, the method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor can include the following steps:
step S110: an N-type well region and a P-type well region are formed in selected areas of a semiconductor substrate.
Preferably, before step S110, the method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor further includes: and forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate, wherein the N-type buried layer is positioned below the N-type well region 106, and the P-type epitaxial layer is positioned below the P-type well region (107 a/107 b).
By way of example, referring to FIG. 3a, a layer of SiO2 may be oxidized on a semiconductor substrate 100 (e.g., a P-type Silicon substrate); forming an N-type buried layer 108 (NBL) by photolithography, N-type ion implantation (e.g., by heavily doped ion implantation of antimony or arsenic), photoresist removal, annealing, and the like; and then epitaxially growing a P-type epitaxial layer (e.g., P-typeSi).
Next, a layer of SiO2 is oxidized on the semiconductor substrate 100; forming N-type well region 106 (e.g., HVNW region) by HVNW lithography and N-type ion implantation, removing photoresist; forming a P-type well region (107 a/107 b) (for example, HVPW region) by HVPW photoetching and P-type ion implantation, and removing photoresist; and then high temperature propulsion is carried out, the structure shown in figure 3b can be formed.
Step S120: a low-k dielectric shallow trench isolation region is formed.
Referring to fig. 3c, to support the above example, the SiO2 oxide layer is removed, and then a PADSiO2 layer is oxidized again; chemical Vapor Deposition (CVD) Si3N 4; photoetching in an Active Area (AA), performing dry etching on Si3N4 and SiO2, performing dry etching on Silicon to form a Shallow Trench Isolation (STI) area 110, and removing photoresist; then performing STIIliner oxidation, Chemical Vapor Deposition (CVD) on the Low-K dielectric layer to form a Low-dielectric-constant dielectric shallow trench isolation region, performing STI high-temperature annealing, performing Chemical Mechanical Polishing (CMP) on the Low-K dielectric layer, removing the Si3N4 wet method, and removing the PADSiO2 layer by the wet method.
The dielectric constant of the low-dielectric-constant dielectric shallow trench isolation preferably selected in the embodiment of the invention can be 2.5-3. The Low-K dielectric layer in the figure has the main component of SiO2 and the dielectric constant is about 2.5, while the dielectric constant of pure SiO2 can be selected to be 3.9.
Step S130: and forming a P-type body region and an N-type drift region in the selected region of the semiconductor substrate.
Following the above example, a thin layer of SiO2 is thermally oxidized on the structure shown in FIG. 3c, P-type Body regions 104 (e.g., P-Body regions) are etched, P-type ion implantation is performed to form P-Body regions, and the photoresist is removed; then, photoetching N-type drift regions (105 a/105 b) (such as NRF regions), forming NRF regions by N-type ion implantation, and removing photoresist; a high temperature anneal, wet removing the thin SiO2 layer, may form the structure shown in fig. 3 d.
Step S140: and forming a high-dielectric-constant dielectric metal gate region above the P-type body region and the N-type drift region, forming a drain region above the N-type drift region, and forming a source region above the P-type body region.
Preferably, the forming of the high-k dielectric metal gate region above the P-type body region and the N-type drift region may include: forming a high dielectric constant dielectric layer over the P-type body region and the N-type drift region by atomic deposition; a metal gate is formed by physical vapor deposition over the high-permittivity dielectric layer.
To take the above example, a thin oxide Layer is thermally oxidized on the structure shown in fig. 3d, a High-K dielectric Layer (High-K gate dielectric Layer), such as HfOx, is deposited by Atomic Layer Deposition (ALD), and then a metal gate is formed by Physical Vapor Deposition (PVD), such as Tantalum, etc., by gate lithography, dry etching of the metal gate, etching of the High-K dielectric Layer, forming the metal gate; then, respectively, N + and P + photolithography, heavily doped N + and P + ion implantation, annealing, forming N + and P + source/drain regions and a guard ring, and finally forming the LDMOSFET structure shown in fig. 3 e.
Wherein the dielectric constant of the High-K dielectric layer (High-K) is 25 to 30.
Fig. 4 is a schematic structural diagram of another lateral double-diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention, referring to fig. 4, the lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET may include a semiconductor substrate 100, a source region 102, a drain region 103, a gate region 101, a shallow trench isolation region 110, a P-type body region 104, and an N-type well region 106, a P-type well region (107 a/107 b), and an N-type drift region (105 a/105 b) on the semiconductor substrate 100, and the lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET further includes a low-k dielectric layer 111.
Wherein the gate region 101 is a high-k dielectric metal gate, and the low-k dielectric layer 111 is located between the high-k dielectric metal gate and the N-type drift region (105 a/105 b).
The dielectric constant of the dielectric layer 111 with low dielectric constant preferred in the embodiment of the invention can be 2.5-3; the dielectric constant of the shallow trench isolation region 110 (the composition is, for example, pure SiO 2) may be 3.9-4.
Referring to fig. 1 and 4, compared to the LDMOSFET shown in fig. 1, the LDMOSFET shown in fig. 4 has a Low-K material for the dielectric layer under the field plate, which can reduce the step.
A preferred high-k dielectric metal gate of an embodiment of the present invention comprises a metal gate and a high-k dielectric layer, wherein the metal gate is connected to the P-type body region 104 and above the N-type drift region (105 a/105 b) through the high-k dielectric layer.
Wherein the dielectric constant of the high-k dielectric layer is 25-30.
Preferably, the LDMOSFET may further include an N-type buried layer 108 and a P-type epitaxial layer 109, wherein the N-type buried layer 108 is located below the N-type well region 106, and the P-type epitaxial layer is located below the P-type well region (107 a/107 b).
The preferred P-type well region in the embodiment of the invention comprises a first P-type well region and a second P-type well region, wherein the first P-type well region and the second P-type well region are respectively positioned at two sides of the N-type well region and are connected with the N-type well region.
The P-type well region (107 a/107 b) preferred in the embodiment of the present invention may include a first P-type well region (e.g., 107 a) and a second P-type well region (e.g., 107 b), where the first P-type well region 107a and the second P-type well region 107b are respectively located at two sides of the N-type well region 106 and connected to the N-type well region 106.
Further, the P-type body region 104 and the N-type drift region are located above the N-type well region (105 a/105 b). The N-type drift regions (105 a/105 b) may include a first N-type drift region (e.g., 105 a) and a second N-type drift region (e.g., 105 b), the first N-type drift region 105a and the second N-type drift region 105b being respectively located at both sides of the P-type body region 104 and connected with the P-type body region 104. The drain region 103 is located over the N-type drift regions (105 a/105 b) and the source region 102 is located over the P-type body region 104.
Fig. 5 is a schematic flow chart of another method for manufacturing a lateral double-diffused mosfet according to an embodiment of the invention. The method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor can be used for manufacturing the LDMOSFET shown in fig. 4, fig. 6a to 6c are schematic structural diagrams of respective manufacturing links of the LDMOSFET shown in fig. 4, and with reference to fig. 5, fig. 3a to 3b, and fig. 6a to 6c, the method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor can include the following steps:
step S210: an N-type well region and a P-type well region are formed in selected areas of a semiconductor substrate.
Preferably, before step S210, the method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor further includes: and forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate, wherein the N-type buried layer is positioned below the N-type trap area, and the P-type epitaxial layer is positioned below the P-type trap area.
By way of example, referring to FIG. 3a, a layer of SiO2 may be oxidized on a semiconductor substrate 100 (e.g., a P-type Silicon substrate); forming an N-type buried layer 108 (NBL) by photolithography, N-type ion implantation (e.g., by heavily doped ion implantation of antimony or arsenic), photoresist removal, annealing, and the like; and then epitaxially growing a P-type epitaxial layer (e.g., P-typeSi).
Next, a layer of SiO2 is oxidized on the semiconductor substrate 100; forming N-type well region 106 (e.g., HVNW region) by HVNW lithography and N-type ion implantation, removing photoresist; forming a P-type well region (107 a/107 b) (for example, HVPW region) by HVPW photoetching and P-type ion implantation, and removing photoresist; and then high temperature propulsion is carried out, the structure shown in figure 3b can be formed.
Step S220: and forming shallow trench isolation regions.
Following the example described above, the SiO2 was removed on the structure shown in fig. 3b, and then a layer of PADSiO2 was oxidized again; chemical Vapor Deposition (CVD) Si3N 4; active Area (AA) photolithography, dry etching Si3N4 and SiO2, dry etching Silicon to form shallow trench isolation 110 (STI), photoresist removal, then performing stliner oxidation, high plasma Chemical vapor deposition (HDP) SiO2 dielectric layer (dielectric), STI high temperature annealing, Chemical Mechanical Polishing (CMP) SiO2 dielectric layer, Si3N4 wet removal, and wet removal of PADSiO2 layer can form the structure shown in fig. 6 a.
The dielectric constant of the shallow trench isolation region 110 (e.g., a SiO2 dielectric layer) may be 3.9-4.
Step S230: a low dielectric constant dielectric layer is formed over the N-type drift region.
Following the above example, a thin layer of SiO2 was thermally oxidized on the structure shown in fig. 6a, and then a Low-K dielectric layer 111, i.e. a Low-K dielectric layer, whose main component was SiO2, was fabricated by Chemical Vapor Deposition (CVD).
The dielectric constant of the Low-K dielectric layer 111 (i.e., the Low-K dielectric layer) preferred in the embodiment of the invention may be 2.5-3.
Step S240: and forming a P-type body region and an N-type drift region in the selected region of the semiconductor substrate.
In step S230, P-type Body region 104 (e.g., P-Body region) is etched, P-type ion implantation is performed to form P-Body region, and photoresist is removed; then, photoetching N-type drift regions (105 a/105 b) (such as NRF regions), forming NRF regions by N-type ion implantation, and removing photoresist; a high temperature anneal, wet removing the thin SiO2 layer, can form the structure shown in fig. 6 b.
Step S250: and forming a high-dielectric-constant dielectric metal gate region above the P-type body region and the low-dielectric-constant dielectric layer, forming a drain region above the N-type drift region, and forming a source region above the P-type body region.
Preferably, the forming of the high-k dielectric metal gate region over the P-type body region and the N-type drift region includes: forming a high dielectric constant dielectric layer over the P-type body region and the N-type drift region by atomic deposition; a metal gate is formed by physical vapor deposition over the high-permittivity dielectric layer.
To take the above example, a thin oxide Layer is thermally oxidized on the structure shown in fig. 6b, a High-K dielectric Layer (High-K gate dielectric Layer), such as HfOx, is deposited by Atomic Layer Deposition (ALD), and then a metal gate is formed by Physical Vapor Deposition (PVD), such as Tantalum, etc., by gate lithography, dry etching of the metal gate, etching of the High-K dielectric Layer, forming the metal gate; then, respectively performing N + and P + photoetching, heavily doping N + and P + ions, annealing to form N + and P + source and drain regions and a guard ring, and finally forming the LDMOSFET structure shown in fig. 6 c.
Wherein the dielectric constant of the high-k dielectric layer is 25-30.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (24)
1. A transverse double-diffusion metal oxide semiconductor field effect transistor comprises a semiconductor substrate, a source region, a drain region, a gate region, a shallow slot isolation region, a P-type body region, an N-type well region, a P-type well region and an N-type drift region, wherein the N-type well region, the P-type well region and the N-type drift region are located on the semiconductor substrate.
2. The LDMOS transistor of claim 1 wherein the low-k dielectric shallow trench isolation has a dielectric constant of 2.5-3.
3. The LDMOS transistor of claim 1, wherein the high-k dielectric metal gate includes a metal gate and a high-k dielectric layer,
wherein the metal gate is connected to the P-type body region and the N-type drift region through the high-k dielectric layer.
4. The LDMOS transistor of claim 3, wherein the high-k dielectric layer has a dielectric constant of 25-30.
5. The LDMOS transistor of claim 1 further comprising an N-type buried layer and a P-type epitaxial layer,
the N-type buried layer is located below the N-type trap region, and the P-type epitaxial layer is located below the P-type trap region.
6. The LDMOS transistor of claim 1, wherein the P-well region comprises a first P-well region and a second P-well region, the first P-well region and the second P-well region being respectively located on two sides of the N-well region and connected to the N-well region.
7. The LDMOS of claim 6 wherein the P-type body region and the N-type drift region are over the N-type well region.
8. The LDMOS of claim 7, wherein the N-type drift region comprises a first N-type drift region and a second N-type drift region, the first N-type drift region and the second N-type drift region being respectively located on both sides of the P-type body region.
9. The ldmos field effect transistor of claim 8 wherein said drain region is located above said N-type drift region and said source region is located above said P-type body region.
10. A method for manufacturing a lateral double-diffused metal oxide semiconductor field effect transistor is characterized by comprising the following steps:
forming an N-type well region and a P-type well region in a selected region of a semiconductor substrate;
forming a low-dielectric constant dielectric shallow trench isolation region;
forming a P-type body region and an N-type drift region in a selected region of the semiconductor substrate;
and forming a high-dielectric-constant dielectric metal gate region above the P-type body region and the N-type drift region, forming a drain region above the N-type drift region, and forming a source region above the P-type body region.
11. The method of claim 10, wherein forming a high-k dielectric metal gate region over the P-type body region and the N-type drift region comprises:
forming a high dielectric constant dielectric layer over the P-type body region and the N-type drift region by atomic deposition;
a metal gate is formed by physical vapor deposition over the high-permittivity dielectric layer.
12. The method of claim 10, wherein prior to said forming said N-well and P-well regions in said selected region of said semiconductor substrate, said method further comprises:
forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate,
the N-type buried layer is located below the N-type trap area, and the P-type epitaxial layer is located below the P-type trap area.
13. A lateral double-diffused metal oxide semiconductor field effect transistor comprises a semiconductor substrate, a source region, a drain region, a gate region, a shallow trench isolation region, a P-type body region, an N-type well region, a P-type well region and an N-type drift region which are arranged on the semiconductor substrate, and is characterized in that the lateral double-diffused metal oxide semiconductor field effect transistor also comprises a low dielectric constant dielectric layer,
the gate region is a high-dielectric-constant dielectric metal gate, and the low-dielectric-constant dielectric layer is located between the high-dielectric-constant dielectric metal gate and the N-type drift region.
14. The LDMOS transistor of claim 13 wherein the low-k dielectric layer has a dielectric constant of 2.5-3 and the shallow trench isolation region has a dielectric constant of 3.9-4.
15. The LDMOS transistor of claim 13, wherein the high-k dielectric metal gate includes a metal gate and a high-k dielectric layer,
wherein the metal gate is connected to the P-type body region and the N-type drift region through the high-k dielectric layer.
16. The LDMOS transistor of claim 15, wherein the high-k dielectric layer has a dielectric constant of 25-30.
17. The LDMOS transistor of claim 13 further comprising an N-type buried layer and a P-type epitaxial layer,
the N-type buried layer is located below the N-type trap region, and the P-type epitaxial layer is located below the P-type trap region.
18. The ldmos field effect transistor of claim 13, wherein said P-type well region comprises a first P-type well region and a second P-type well region, said first P-type well region and said second P-type well region are respectively located on two sides of said N-type well region and are connected to said N-type well region.
19. The ldmos field effect transistor according to claim 18, wherein said P-type body region and said N-type drift region are located above said N-type well region.
20. The ldmos field effect transistor of claim 19 wherein said N-type drift region includes a first N-type drift region and a second N-type drift region, said first N-type drift region and said second N-type drift region being respectively located on either side of said P-type body region.
21. The ldmos field effect transistor of claim 20 wherein the drain region is located above the N-type drift region and the source region is located above the P-type body region.
22. A method for manufacturing a lateral double-diffused metal oxide semiconductor field effect transistor is characterized by comprising the following steps:
forming an N-type well region and a P-type well region in a selected region of a semiconductor substrate;
forming a shallow groove isolation region;
forming a low dielectric constant dielectric layer above the N-type drift region;
forming a P-type body region and an N-type drift region in a selected region of the semiconductor substrate;
and forming a high-dielectric-constant dielectric metal gate region above the P-type body region and the low-dielectric-constant dielectric layer, forming a drain region above the N-type drift region, and forming a source region above the P-type body region.
23. The method of claim 22, wherein said forming a high-k dielectric metal gate region over said P-type body region and said N-type drift region comprises:
forming a high dielectric constant dielectric layer over the P-type body region and the N-type drift region by atomic deposition;
a metal gate is formed by physical vapor deposition over the high-permittivity dielectric layer.
24. The method of claim 22, wherein prior to said forming said N-well and P-well regions in said selected region of said semiconductor substrate, said method further comprises:
forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate,
the N-type buried layer is located below the N-type trap area, and the P-type epitaxial layer is located below the P-type trap area.
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