CN114361243B - Full-isolation lateral double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents

Abstract

The embodiment of the invention provides a fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor and a manufacturing method thereof, belonging to the technical field of chips. The fully-isolated transverse double-diffused metal oxide semiconductor field effect transistor comprises a semiconductor substrate, a source electrode region, a drain electrode region, a gate region, a shallow groove isolation region, a P-type body region, an N-type well region, a P-type well region and an N-type drift region, wherein the N-type well region, the P-type well region and the N-type drift region are positioned on the semiconductor substrate, the fully-isolated transverse double-diffused metal oxide semiconductor field effect transistor further comprises a gate oxide dielectric layer, the gate oxide dielectric layer is positioned between the gate region and the N-type drift region, the drain electrode region comprises a drain electrode heavily-doped region and a drain electrode lightly-doped region, and the source electrode region comprises a source electrode heavily-doped region and a source electrode lightly-doped region. The LDMOSFET structure is provided with a drain lightly doped region and a source lightly doped region with adjustable lengths, full isolation of a drain region and a gate region is realized based on the drain lightly doped region, the source lightly doped region and a gate oxide dielectric layer, and the on-state breakdown voltage of the LDMOSFET is effectively improved.

Description

Full-isolation lateral double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof

Technical Field

The invention relates to the technical field of chips, in particular to a full-isolation transverse double-diffusion metal oxide semiconductor field effect transistor and a manufacturing method thereof.

Background

The fabrication of a high voltage Lateral Double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) requires a Drift region (Drift) at the drain of the LDMOSFET to withstand the voltage. Aiming at the LDMOSFET with the common drain terminal being an N +/P + or P +/N + junction, when the LDMOSFET is started, the drain terminal has a larger electric field, and the breakdown voltage BVon is reduced greatly.

When the chip is manufactured at the present stage, the problem can be solved by injecting Light Doped Drain (LDD) ions or injecting the LDD ions to the position below a PN junction at a drain end at a larger angle, but the LDD ions are too short and have unobvious effects. Furthermore, the source drain implant and the LDD implant are performed after the Gate formation, and the thick oxide layer OX under the poly field plate is also completed, and there is no way to solve the length problem of the lightly doped drain.

Disclosure of Invention

An object of an embodiment of the present invention is to provide a fully isolated lateral double diffused mosfet, which can solve the problems of the length of a light doped drain, and the like.

In order to achieve the above object, an embodiment of the present invention provides a fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor, which includes a semiconductor substrate, a source region, a drain region, a gate region, a shallow trench isolation region, a P-type body region, and an N-type well region, a P-type well region, and an N-type drift region located on the semiconductor substrate, and further includes a gate oxide dielectric layer, where the gate oxide dielectric layer is located between the gate region and the N-type drift region, the drain region includes a heavily doped drain region and a lightly doped drain region, and the source region includes a heavily doped source region and a lightly doped source region.

Optionally, the drain lightly doped region and the source lightly doped region are manufactured by N-type ion lightly doped drain and high-voltage double diffusion.

Optionally, the setting of the parameters of the lightly doped drain includes: the length is 0.4-0.6 um, the depth is 0.2 um-0.3 um, and the concentration is 2e18cm³~6e18cm³。

Optionally, the parameter setting of the high-pressure double diffusion includes: the length is 0.4-0.6 um, the depth is 0.3-0.5 um, and the concentration is 1e18cm³~6e18cm³。

Optionally, the gate region is a metal gate or a polysilicon gate electrode, and the gate region is connected to the P-type body region and the N-type drift region.

Optionally, the fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor further includes an N-type buried layer and a P-type epitaxial layer, wherein the N-type buried layer is located below the N-type well region, and the P-type epitaxial layer is located below the P-type well region.

Optionally, the P-type well region includes first P-type well region, second P-type well region, first P-type well region with second P-type well region is located respectively the both sides in N-type well region and with N-type well region connects, the horizontal double-diffused metal oxide semiconductor field effect transistor of full isolation still includes third P-type well region, is located the top in N-type well region.

Optionally, the P-type body region and the N-type drift region are located above the third P-type well region.

Optionally, the N-type drift region includes a first N-type drift region and a second N-type drift region, and the first N-type drift region and the second N-type drift region are respectively located on two sides of the P-type body region.

Optionally, the drain region is located above the N-type drift region, and the source region is located above the P-type body region.

The embodiment of the invention also provides a manufacturing method of the full-isolation lateral double-diffusion metal oxide semiconductor field effect transistor, which comprises the following steps: forming an N-type well region and a P-type well region in a selected region of a semiconductor substrate; forming a shallow trench isolation region, a P-type body region and an N-type drift region in a selected region of the semiconductor substrate; forming a drain region above the N-type drift region, and forming a source region above the P-type body region, wherein the drain region comprises a heavily doped drain region and a lightly doped drain region, and the source region comprises a heavily doped source region and a lightly doped source region; and forming a gate region above the P-type body region and the N-type drift region.

Optionally, the drain lightly doped region and the source lightly doped region are manufactured by N-type ion lightly doped drain and high-voltage double diffusion.

Optionally, the setting of the parameters of the lightly doped drain includes: the length is 0.4-0.6 um, the depth is 0.2 um-0.3 um, and the concentration is 2e18cm³~6e18cm³。

Optionally, the parameter setting of the high-pressure double diffusion includes: the length is 0.4-0.6 um, the depth is 0.3-0.5 um, and the concentration is 1e18cm³~6e18cm³。

Optionally, the gate region is a metal gate or a polysilicon gate electrode, and the forming the gate region above the P-type body region and the N-type drift region includes: forming a gate oxide dielectric layer above the N-type drift region through chemical vapor deposition; and forming a gate region above the P-type body region and the gate oxide dielectric layer by physical vapor deposition.

Optionally, before forming the N-type well region and the P-type well region in the selected region of the semiconductor substrate, the method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor further includes: and forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate, wherein the N-type buried layer is positioned below the N-type trap area, and the P-type epitaxial layer is positioned below the P-type trap area.

Through the technical scheme, the fully-isolated lateral double-diffusion metal oxide semiconductor field effect transistor LDMOSFET structure provided by the embodiment of the invention has the drain lightly-doped region and the source lightly-doped region with adjustable lengths, and can realize full isolation of a drain region and a gate region based on the drain lightly-doped region, the source lightly-doped region and a gate oxide dielectric layer, so that the on-state breakdown voltage of the LDMOSFET is effectively improved.

Additional features and advantages of embodiments of the present invention will be described in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention and not to limit the embodiments of the invention. In the drawings:

fig. 1a and fig. 1b are schematic structural diagrams of a fully isolated lateral double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a method for manufacturing a fully isolated lateral double diffused mosfet according to an embodiment of the present invention;

FIGS. 3a-3c, FIGS. 4a-4b, and FIGS. 5a-5b are schematic structural diagrams of respective stages of fabricating LDMOSFETs shown in FIG. 1a or FIG. 1 b.

Description of the reference numerals

100-semiconductor substrate, 101-gate region, 102-source region, 103-drain region,

112-source heavily doped region, 122-source lightly doped region,

113-heavily doped drain region, 123-lightly doped drain region,

104-P type body region, 105a/105b-N type drift region, 106-N type well region,

107a/107 b-a P-type well region, 108-an N-type buried layer, 109-a P-type epitaxial layer,

110-shallow trench isolation region, 111-gate oxide dielectric layer.

Detailed Description

The following describes in detail embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.

Fig. 1a and fig. 1b are schematic structural diagrams of a fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention, please refer to fig. 1a and fig. 1b, the fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET may include a semiconductor substrate 100, a source region 102, a drain region 103, a gate region 101, a shallow trench isolation region 110, a P-type body region 104, and an N-type well region 106, a P-type well region (107 a/107 b), and an N-type drift region (105 a/105 b) on the semiconductor substrate 100, and the fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET may further include a gate oxide dielectric layer 111.

Wherein the gate oxide dielectric layer 111 is located between the gate region 101 and the N-type drift region (105 a/105 b). The drain region 103 may include a heavily doped drain region 113 and a lightly doped drain region 123, and the source region 102 includes a heavily doped source region 112 and a lightly doped source region 122.

The drain lightly doped region and the source lightly doped region preferred by the embodiment of the invention are manufactured by N-type ion lightly doped drain and high-pressure double diffusion.

Preferably, the parameter setting of the lightly doped drain comprises: the length is 0.4-0.6 um, the depth is 0.2 um-0.3 um, and the concentration is 2e18cm³~6e18cm³。

Preferably, the parameter setting of the high-pressure double diffusion comprises the following steps: the length is 0.4-0.6 um, the depth is 0.3-0.5 um, and the concentration is 1e18cm³~6e18cm³。

The drain lightly doped region 123 and the source lightly doped region 122 may be fabricated with adjustable lengths through an N-type ion Lightly Doped Drain (LDD) process or a high voltage double diffusion (DDD) process. The lightly doped drain region 123 and the lightly doped source region 122 may have the structure shown in fig. 1a or the structure shown in fig. 1 b.

By way of illustration, source drain implant and LDD implant or high voltage double diffusion (DDD) is performed before the gate region 101 is formed, which can effectively solve the problem of the length of the lightly doped drain. The LDD of the lightly doped region is connected with the source drain heavily doped region, the depth of the LDD is not more than the depth of a source drain junction, the length of the LDD can be 0.4-0.6 um, and the depth can be: 0.2um to 0.3 um; LDD concentration 2e18cm³~6e18cm³The DDD is larger than the source drain region and surrounds the source drain region, and the DDD length can be as follows: 0.4~0.6um, the DDD degree of depth can be: 0.3-0.5 um, concentration of DDD 1e18cm ³~6e18cm³。

The drain region 103 and the gate region 101 can be fully isolated based on the drain lightly doped region 123, the source lightly doped region 122 and the gate oxide dielectric layer 111.

The gate region 101, which is preferred in the present invention, may be a metal gate or a polysilicon gate electrode, and the gate region 101 is connected to the P-type body region 104 and the N-type drift region (105 a/105 b).

Preferably, the fully isolated lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET may further include an N-type buried layer 108 and a P-type epitaxial layer 109, wherein the N-type buried layer 108 is located below the N-type well region 106, and the P-type epitaxial layer 109 is located below the P-type well region (107 a/107 b).

The P-type well region (107 a/107 b) preferred in the present invention may include a first P-type well region (e.g., 107 a) and a second P-type well region (e.g., 107 b), the first P-type well region 107a and the second P-type well region 107b are respectively located at two sides of the N-type well region 106 and connected to the N-type well region 106, and the fully isolated lateral double diffused metal oxide semiconductor field effect transistor LDMOSFET may further include a third P-type well region 107c located above the N-type well region 106.

Further preferably, the P-type body region 104 and the N-type drift region (105 a/105 b) may be located above the third P-type well region 107 c.

The N-type drift region (105 a/105 b) preferred in the present invention may include a first N-type drift region (e.g., 105 a) and a second N-type drift region (e.g., 105 b), the first N-type drift region 105a and the second N-type drift region 105b being located at both sides of the P-type body region 104, respectively.

Further preferably, the drain region 103 is located above the N-type drift region, and the source region is located above the P-type body region.

Fig. 2 is a schematic flow chart of a method for manufacturing a fully-isolated lateral double-diffused mosfet according to an embodiment of the present invention, where the method for manufacturing a fully-isolated lateral double-diffused mosfet can be used for manufacturing an LDMOSFET shown in fig. 1, and fig. 3a to 3c, fig. 4a to 4b, and fig. 5a to 5b are schematic structural diagrams of respective manufacturing links of the LDMOSFET shown in fig. 1a or fig. 1b, and with reference to fig. 2, fig. 3a to 3c, fig. 4a to 4b, and fig. 5a to 5b, the method for manufacturing can include the following steps:

step S110: n-type well regions and P-type well regions are formed in selected areas of a semiconductor substrate.

Before step S110, the method for manufacturing a lateral double-diffused metal oxide semiconductor field effect transistor may further include: and forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate, wherein the N-type buried layer is positioned below the N-type well region 106, and the P-type epitaxial layer is positioned below the P-type well region (107 a/107 b).

By way of example, referring to fig. 3a, a layer of SiO2 may be oxidized on a semiconductor substrate 100 (e.g., a P-type Silicon substrate); forming an N-type buried layer 108 (NBL) through photolithography, N-type ion implantation (e.g., by heavily doped ion implantation of antimony or arsenic), photoresist removal, annealing, and the like; and then a P-type epitaxial layer (e.g., P-typeSi) is epitaxially grown.

Next, a layer of SiO2 is oxidized on the semiconductor substrate 100; forming an N-type well region 106 (e.g., HVNW region) by HVNW lithography and N-type ion implantation, and removing the photoresist; forming a P-type well region (107 a/107 b) (for example, HVPW region) by HVPW photoetching and P-type ion implantation, and removing photoresist; then, high temperature propulsion is performed, so that the structure shown in fig. 3b can be formed.

Step S120: and forming a shallow trench isolation region, a P-type body region and an N-type drift region in a selected region of the semiconductor substrate.

To support the above example, SiO2 is removed from the structure shown in fig. 3b, a PAD SiO2 layer is oxidized again, Chemical Vapor Deposition (CVD) Si3N4 is performed, Active Area (AA) lithography is performed, Si3N4 and SiO2 are dry etched, Silicon is dry etched, Shallow Trench Isolation (STI) is formed, and photoresist is removed; then, STI liner oxidation, high plasma Chemical vapor deposition (HDP) SiO2 dielectric layer (dielectric), STI high temperature annealing, Chemical Mechanical Polishing (CMP) SiO2 dielectric layer, Si3N4 wet removal, and PADSiO2 wet removal are performed to form the structure shown in fig. 3 c.

Step S130: and forming a drain region above the N-type drift region, and forming a source region above the P-type body region, wherein the drain region comprises a heavily-doped drain region and a lightly-doped drain region, and the source region comprises a heavily-doped source region and a lightly-doped source region.

Preferably, the drain lightly doped region and the source lightly doped region are manufactured by N-type ion lightly doped drain and high-voltage double diffusion.

Preferably, the parameter setting of the lightly doped drain includes: the length is 0.4-0.6 um, the depth is 0.2 um-0.3 um, and the concentration is 2e18cm³~6e18cm³。

Preferably, the parameter setting of the high-pressure double diffusion comprises the following steps: the length is 0.4-0.6 um, the depth is 0.3-0.5 um, and the concentration is 1e18cm³~6e18cm³。

Following the above example, a thin layer of SiO2 was thermally oxidized on the structure shown in FIG. 3c, and N-type drift regions (105 a/105 b), such as NRF regions, were etched; then N-type ions are injected into an NRF region, and the photoresist is removed; photoetching a P-type Body region 104, such as a P-Body region, performing P-type ion implantation on the P-Body region, and removing photoresist; and annealing at high temperature to form an NRF region and a P-Body region.

Then, respectively photoetching N +, P + and N-lightly doped regions (namely the source lightly doped region 122); and respectively carrying out heavy doping ion implantation on the N-type N + region, the P-type P + region and the N-type N-lightly doped region, respectively removing photoresist, and then annealing together to form the structure shown in figure 4a or figure 4 b.

To illustrate, source drain implant and LDD implant or highThe compressive double diffusion (DDD) is performed before the gate region 101 is formed, which can effectively solve the length problem of the light doped drain. The LDD of the lightly doped region is connected with the source drain heavily doped region, the depth does not exceed the depth of the source drain junction, the length of the LDD can be 0.4-0.6 um, and the depth can be: 0.2um to 0.3 um; LDD concentration 2e18cm³~6e18cm³The DDD is larger than the source drain region and surrounds the source drain region, and the DDD length can be as follows: 0.4-0.6 um, the DDD depth can be: 0.3-0.5 um, concentration of DDD 1e18cm³~6e18cm³。

Step S140: and forming a gate region above the P-type body region and the N-type drift region.

Preferably, the gate region is a metal gate or a polysilicon gate electrode, and the step S140 may include: forming a gate oxide dielectric layer above the N-type drift region through chemical vapor deposition; and forming a gate region above the P-type body region and the gate oxide dielectric layer by physical vapor deposition.

Step S130 is performed, taking the gate region as a metal gate for example, a gate oxide dielectric layer 111 (e.g., a SiO2 dielectric layer) is formed on the structure shown in fig. 4a or 4b by Chemical Vapor Deposition (CVD), and a portion of the SiO2 dielectric layer is etched by photolithography and dry etching; then thermally oxidizing a thin oxide layer, removing the oxide layer, and oxidizing a gate by using a SiO2 layer; by Physical Vapor Deposition (PVD) of metal, such as aluminum, photolithography, dry etching of a portion of the metal, stripping and removing photoresist, the fabrication of the metal gate is completed, and the LDMOSFET structure shown in fig. 5a or fig. 5b is correspondingly formed.

Therefore, the fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET structure provided by the embodiment of the invention has the drain lightly-doped region and the source lightly-doped region with adjustable lengths, and can realize full isolation of a drain region and a gate region based on the drain lightly-doped region, the source lightly-doped region and a gate oxide dielectric layer, so that the on-state breakdown voltage of the LDMOSFET is effectively improved; when the LDMOSFET is manufactured, ion implantation and high-temperature processes can be completed firstly, and the LDD or the DDD with adjustable length is performed before the gate region is formed, so that the problem of the length of the light doped drain can be effectively solved.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art to which the present application pertains. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present application shall be included in the scope of the claims of the present application.

Claims (10)

1. A full-isolation transverse double-diffusion metal oxide semiconductor field effect transistor comprises a semiconductor substrate, a source region, a drain region, a gate region, a shallow trench isolation region, a P-type body region, an N-type well region, a P-type well region and an N-type drift region which are positioned on the semiconductor substrate, and is characterized in that the full-isolation transverse double-diffusion metal oxide semiconductor field effect transistor also comprises a gate oxide dielectric layer,

wherein the gate oxide dielectric layer is positioned between the gate region and the N-type drift region,

wherein the drain region comprises a heavily doped drain region and a lightly doped drain region, the source region comprises a heavily doped source region and a lightly doped source region,

wherein the drain lightly doped region and the source lightly doped region are formed by N-type ion lightly doped drain and high-voltage double diffusion, and the drain lightly doped region and the source lightly doped region are formed in front of the gate region,

Wherein, the parameter setting of lightly doped drain includes: the length is 0.4-0.6 um, the depth is 0.2 um-0.3 um, and the concentration is 2e18cm³~6e18cm³，

In which the high pressure is double diffusedThe parameter setting comprises the following steps: the length is 0.4-0.6 um, the depth is 0.3-0.5 um, and the concentration is 1e18cm³~6e18cm³。

2. The fully isolated lateral double diffused metal oxide semiconductor field effect transistor of claim 1, wherein the gate region is a metal gate or a polysilicon gate electrode,

the gate region is connected with the P-type body region and the N-type drift region.

3. The fully isolated LDMOS FET of claim 1 further comprising an N-type buried layer and a P-type epitaxial layer,

the N-type buried layer is located below the N-type trap area, and the P-type epitaxial layer is located below the P-type trap area.

4. The fully isolated LDMOS FET of claim 3, wherein the P-well region comprises a first P-well region and a second P-well region, the first P-well region and the second P-well region are respectively located on two sides of the N-well region and connected to the N-well region,

The fully-isolated transverse double-diffused metal oxide semiconductor field effect transistor further comprises a third P-type well region which is positioned above the N-type well region.

5. The fully isolated LDMOS transistor of claim 4, wherein the P-body region and the N-drift region are located above the third P-well region.

6. The fully isolated LDMOS transistor of claim 5, wherein the N-type drift region comprises first and second N-type drift regions on opposite sides of the P-type body region, respectively.

7. The fully isolated lateral double diffused mosfet of claim 6 wherein said drain region is above said N-type drift region and said source region is above said P-type body region.

8. A method for manufacturing a fully-isolated lateral double-diffused metal oxide semiconductor field effect transistor is characterized by comprising the following steps:

forming an N-type well region and a P-type well region in a selected region of a semiconductor substrate;

Forming a shallow trench isolation region, a P-type body region and an N-type drift region in a selected region of the semiconductor substrate;

forming a drain region over the N-type drift region, a source region over the P-type body region,

the drain region comprises a heavily doped drain region and a lightly doped drain region, and the source region comprises a heavily doped source region and a lightly doped source region;

forming a gate region over the P-type body region and the N-type drift region,

wherein the drain lightly doped region and the source lightly doped region are formed by N-type ion lightly doped drain and high voltage double diffusion,

wherein, the parameter setting of lightly doped drain includes: the length is 0.4-0.6 um, the depth is 0.2 um-0.3 um, and the concentration is 2e18cm³~6e18cm³，

Wherein, the parameter setting of the high-pressure double diffusion comprises the following steps: the length is 0.4-0.6 um, the depth is 0.3-0.5 um, and the concentration is 1e18cm³~6e18cm³。

9. The method of claim 8, wherein the gate region is a metal gate or a polysilicon gate electrode, and the forming the gate region above the P-type body region and the N-type drift region comprises:

forming a gate oxide dielectric layer above the N-type drift region through chemical vapor deposition;

And forming a gate region above the P-type body region and the gate oxide dielectric layer through physical vapor deposition.

10. The method of claim 8, wherein prior to said forming said N-well and P-well regions in said selected region of said semiconductor substrate, said method further comprises:

forming an N-type buried layer and a P-type epitaxial layer on the semiconductor substrate,

the N-type buried layer is located below the N-type trap area, and the P-type epitaxial layer is located below the P-type trap area.

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