CN107425046B - LDMOS device and manufacturing method thereof - Google Patents

LDMOS device and manufacturing method thereof Download PDF

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CN107425046B
CN107425046B CN201610344276.0A CN201610344276A CN107425046B CN 107425046 B CN107425046 B CN 107425046B CN 201610344276 A CN201610344276 A CN 201610344276A CN 107425046 B CN107425046 B CN 107425046B
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well
doping type
semiconductor substrate
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CN107425046A (en
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冯喆韻
马千成
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

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Abstract

The invention provides an LDMOS device and a manufacturing method thereof, wherein the LDMOS device comprises: a semiconductor substrate; a first well region located in the semiconductor substrate; a second well region located in the first well region; the body region and the drift region are positioned in the second well region and are arranged at intervals; the source region and the base region are positioned in the body region and are arranged at intervals; a drain region located in the drift region; the gate structure is positioned on the semiconductor substrate and is connected across the body region and the drift region; the shallow trench isolation structure is positioned between the grid structure and the drain region and is simultaneously positioned in the drift region; and the inversion ion implantation region is positioned on the surface of the second well region between the body region and the drift region. The LDMOS device provided by the invention adopts a full-isolation structure and has high breakdown voltage; the surface inversion ion implantation area is added, the on-resistance is reduced, and the inversion ion implantation area is formed without an additional mask, so that the process cost is reduced.

Description

LDMOS device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LDMOS (laterally diffused metal oxide semiconductor) device.
Background
The LDMOS (Laterally Diffused Metal oxide semiconductor) adopts a double diffusion technology, boron and phosphorus are Diffused twice in the same window, and the channel length can be accurately determined by the difference of the lateral junction depths of the two impurity diffusions. The increasing market for cellular communications has ensured the use of LDMOS transistors and has led to the technology of LDMOS transistors becoming mature. For LDMOS transistors, the on-resistance (Rdson) and the breakdown voltage (BVdss) are the two most important parameters. The smaller the on-resistance is, the stronger the driving capability of the LDMOS is; the larger the breakdown voltage, the higher the reliability of the LDMOS. It is generally desirable for the LDMOS to have a smaller on-resistance and a larger breakdown voltage.
The LDMOS in the power integrated circuit is manufactured by adopting a BCD (Bipolar-CMOS-DMOS) process. The BCD process is a process for manufacturing a bipolar transistor (BJT), a Complementary Metal Oxide Semiconductor (CMOS) and a Diffused Metal Oxide Semiconductor (DMOS) on the same chip, and has the advantages of high transconductance, strong load driving capability, high CMOS integration level and low power consumption of a bipolar device. To be compatible with standard CMOS processes, BCD processes typically employ P-type substrates. How to reduce the cost of the BCD process while improving the product performance is an urgent problem to be solved in the prior art.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides an LDMOS device, which comprises:
a semiconductor substrate;
a first well region in the semiconductor substrate, the first well region having a first doping type;
a second well region in the first well region, the second well region having a second doping type;
the body region and the drift region are arranged in the second well region at intervals, the body region has the second doping type, and the drift region has the first doping type;
the source region and the base region are arranged in the body region at intervals, the source region is provided with a first doping type, and the base region is provided with a second doping type;
a drain region in the drift region, the drain region having a first doping type;
the gate structure is positioned on the semiconductor substrate and is connected across the body region and the drift region;
the shallow trench isolation structure is positioned between the grid structure and the drain region and is simultaneously positioned in the drift region;
and the inversion ion implantation region is positioned on the surface of the second well region between the body region and the drift region and has a first doping type.
Illustratively, isolation regions are formed in the semiconductor substrate outside the first well region, the isolation regions having a second doping type.
Illustratively, isolation structures are formed on the surface of the semiconductor substrate at the boundaries of the second well regions to define active regions.
Illustratively, an isolation structure is formed between the source region and the base region in the body region.
Illustratively, the inversion type ion implantation region and the drift region form a step type ion implantation region.
The invention also provides a manufacturing method of the LDMOS device, which comprises the following steps:
providing a semiconductor substrate;
forming a first well region in the semiconductor substrate, the first well region having a first doping type;
forming a second well region in the first well region, the second well region having a second doping type;
forming an inversion ion implantation region on the surface of the second well region, wherein the inversion ion implantation region has a first doping type
Forming a body region and a drift region which are arranged at intervals in the second well region, wherein the body region has a second doping type, and the drift region has a first doping type;
forming a gate structure on the semiconductor substrate and bridging the body region and the drift region;
forming a source region and a base region which are arranged at intervals in the body region, wherein the source region has a first doping type, and the base region has a second doping type;
and forming a drain region in the drift region, wherein the drain region has a first doping type.
Illustratively, the step of forming the second well region in the first well region further comprises, before or after the step of forming the second well region, a step of forming an isolation structure in the first well region to define an active region.
Illustratively, the isolation structure comprises a shallow trench isolation structure between a subsequently formed gate structure and a drain region.
Illustratively, the body region and the drift region are formed after the step of forming isolation structures in the first well region to define active regions.
Illustratively, the body region and the drift region are formed prior to the step of forming isolation structures in the first well region to define the active region.
Exemplarily, the method further comprises the step of forming an isolation region outside the first well region in the semiconductor substrate, wherein the isolation region has a second doping type.
Illustratively, the step of forming a first well region in the semiconductor substrate includes the step of forming an epitaxial layer having a first doping type on the semiconductor substrate.
Illustratively, the step of forming a first well region in the semiconductor substrate includes the step of performing ion implantation in the semiconductor substrate to form a buried layer having a first doping type.
Illustratively, the inversion type ion implantation region and the drift region form a step type ion implantation region.
Illustratively, the inversion ion implantation region and the second well region are formed in the same process using the same mask.
The LDMOS device provided by the invention adopts a full-isolation structure, so that the device has high breakdown voltage; the surface inversion ion implantation area is added, the on-resistance of the device is reduced, no extra mask is needed for forming the inversion ion implantation area, and the cost of the BCD process is reduced.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a cross-sectional view of a prior art fully isolated LDMOS device;
FIG. 2 is a schematic structural diagram of an LDMOS device of the present invention;
fig. 3 a-3 d are cross-sectional views of devices obtained at various steps in the fabrication of an LDMOS device of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Different from the traditional HS NLDMOS (High Side NLDMOS), the fully-isolated LDMOS is added with DPW (P-type deep well) and can fully isolate the substrate from the drain, so that the breakdown voltage is increased.
FIG. 1 is a schematic structural diagram of a conventional fully-isolated LDMOS device; taking an N-type LDMOS device as an example, an existing NLDMOS device is formed on a P-type silicon substrate (P-sub)101, and a Shallow Trench Isolation (STI)105 is formed on the silicon substrate 101, where the shallow trench isolation 105 is used to isolate active regions. An N-type deep well (DNW)102 is formed on the silicon substrate 101, a P-type isolation (P-ISO)103 is formed outside the N-type deep well, a P-type deep well (DPW)104 is formed on the N-type deep well 102, and a body region (P-body)106 composed of a P-well and a drift region (N-drift)107 composed of an N-type doped region are formed in the P-type deep well 104. A gate structure composed of a gate oxide layer 110, a polysilicon gate 111 and an insulating layer 112 is formed on the surface of the silicon substrate 101, the gate structure is bridged over the body region 106 and the surface of the drift region 107, and the surface of the body region 106 covered by the gate structure is used for forming a channel. A source region 108a of N + region is formed in the body region 106 and is self-aligned to one side of the gate, and a drain region 108b of N + region is formed in the drift region 107 and has a shallow trench isolation 105 to the other side of the gate. A base region 109 is further formed in the body region 106, and the base region 109 is used for adjusting and controlling the potential of the body region. The breakdown voltage of the LDMOS device can be effectively improved by adopting a completely isolated structure, but the on-resistance of the LDMOS device cannot be reduced.
In order to improve the breakdown voltage of the LDMOS device, reduce the on-resistance of the LDMOS device and reduce the cost of the BCD process, the invention provides the LDMOS device, which comprises:
a semiconductor substrate; a first well region having a first doping type in the semiconductor substrate; a second well region of a second doping type located in the first well region; the body region with the second doping type and the drift region with the first doping type are positioned in the second well region and are arranged at intervals; the source regions with the first doping type and the base regions with the second doping type are arranged in the body region at intervals; a drain region of a first doping type located in the drift region; the gate structure is positioned on the semiconductor substrate and is connected across the body region and the drift region; the shallow trench isolation structure is positioned between the grid structure and the drain region and is simultaneously positioned in the drift region; and the surface of the second well region positioned between the body region and the drift region is provided with an inversion ion implantation region of the first doping type.
An isolation region with a second doping type is formed outside the first well region in the semiconductor substrate; forming an isolation structure on the surface of the semiconductor substrate positioned at the boundary of the second well region to define an active region; an isolation structure is formed between the source region and the base region in the body region; the inversion type ion implantation region and the drift region form a step type ion implantation region.
Compared with the prior art, the LDMOS device provided by the invention adopts a full-isolation structure, so that the device has high breakdown voltage; the surface inversion ion implantation area is added, the on-resistance of the device is reduced, no extra mask is needed for forming the inversion ion implantation area, and the cost of the BCD process is reduced.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
[ exemplary embodiment one ]
The following describes in detail an embodiment of the present invention with reference to fig. 2. Taking an N-type LDMOS device as an example, an LDMOS device provided by an embodiment of the present invention includes:
the semiconductor substrate 201 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, Silicon On Insulator (SOI), or the like. For an N-type LDMOS device, the semiconductor substrate 201 is a P-type substrate, and the specific doping concentration thereof is not limited by the present invention.
A first well region 202 of a first doping type is formed in the semiconductor substrate 201. In this embodiment, the first well region is an N-type deep well, and the doped ions of the first well region may include phosphorus ions or arsenic ions, or other elements of main group v, and the concentration of the doped ions may be 1E12/cm2～1E14/cm2. P-type isolation regions 204 are also formed on both sides of the N-type deep well.
A second well region 203 of a second doping type is formed in the first well region 202. For the N-type LDMOS device provided in this embodiment, the second well region is a P-type deep well, and the doped ion concentration is 1E12/cm2～1E14/cm2。
A body region 206 of the second doping type and a drift region 207 of the first doping type are formed in the second well region 203. For the N-type LDMOS device provided by this embodiment, the body region is P-type dopedThe concentration range can be 1E13/cm2～1E14/cm2. For the N-type LDMOS device provided by this embodiment, the drift region is doped N-type, and the doping concentration range may be 1E12/cm2～1E13/cm2. The existence of the drift region can provide the breakdown voltage of the LDMOS device, and meanwhile, the parasitic capacitance between the source electrode and the drain electrode is reduced. Shallow trench isolation Structures (STI)205 are also formed on the semiconductor substrate 201 between the active regions.
An inversion ion implantation region 213 is formed on the surface of the second well region 203 between the body region 206 and the drift region 207, and the inversion ion implantation region 213 is formed in the same step as the second well region 203. The inversion ion implantation region 213 is an N-type ion implantation region in this embodiment. The inversion ion implantation region 213 provides majority carriers for the channel in the on state, reducing the on resistance. And the inversion ion implantation region 213 and the drift region 207 together form a step-type ion implantation region, which improves the distribution of the electric field by the modulation effect on the electric field, thereby improving the breakdown voltage of the device.
A source region 208a of the first doping type is formed in the body region 206. For the N-type LDMOS device provided by this embodiment, the source region 208a is an N + region with a doping concentration of 1E14/cm2～1E16/cm2. A base region 209 of the second doping type is further formed in the body region 206, the base region 209 is composed of a P + doping region, a shallow trench isolation structure 205 is isolated from the source region 206a, and the base region 209 is used for adjusting and controlling the potential of the body region. A drain region 208b of the first doping type is formed in the drift region 207. For the N-type LDMOS device provided by this embodiment, the drain region 208b is an N + region with a doping concentration of 1E14/cm2～1E16/cm2。
A gate structure composed of a gate oxide layer 210, a polysilicon gate 211 and a gate sidewall 212 is formed on the surface of the silicon substrate 201, the gate structure is bridged over the surfaces of the body region 206 and the drift region 207, one side of the gate structure is self-aligned with the source region 208a, and a shallow trench isolation 205 is formed between the other side of the gate structure and the drain region 208 b. The surface of body region 206 covered by the gate structure is used to form a channel.
It should be noted that, in the embodiment of the present invention, the LDMOS device further includes: a light source region (not shown) formed by lightly doping the body region 206 with the gate structure as a mask, and a light drain region (not shown) formed by lightly doping the drift region; and the extraction regions of the N-type deep well and the P-type deep well.
Compared with the prior art, the LDMOS device provided by the invention adopts a full-isolation structure, so that the device has high breakdown voltage; the surface inversion ion implantation area is added, the on-resistance of the device is reduced, no extra mask is needed for forming the inversion ion implantation area, and the cost of the BCD process is reduced.
[ second exemplary embodiment ]
Referring to fig. 3 a-3 d, schematic cross-sectional views of a device obtained according to the fabrication method provided by the present invention are shown.
First, a semiconductor substrate 301 is provided, and a constituent material of the semiconductor substrate may be undoped single crystal silicon, impurity-doped single crystal silicon, Silicon On Insulator (SOI), or the like. By way of example, in the present embodiment, the semiconductor substrate is made of a single crystalline silicon material. For an N-type LDMOS device, the semiconductor substrate 301 is a P-type substrate, and the specific doping concentration thereof is not limited by the present invention.
A first well region 302 of a first doping type is formed in a semiconductor substrate 301. The first well region 302 formed in this embodiment is an N-type deep well. The doping process for forming the deep N-well 302 is performed at an ion concentration of 1E12/cm2～1E14/cm2And implanting phosphorus ions by an ion implantation process with ion energy of 1000-2000 Kev and an incident angle of 0-10 inclined angles, and then performing high-temperature annealing at 1000-1200 ℃ for 5-10 hours. The method of forming the first well region 302 may also be to form an epitaxial layer or buried layer of the first doping type, which will not be described in detail herein.
Ion implantation and diffusion are performed outside the first well region 302 to form an isolation region 303 with a second doping type.
A second well region 304 having a second doping type is formed in the first well region 302. The second well 304 formed in this embodiment is a P-type deep well. The doping process is to make the ion concentration be 1E12/cm2～1E14/cm2And implanting boron ions by an ion implantation process with ion energy of 1000-2000 Kev and an incident angle of 0-10 inclined angles, and then performing high-temperature annealing at 1000-1200 ℃ for 5-10 hours. The surface inversion ion implantation region 313 is formed by performing inversion ion implantation on the surface of the second well region using the same mask during this step. The ions injected in the embodiment are phosphorus ions, and the ion concentration is 1E 12-1E 14/cm2. The formed inversion ion implantation region 313 and the drift region form a step-type ion implantation region.
Before or after the second well region 304 is formed in the first well region 302, isolation structures 305 are formed in the first well region 302 to define active regions. The isolation structure is also positioned between the subsequently formed gate structure and the drain region. The process used in this embodiment is a shallow trench isolation process, and specifically, a silicon nitride layer and a silicon oxide layer are formed on a semiconductor substrate, the silicon nitride layer and the silicon oxide layer above a drift region are sequentially etched away by dry etching with a photoresist layer having the drift region as a mask to form a trench structure, the photoresist layer having a pattern of the drift region is removed, and a shallow trench isolation structure is formed by oxide layer deposition and planarization.
Before or after the step of forming isolation structures in the first well region to define active regions, P-wells 306 are formed in the second well region 304 as body regions. The doping concentration range of the body region can be 1E12/cm2～1E14/cm2The ion implantation energy is 100-800 eV. While a drift region 307 is formed in the P-type deep well 304. The drift region can improve the breakdown voltage of the LDMOS device and reduce the parasitic capacitance between the source and the drain, for an N-type LDMOS device, the drift region is doped N-type, the doping concentration of the drift region is generally lower than that of the drain, and in the embodiment, the doping concentration range of the drift region 307 can be 1E10/cm2～1E12/cm2。
A base region 308a is formed by implanting P + -type impurities in the body region, and a source region 309 is formed by implanting N + -type impurities. An N + -type impurity is implanted in the drift region to form a drain region 308 b. The doping concentration of the source region 308a and the drain region 308b may be the same, thus, twoCan be formed simultaneously with doping. In the present embodiment, the N-type doping concentration range of the source region 308a and the drain region 308b may be 1E12/cm2～1E14/cm2。
The forming step of the gate structure comprises the following steps: forming a gate dielectric layer 310 on the surfaces of the partial body region 306 and the partial drift region 307; and forming a gate electrode layer 311 covering the surface of the gate dielectric layer 310. The gate dielectric layer 310 is used for isolating the body region 306, the drift region 307 and the gate electrode layer 311, and the forming process of the gate dielectric layer 310 is a deposition process, such as a chemical vapor deposition process. The gate dielectric layer 310 is made of silicon oxide or a high-K dielectric material, which is not described herein again; the gate electrode layer 311 is used as a gate electrode of the LDMOS device, and the forming process is a deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. The material of the gate electrode layer 311 may be polysilicon or metal. And depositing silicon dioxide on the side wall of the gate structure to form a gate side wall (spacer) 312.
To this end, the process steps performed by the method according to the first exemplary embodiment of the present invention are completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device.
Compared with the prior art, the LDMOS device provided by the invention adopts a full-isolation structure, so that the device has high breakdown voltage; the surface inversion ion implantation area is added, the on-resistance of the device is reduced, no extra mask is needed for forming the inversion ion implantation area, and the cost of the BCD process is reduced.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (14)

1. An LDMOS device, comprising:
a semiconductor substrate;
a first well region in the semiconductor substrate, the first well region having a first doping type;
a second well region in the first well region, the second well region having a second doping type;
the body region and the drift region are arranged in the second well region at intervals, the body region has the second doping type, and the drift region has the first doping type;
the source region and the base region are arranged in the body region at intervals, the source region is provided with a first doping type, and the base region is provided with a second doping type;
a drain region in the drift region, the drain region having a first doping type;
the gate structure is positioned on the semiconductor substrate and is connected across the body region and the drift region;
the shallow trench isolation structure is positioned between the grid structure and the drain region and is simultaneously positioned in the drift region;
and the inversion ion implantation region is positioned on the surface of the second well region between the body region and the drift region, has a first doping type, and is formed by using the same mask in the same process with the second well region.
2. The LDMOS device of claim 1, wherein an isolation region is formed in the semiconductor substrate outside the first well region, the isolation region having a second doping type.
3. The LDMOS device set forth in claim 1 wherein an isolation structure is formed on a surface of the semiconductor substrate bordering said second well region to define an active region.
4. The LDMOS device of claim 1, wherein an isolation structure is formed between a source region and a base region within the body region.
5. The LDMOS device of claim 1, wherein the inversion ion implantation region and the drift region constitute a step-type ion implantation region.
6. A manufacturing method of an LDMOS device is characterized by comprising the following steps:
providing a semiconductor substrate;
forming a first well region in the semiconductor substrate, the first well region having a first doping type;
forming a second well region in the first well region, the second well region having a second doping type;
forming an inversion ion implantation area on the surface of the second well area by using the same mask as the second well area, wherein the inversion ion implantation area has a first doping type;
forming a body region and a drift region which are arranged at intervals in the second well region, wherein the body region has a second doping type, and the drift region has a first doping type;
forming a gate structure on the semiconductor substrate and bridging the body region and the drift region;
forming a source region and a base region which are arranged at intervals in the body region, wherein the source region has a first doping type, and the base region has a second doping type;
and forming a drain region in the drift region, wherein the drain region has a first doping type.
7. The method of claim 6 further comprising, before or after the step of forming the second well region in the first well region, a step of forming an isolation structure in the first well region to define an active region.
8. The method of claim 7, wherein the isolation structure comprises a shallow trench isolation structure between a subsequently formed gate structure and a drain region.
9. The method of claim 7, wherein the body region and the drift region are formed after the step of forming isolation structures in the first well region to define active regions.
10. The method of claim 7, wherein the body region and the drift region are formed before the step of forming isolation structures in the first well region to define the active region.
11. The method of claim 6, further comprising the step of forming isolation regions outside the first well region in the semiconductor substrate, the isolation regions having a second doping type.
12. The method of manufacturing of claim 6, wherein the step of forming a first well region in the semiconductor substrate comprises the step of forming an epitaxial layer having a first doping type on the semiconductor substrate.
13. The method of claim 6, wherein the step of forming the first well region in the semiconductor substrate comprises the step of performing ion implantation in the semiconductor substrate to form a buried layer having the first doping type.
14. The method according to claim 6, wherein the inversion ion implantation region and the drift region form a step-type ion implantation region.
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