KR101015529B1 - Lateral DMOS transistor and method of fabricating thereof - Google Patents

Lateral DMOS transistor and method of fabricating thereof Download PDF

Info

Publication number
KR101015529B1
KR101015529B1 KR1020080093350A KR20080093350A KR101015529B1 KR 101015529 B1 KR101015529 B1 KR 101015529B1 KR 1020080093350 A KR1020080093350 A KR 1020080093350A KR 20080093350 A KR20080093350 A KR 20080093350A KR 101015529 B1 KR101015529 B1 KR 101015529B1
Authority
KR
South Korea
Prior art keywords
region
well
body region
layer
type
Prior art date
Application number
KR1020080093350A
Other languages
Korean (ko)
Other versions
KR20100034299A (en
Inventor
이상용
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080093350A priority Critical patent/KR101015529B1/en
Publication of KR20100034299A publication Critical patent/KR20100034299A/en
Application granted granted Critical
Publication of KR101015529B1 publication Critical patent/KR101015529B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Abstract

The LDMOS transistor of the present invention includes an N well formed in a semiconductor substrate, an epi layer grown on the N well, a body region formed in the N well and an epi layer, and a drift formed in the N well and epi layer at a predetermined distance from the body region. A region, a field insulating layer formed in the N well and the drift region, a first channel region bypassing the body insulation layer from the body region to the lower end of the field insulation layer, and a second channel region and the first channel region formed in the epi layer between the body region and the drift region. And a gate electrode formed over the first and second channel regions.

LDMOS, epi layer, channel area

Description

LMDMOS transistor and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to an LDMOS transistor and a method of manufacturing the same.

Ideally, the power semiconductor device is preferably a device capable of operating at a high voltage close to the theoretical breakdown voltage of the semiconductor.

Accordingly, when an external system using high voltage is controlled by an integrated circuit, the integrated circuit needs an element for high voltage control therein, and such an element requires a structure having a high breakdown voltage. do.

That is, in the drain or source of the transistor to which the high voltage is integrated, the punch-through voltage between the drain and the source and the semiconductor substrate and the breakdown voltage between the drain and the source and the well or the substrate should be greater than the high voltage. .

Among high voltage semiconductor devices, LDMOS (lateral diffused MOS), which is a high voltage MOS, has a structure suitable for high voltage because the channel region and the drain electrode are separated by a drift region and controlled by the gate electrode.

1 is a cross-sectional view showing an example of the structure of a conventional LDMOS transistor.

Referring to FIG. 1, an N-type epitaxial layer 103 is grown on a P-type semiconductor substrate 101, N-type impurities are implanted in the N-well 105, and a P-type body region (in the N-well 105) is formed. 107 and an N-type drift region 109 are formed.

In the N-type drift region 109, a drain region 111 doped with N + -type impurities is formed, and a source region 113 doped with N + -type impurities is formed in the P-type body region 107. A P + type source contact region 115 is formed adjacent to the source region 113.

The gate electrode 119 is formed on the semiconductor substrate 101 via the gate insulating layer 117, and the field insulating layer 120 is formed on the surface of the N-type drift region 109 to improve breakdown voltage characteristics. do.

Meanwhile, a channel region (dotted line display) is formed under the gate electrode between the contact surface where the P-type body region 107 and the N-type drift region 109 contact and the source region 113.

At this time, the channel region is not formed in a straight line due to the field insulating film 120, and bypasses the path of the current flow as it bypasses the circumference of the bottom of the field insulating film 120, in which case Rdson It will cause a loss on the side.

That is, when the semiconductor device is a technology of 0.25 μm or less, a shallow trench isolation (STI) is generally used, and the current flow path of the LDMOS transistor to which the STI is applied to the drift region is bypassed around the lower end of the STI. This causes a great loss in terms of Rdson.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an LDMOS transistor and a method of manufacturing the same, which improve an Rdson loss and improve a current flow path of an LDMOS transistor according to the use of STI.

LDMOS transistor of the present invention for the above object is an N well formed in a semiconductor substrate, an epi layer grown on the N well, a body region formed in the N well and the epi layer, and a predetermined distance from the body region A drift region formed in the N well and the epi layer, a field insulation layer formed in the N well and the drift region, a first channel region bypassing the body region from the body region to a lower end of the field insulation layer, and the body region And a second channel region formed in the epitaxial layer between the drift region and a gate electrode formed over the first and second channel regions.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming an N well in a semiconductor substrate, growing an epi layer on the N well, and a body region in the N well and the epi layer. Forming a drift region in the N well and the epi layer at a predetermined distance from the body region, forming a field insulating layer in the N well and the drift region, and forming the body region. And forming a gate electrode on the semiconductor substrate between the drift region and the drift region.

The LDMOS transistor and the method of manufacturing the same according to the present invention form a surface current flow path in addition to the current flow path around the bottom of the STI, thereby implementing a dual current flow path, thereby improving the Rdson characteristics of the LDMOS transistor. Has

Hereinafter, an embodiment of an LDMOS transistor according to the present invention will be described with reference to the accompanying drawings.

2 shows a cross-sectional view of an LDMOS transistor of the present invention.

As shown in FIG. 2, an N-type epitaxial layer 203 is grown on the P-type semiconductor substrate 201, and an N-type epitaxial layer 204 is formed on the surface of the N well 205. The P type body region 207 and the N type drift region 209 are formed in the N well 205 and the N type epi layer 204.

In the N-type drift region 209, a drain region 211 doped with N + -type impurities is formed, and a source region 213 doped with N + -type impurities is formed in the P-type body region 207. A P + type source contact region 215 is formed adjacent to the source region 213.

The gate electrode 219 is formed on the semiconductor substrate 201 via the gate insulating layer 217, and the field insulating layers 220 and 221 are formed on the surface of the N-type drift region 209 to improve breakdown voltage characteristics. It is.

Current flow path A formed from the P-type body region 207 to the bottom of the field insulating layer 220 to the N-type drift region 209 and the N-type drift region 209 from the P-type body region 207. A linear current flow path B is formed in the N-type epitaxial layer 204 in a straight line.

Here, the linear current flow path (B) is a current flow path formed by growing the N-type epitaxial layer 204 on the N well 205, which is characteristically, compared with the conventional art, and in addition to the existing current flow path (A) Form a dual current flow path.

Accordingly, the dual current flow path of the present invention can greatly improve the Rdson loss problem of the LDMOS transistor due to the use of the STI.

 Hereinafter, an embodiment of a method of manufacturing an LDMOS transistor according to the present invention will be described with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a method of manufacturing the LDMOS transistor of the present invention.

As shown in FIG. 3A, the N-type epitaxial layer 203 is grown on the semiconductor substrate 201 using epitaxial growth.

The N well 205 is formed by ion implantation into the N-type epitaxial layer 203, and the field insulating layers 220 and 221 are formed in the N well 205. For example, field insulating layers 220 and 221 made of field oxide are formed using conventional LOCOS techniques.

The field insulating layers 220 and 221 are formed on the upper surface of the N well 205 and are formed at a distance apart from the P-type body region 207 by a predetermined distance.

As shown in FIG. 3B, an N-type epitaxial layer 204 is formed on the upper surface of the N well 205 using epitaxial growth. The N-type epitaxial layer 204 is formed using a TCS (SiHCl 3 ) at a temperature of 1000 to 1200 ° C., a pressure atmospheric pressure (760torr), or a reduced pressure (20torr) condition. PH 3 may be used as the dopant.

As shown in FIG. 3C, impurity ions are implanted into the N well 205 and the N type epi layer 204 to form the N type drift region 209 and the P type body region 207.

After implanting N-type impurity ions, such as phosphorus ions, in a dose of about 2E12 on the exposed N well 205 and the N-type epitaxial layer 204, for example, at a constant temperature and time, for example, 1100 ° C to 1200 The drift region 209 is formed by performing an impurity diffusion process at a temperature of about 7-9 hours.

Subsequently, a P-type body region 207 is formed by selectively implanting P-type impurity ions, for example boron (B) ions, in a predetermined dose using a predetermined ion implantation mask (not shown).

Part of the P-type body region 207 serves as a channel region of the LDMOS transistor.

As shown in FIG. 3D, a source contact region 213 doped with P + impurities and a source region 215 doped with N + impurities are formed in the P-type body region 207.

The gate electrode 219 is formed on the semiconductor substrate 201 via the gate insulating layer 217.

N between the P-type body region 207 and the drift region 209 and the channel region bypassing the P-type body region 207 from the P-type body region 207 to the bottom of the field insulating layer 220 according to the bias voltage applied to the gate electrode 219. A channel region is formed in the type epi layer 204.

That is, a current flow path A is formed from the P-type body region 207 to the bottom of the field insulating layer 220, and the N-type epi layer 204 between the P-type body region 207 and the drift region 209. A straight current flow path B is formed at.

Here, the linear current flow path (B) is a current flow path formed by growing the N-type epitaxial layer 204 on the N well 205, which is characteristically, compared with the conventional art, and in addition to the existing current flow path (A) Form a dual current flow path.

Due to the dual current flow path, the current flows more than before, so that Ron and Rsp are lowered.

Accordingly, the dual current flow path of the present invention can greatly improve the Rdson loss problem of the LDMOS transistor due to the use of the STI.

1 is a cross-sectional view of a general LDMOS transistor.

2 is a cross-sectional view of an LDMOS transistor of the present invention.

3A to 3D are sectional views of the manufacturing process of the LDMOS transistor of the present invention.

Claims (4)

An N well formed in the semiconductor substrate; An epitaxial layer grown on the N well; A body region formed in the N well and the epi layer; A drift region formed in the N well and the epi layer at a predetermined distance from the body region; A field insulating layer formed in the N well and the drift region; A first channel region bypassing the body region to a lower end of the field insulating layer; A second channel region formed in the epi layer between the body region and the drift region; And A gate electrode formed over the first and second channel regions; LDMOS transistor comprising a. Forming an N well in the semiconductor substrate; Growing an epitaxial layer on the N well; Forming a body region in the N well and the epi layer; Forming a drift region in the N well and the epi layer at a distance from the body region; Forming a field insulating layer in said N well and said drift region; Forming a gate electrode on the semiconductor substrate between the body region and the drift region; LDMOS transistor manufacturing method comprising a. The method of claim 2, And the epitaxial layer is formed by epitaxial growth. The method of claim 3, wherein The epi layer is formed using a TCS (SiHCl 3 ) at a temperature of 1000 ~ 1200 ℃, pressure atmospheric pressure (760torr) or reduced pressure (20torr) conditions, manufacturing a LDMOS transistor characterized in that using a PH 3 as a dopant (dopant) Way.
KR1020080093350A 2008-09-23 2008-09-23 Lateral DMOS transistor and method of fabricating thereof KR101015529B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080093350A KR101015529B1 (en) 2008-09-23 2008-09-23 Lateral DMOS transistor and method of fabricating thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080093350A KR101015529B1 (en) 2008-09-23 2008-09-23 Lateral DMOS transistor and method of fabricating thereof

Publications (2)

Publication Number Publication Date
KR20100034299A KR20100034299A (en) 2010-04-01
KR101015529B1 true KR101015529B1 (en) 2011-02-16

Family

ID=42212470

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080093350A KR101015529B1 (en) 2008-09-23 2008-09-23 Lateral DMOS transistor and method of fabricating thereof

Country Status (1)

Country Link
KR (1) KR101015529B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103177967A (en) * 2011-12-22 2013-06-26 三星电子株式会社 Semiconductor devices and methods of forming the same
US8674436B2 (en) 2011-11-22 2014-03-18 Hyundai Motor Company Lateral double diffusion metal-oxide semiconductor device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004152979A (en) 2002-10-30 2004-05-27 Fuji Electric Device Technology Co Ltd Semiconductor device
KR20070044689A (en) * 2005-10-25 2007-04-30 삼성전자주식회사 Lateral dmos transistor and method of fabricating thereof
KR20080025507A (en) * 2006-09-18 2008-03-21 동부일렉트로닉스 주식회사 Device of protecting an electro static discharge for high voltage and manufacturing method thereof
KR20100020688A (en) * 2008-08-13 2010-02-23 주식회사 동부하이텍 Ldmos semiconductor and method for fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004152979A (en) 2002-10-30 2004-05-27 Fuji Electric Device Technology Co Ltd Semiconductor device
KR20070044689A (en) * 2005-10-25 2007-04-30 삼성전자주식회사 Lateral dmos transistor and method of fabricating thereof
KR20080025507A (en) * 2006-09-18 2008-03-21 동부일렉트로닉스 주식회사 Device of protecting an electro static discharge for high voltage and manufacturing method thereof
KR20100020688A (en) * 2008-08-13 2010-02-23 주식회사 동부하이텍 Ldmos semiconductor and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8674436B2 (en) 2011-11-22 2014-03-18 Hyundai Motor Company Lateral double diffusion metal-oxide semiconductor device and method for manufacturing the same
CN103177967A (en) * 2011-12-22 2013-06-26 三星电子株式会社 Semiconductor devices and methods of forming the same

Also Published As

Publication number Publication date
KR20100034299A (en) 2010-04-01

Similar Documents

Publication Publication Date Title
US9466700B2 (en) Semiconductor device and method of fabricating same
US10861966B2 (en) Vertical trench power devices with oxygen inserted Si-layers
US8772871B2 (en) Partially depleted dielectric resurf LDMOS
US9070576B2 (en) Semiconductor device and related fabrication methods
KR100861213B1 (en) Semiconductor device and method for manufactruing of the same
US20090134402A1 (en) Silicon carbide mos field-effect transistor and process for producing the same
US9000518B2 (en) Semiconductor device and related fabrication methods
US9660020B2 (en) Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
CN105321824B (en) Method for manufacturing semiconductor device
CN107425046B (en) LDMOS device and manufacturing method thereof
KR100381347B1 (en) Semiconductor deⅴice and method of manufacturing the same
US9385229B2 (en) Semiconductor device with improved breakdown voltage
KR20160018322A (en) Method for manufacturing semiconductor device
US9111992B2 (en) Semiconductor device including an n-well structure
KR20110078621A (en) Semiconductor device, and fabricating method thereof
JP5834200B2 (en) Semiconductor device
US10217828B1 (en) Transistors with field plates on fully depleted silicon-on-insulator platform and method of making the same
US10615079B2 (en) Semiconductor device and method for manufacturing the same
US20180301548A1 (en) Silicon carbide transistor
TWI576989B (en) Method of integrating high voltage devices
KR101015529B1 (en) Lateral DMOS transistor and method of fabricating thereof
US20110204423A1 (en) Semiconductor device and manufacturing method thereof
KR101198938B1 (en) Method for isolation of high voltage device
US9985092B2 (en) PowerMOS
CN116884832B (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee