CN113764502A - LDMOS semiconductor device and manufacturing method thereof - Google Patents

LDMOS semiconductor device and manufacturing method thereof Download PDF

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CN113764502A
CN113764502A CN202010489558.6A CN202010489558A CN113764502A CN 113764502 A CN113764502 A CN 113764502A CN 202010489558 A CN202010489558 A CN 202010489558A CN 113764502 A CN113764502 A CN 113764502A
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region
conductivity type
type
isolation structure
gate
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CN113764502B (en
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李敏
季明华
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a semiconductor device and a forming method thereof, wherein the semiconductor device comprises: a first region having a first conductivity type; a second region of a second conductivity type on the first region; a first drift region of the second conductivity type located within the second region; an isolation structure is arranged on one side of the first drift region; and a third region of the first conductivity type located below the isolation structure; a drain region and a source region in the first and second drift regions, respectively. According to the scheme, the third region is formed by doping below the isolation structure, due to the charge sharing effect, the first drift region can be completely exhausted before the transverse electric field reaches the critical breakdown electric field, so that the breakdown voltage between the source and the drain of the semiconductor device is greatly improved, and meanwhile, more electrons can be led out from the first drift region by the third region, so that the on-resistance between the source and the drain of the semiconductor device is reduced.

Description

LDMOS semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LDMOS semiconductor device and a manufacturing method thereof.
Background
Laterally Diffused Metal Oxide Semiconductor (LDMOS) is compatible with CMOS (complementary metal oxide semiconductor) technology and can withstand high breakdown voltage, and thus is widely used in power integrated circuits, such as radio frequency power amplifiers facing mobile phone base stations, and also in High Frequency (HF), Very High Frequency (VHF), and Ultra High Frequency (UHF) broadcast transmitters, microwave radars, navigation systems, and the like. The LDMOS technology as a new generation base station amplifier brings higher power peak-to-average ratio, higher gain and linearity, and simultaneously brings higher data transmission rate for multimedia services.
However, as mobile communication applications continue to increase the demand for high performance LDMOS devices, it is difficult to achieve higher performance without reducing BV (Breakdown Voltage). For example, a trade-off needs to be made between BVds (breakdown voltage between source and drain) and Rdson (on-resistance between source and drain).
Disclosure of Invention
The scheme aims to provide the LDMOS semiconductor device and the manufacturing method thereof so as to solve the problem that the breakdown voltage and the on-resistance are difficult to balance.
In order to achieve the purpose, the technical scheme is as follows:
in a first aspect, the present solution provides an LDMOS semiconductor device comprising:
a first region having a first conductivity type;
a second region of a second conductivity type on the first region;
a first drift region of the second conductivity type located within the second region;
an isolation structure is arranged on one side of the first drift region; and the number of the first and second groups,
a third region of the first conductivity type located under the isolation structure;
a drain region of the second conductivity type located in the first drift region; a source region having a second conductivity type in the second region; and the source region and the drain region are respectively positioned at two sides of the isolation structure.
In a preferred embodiment, the doping concentration of the second region is less than the doping concentration of the first drift region.
In a preferred embodiment, the doping concentration range of the third region is: 1e12～1e14。
In a preferred embodiment, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductive type is an N type, and the second conductive type is a P type.
In a preferred embodiment, the first drift region has a second drift region thereunder.
In a preferred embodiment, the semiconductor device further includes: a well region of the first conductivity type located in the second region; the first drift region and well region are spaced apart by a second region; the source region is located in the well region.
In a preferred embodiment, the semiconductor device further includes: a gate structure located on the second region.
In a preferred embodiment, the gate structure includes: a gate insulator layer gate insulation layer on the second region, a gate on the gate insulator layer gate insulation layer, and spacers on sides of the gate; wherein a portion of the gate and a portion of the spacer are over the isolation structure.
In a preferred embodiment, the semiconductor device further includes: a body region adjoining a side of the source region remote from the isolation structure.
In a preferred embodiment, the isolation structure is a trench body formed based on an STI process; and the tank body is filled with an insulator.
In a preferred embodiment, the semiconductor device further includes: isolating the contact hole; the isolation contact hole penetrates through the dielectric layer covering the isolation structure and extends into the groove body;
the third region is formed by implantation doping of the isolation contact hole.
In a second aspect, the present disclosure provides a method for manufacturing an LDMOS semiconductor device, the method comprising the steps of:
providing a first region having a first conductivity type as a substrate;
forming a second region having a second conductivity type on the substrate;
forming a first drift region in the second region;
forming an isolation structure on one side of the first drift region;
doping is carried out below the isolation structure, and a third region with the first conduction type is formed;
forming a drain region having a second conductivity type in the first drift region; forming a source region having a second conductivity type in the second region; and the source region and the drain region are respectively positioned at two sides of the isolation structure.
In a preferred embodiment, the doping concentration of the second region is less than the doping concentration of the first drift region.
In a preferred embodiment, the doping concentration range of the third region is: 1e12～1e14。
In a preferred embodiment, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductive type is an N type, and the second conductive type is a P type.
In a preferred embodiment, a second drift region is formed below the first drift region.
In a preferred embodiment, the steps of the method further comprise: forming a well region having a first conductivity type in the second region; the first drift region and well region are spaced apart by a second region; the source region is located in the well region.
In a preferred embodiment, the steps of the method further comprise: and forming a gate structure on the second region.
In a preferred embodiment, the gate structure includes: a gate insulator layer gate insulation layer on the second region, a gate on the gate insulator layer gate insulation layer, and spacers on sides of the gate; wherein a portion of the gate and a portion of the spacer are over the isolation structure.
In a preferred embodiment, the steps of the method further comprise: and forming a body region on one side of the source region far away from the isolation structure.
In a preferred embodiment, in the step of forming the isolation structure on one side of the first drift region, the isolation structure is a trench body formed based on an STI process, and an insulator is filled in the trench body.
In a preferred embodiment, doping is performed below the isolation structure, and the step of forming the third region having the first conductivity type includes:
covering a dielectric layer above the isolation structure;
utilizing an etching process to penetrate through the dielectric layer and extend into the groove body to form an isolation contact hole;
doping and forming a third region below the isolation structure through the isolation contact hole by using an ion implantation process
Advantageous effects
According to the scheme, the third region is formed by doping below the isolation structure, due to the charge sharing effect, the first drift region can be completely exhausted before the transverse electric field reaches the critical breakdown electric field, so that the breakdown voltage between the source and the drain of the semiconductor device is greatly improved, and meanwhile, more electrons can be led out from the first drift region by the third region, so that the on-resistance between the source and the drain of the semiconductor device is reduced.
According to the scheme, the third region can be formed by doping below the isolation structure through the isolation contact hole and the ion implantation process directly after the contact hole is isolated through etching, the mask process is not required to be added, so that the process steps of manufacturing the semiconductor device are reduced under the condition of improving the performance of the semiconductor device, the manufacturing efficiency of the semiconductor is improved, and the manufacturing cost is reduced.
Drawings
Fig. 1 shows a schematic structural view of a semiconductor device according to this embodiment.
Fig. 2 is a schematic view showing a method for manufacturing a semiconductor device according to the present embodiment.
Fig. 3 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Fig. 4 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Fig. 5 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Fig. 6 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Fig. 7 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Fig. 8 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Fig. 9 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Fig. 10 shows a cross-sectional view of a structure at one stage in the fabrication of an LDMOS device according to one embodiment of the present scheme.
Description of the reference symbols
1. A first region;
2. a second region;
3. a first drift region;
4. a second drift region;
5. an isolation structure;
6. a third region;
7. a well region;
8. a gate structure; 801. a gate insulating layer; 802. a gate electrode; 803. a spacer;
9. a source region;
10. a body region;
11. a drain region;
12. a dielectric layer;
13. and isolating the contact holes.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of the components in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated in the drawings, but may also include deviations in shapes that result, for example, from manufacturing processes. In the drawings, the length and size of some layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like parts. It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.
Aiming at the balance problem existing between the breakdown voltage and the on-resistance of the LDMOS device in the prior art, in order to meet the requirement of mobile communication on the performance of the LDMOS device, the scheme provides a semiconductor device, which comprises: a first region having a first conductivity type; a second region of a second conductivity type on the first region; a first drift region of the second conductivity type located within the second region; an isolation structure is arranged on one side of the first drift region; and a third region of the first conductivity type located below the isolation structure.
The LDMOS device forms a third region below the isolation structure, the third region being adjacent to a boundary of the first drift region. By introducing the third region, the drift region can be completely depleted before the transverse electric field reaches the critical breakdown electric field due to the charge sharing effect, so that the breakdown voltage between the source and the drain of the semiconductor device is greatly improved, and meanwhile, more electrons can be led out from the drift region by the third region, so that the on-resistance between the source and the drain of the semiconductor device is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
As shown in fig. 1, a schematic diagram of a structure (i.e., an LDMOS device) of an embodiment of the semiconductor device according to the present embodiment is shown. The LDMOS device includes: a first region 1 having a first conductivity type; a second region 2 of a second conductivity type located on the first region 1; a first drift region 3 of the second conductivity type located within the second region 2; an isolation structure 5 is arranged on one side of the first drift region 3; and a third region 6 of the first conductivity type located below the isolation structure 5.
In the scheme, the first region 1 serves as a substrate of a semiconductor device, and the substrate serves as a process platform for forming an LDMOS device subsequently. Wherein, the substrate can adopt a silicon substrate.
In other embodiments, the substrate material can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, which can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride base or gallium arsenide substrate, etc.).
When the LDMOS device is a P-type semiconductor device, the substrate is doped in an N type; and when the LDMOS device is an N-type semiconductor device, the substrate is doped in a P-type mode. In this embodiment, the LDMOS device is an N-type LDMOS device, the substrate is doped with P-type impurity ions, and the P-type impurity ions may be one or more of boron ions, gallium ions, and indium ions.
In the scheme, the second region 2 is a Deep N-well (DNW), and the DNW is arranged on the first region 1, so that coupling noise generated by the substrate can be reduced, and adverse effects on the LDMOS device are avoided. In particular, the LDMOS device is applied to a chip which is sensitive to noise.
In this scheme, the first drift region 3 is located in the second region 2, and the conductivity type of the first drift region 3 is opposite to that of the first region 1. In one embodiment, if the conductivity type of the first region 1 is P-type, the conductivity type of the first drift region 3 is N-type. In another embodiment, if the conductivity type of the first region 1 is N-type, the conductivity type of the first drift region 3 is P-type. Furthermore, the doping concentration of the second region 2 is smaller than the doping concentration of the first drift region 3.
In this scheme, a second drift region 4 is provided below the first drift region 3, and the conductivity type of the second drift region 4 is the same as that of the second drift region 4. In one example, the second drift region 4 may be a High Voltage N-type drift region (HVNF). By forming the HVNF layer, the mobility of device carriers can be improved.
In this scheme, an isolation structure 5 is formed on one side of the first drift region 3. The Isolation structure 5 may be a Shallow Trench Isolation (STI). That is, the isolation structure 5 may include: a trench formed at one side of the first drift region 3 and an insulator layer (e.g., silicon dioxide) filled in the trench.
In this scheme, a third region 6 is formed below the isolation structure 5 at a position adjacent to the boundary of the first drift region 3, and the conductivity type of the third region 6 is the same as that of the first region 1. In one embodiment, if the conductivity type of the first region 1 is P-type and the conductivity type of the first drift region 3 is N-type, the conductivity type of the third region 6 is P-type. In another embodiment, if the conductivity type of the first region 1 is N-type and the conductivity type of the first drift region 3 is P-type, the conductivity type of the third region 6 is N-type.
In this embodiment, the third region 6 may be a P-ring (P-ring), and the third region 6 is formed under the isolation structure 5 by an ion implantation process. The third region 6 may be P-ring, and the doping concentration range thereof is: 1e12～1e14(ii) a The doping area of the third region 6 mayThe depth is 0.35-0.7um, and the width is 0.02-0.05 um. In one embodiment, in the case where the first drift region 3 is N-type and the second drift region 4 is N-type, the third region 6 is P-type; the third region 6 has a doping concentration of 1e12The doping area is: the depth is 0.35um and the width is 0.02 um. In one embodiment, in the case where the first drift region 3 is N-type and the second drift region 4 is N-type, the third region 6 is P-type; the third region 6 has a doping concentration of 1e13The doping area is: the depth is 0.5um and the width is 0.03 um. In another example, in the case where the first drift region 3 is P-type and the second drift region 4 is P-type, the third region 6 is N-type; the third region 6 has a doping concentration of 1e14The doping area is: the depth is 0.7um and the width is 0.05 um. The above is an example of doping the third region 6, and it should be understood by those skilled in the art that the doping concentration and area can be arbitrarily configured according to the above concentration and area range according to the actual performance requirement.
In this scheme, a well region 7 having the first conductivity type is formed in the second region 2, and the well region 7 is spaced apart from the first drift region 3 by the second region 2. The well region 7 is of the same conductivity type as the first region 1. In one embodiment, if the conductivity type of the first region 1 is P-type, the conductivity type of the well region 7 is P-type. In another embodiment, if the conductivity type of the first region 1 is N type, the conductivity type of the well region 7 is N type.
In this scheme, a gate structure 8 is formed over the second region 2. The gate structure 8 is used to control the on and off of the LDMOS channel. The gate structure 8 includes: a gate insulating layer 801 on the second region 2, a gate 802 on the gate insulating layer 801, and a spacer 803 on a side of the gate 802; a portion of the gate 802 and a portion of the spacer 803 are located over the isolation structure 5. The gate insulating layer 801 may be formed using silicon oxide; the gate electrode 802 may be made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, or other materials; the spacers 803 may be silicon oxide or silicon nitride. In one embodiment, the gate structure 8 includes: silicon dioxide on the second region 2, polysilicon on the silicon dioxide, and silicon nitride on the sides of the polysilicon.
In other embodiments, the gate structure 8 may also be a metal gate (metal gate) structure, and correspondingly, the gate insulating layer 801 is a high-k gate dielectric layer 12, and the gate 802 is a gate electrode. The material of the high-k gate dielectric layer 12 is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide, for example: HfO2、ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3Etc.; the material of the gate 802 is a conductive material, such as: w, Al, Cu, Ag, Au, Pt, Ni, or Ti.
In other embodiments, the material of the spacer 803 may be one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall spacer may have a single-layer structure or a stacked-layer structure.
In the scheme, a source region 9 is formed in the well region 7, and a drain region 11 is formed in the first drift region 3; the source region 9 and the drain region 11 are respectively located at two sides of the gate structure 8. Both the source region 9 and the drain region 11 are of the second conductivity type. In one embodiment, in the case where the first drift region 3 is N-type and the well region 7 is P-type, both the source region 9 and the drain region 11 are N-type. In another embodiment, when the first drift region 3 is P-type and the well region 7 is N-type, both the source region 9 and the drain region 11 are P-type. In addition, the doping concentration of the source region 9 is greater than that of the well region 7, and the doping concentration of the drain region 11 is greater than that of the first drift region 3. In addition, the drain region 11 adjoins the isolation structure 5.
In this scheme, a body region 10 is formed in the well region 7, and the body region 10 is adjacent to one side of the source region 9 far away from the gate structure 8. The body region 10 has the same conductivity type as the well region 7. In one embodiment, well region 7 is P-type, and body region 10 is P-type. In another embodiment, well region 7 is N-type and body region 10 is N-type. In addition, the doping concentration of the body region 10 is greater than that of the well region 7 to reduce contact resistance.
In the scheme, a dielectric layer 12 covers the isolation structure 5, the dielectric layer 12 is used for providing a process platform for forming the isolation contact hole 13, a conductive structure is introduced through the isolation contact hole 13, and the conductive structure is electrically isolated from other electric connection structures. The isolation contact hole 13 penetrates through the dielectric layer 12 and extends into the groove body. In one embodiment, after forming the isolation contact hole 13, the third region 6 is formed under the isolation structure 5 by an ion implantation process using the isolation contact hole 13.
Correspondingly, the scheme also provides a forming method of the semiconductor device. The method can improve the breakdown voltage of the formed LDMOS device and improve the performance of the device. Fig. 2 to fig. 10 are schematic structural diagrams of an embodiment of a method for forming a semiconductor device according to the present invention and corresponding steps. In particular, the amount of the solvent to be used,
as shown in fig. 2, a flow chart of a method for manufacturing a semiconductor device according to this embodiment is shown. The method comprises the following steps:
step S1, providing a first region 1 having a first conductivity type as a substrate;
step S2, forming a second region 2 having a second conductivity type on the substrate;
step S3, forming a first drift region 3 in the second region 2;
step S4, forming an isolation structure 5 on one side of the first drift region 3;
step S5, doping below the isolation structure 5 to form a third region 6 with the first conductivity type;
step S6, forming a drain region having a second conductivity type in the first drift region; forming a source region having a second conductivity type in the second region; and the source region and the drain region are respectively positioned at two sides of the isolation structure.
Next, a detailed description will be given of a specific process of the method for forming a semiconductor device according to the present embodiment, with reference to fig. 3 to 10.
A first region 1 having a first conductivity type is provided as a substrate structure. For example, doping may be performed on a substrate (e.g., a silicon substrate) to form the first region 1. The first conductivity type may be P-type or N-type. In other embodiments, the substrate material can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, which can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride base or gallium arsenide substrate, etc.). In one embodiment, when the LDMOS device is an N-type semiconductor device, a silicon substrate is P-doped to form a P-type substrate. Wherein, the P-type impurity can be one or more of boron ion, gallium ion and indium ion.
As shown in fig. 3, a second region 2 having a second conductivity type is formed on the first region 1. The second conductivity type may be P-type or N-type, and the second conductivity type is opposite to the first conductivity type. The second region 2 is thus of opposite conductivity type to the first region 1. For example, a separate region is isolated above a P-type substrate, which is formed by lightly N-type doping (i.e., DNW) to isolate the coupling noise generated by the substrate. Wherein, the N-type impurity ions are one or more of phosphorus ions, arsenic ions and antimony ions. In one embodiment, the second region 2 may be formed by performing light doping of phosphorus ions to silicon through an ion implantation process. Since the second region 2 is lightly doped, the doping concentration of the second region 2 is less than that of the first drift region 3.
As shown in fig. 4, a first drift region 3 is formed at one side in the second region 2, and the first drift region 3 is used for forming a high resistance region to provide a breakdown voltage for forming an LDMOS device. The process of forming the first drift region 3 may be a diffusion process or an ion implantation process. In this embodiment, the first drift region 3 is formed by an ion implantation process.
Specifically, the process for forming the first drift region 3 in the second region 2 includes: a first pattern layer (not shown in the figure) is formed on the surface of the second region 2, the first pattern layer is provided with an opening exposing a part of the second region 2, and ion implantation is performed along the opening into the exposed second region 2 by taking the first pattern layer as a mask to form a first drift region 3.
In one embodiment, the conductivity type of the first drift region 3 is opposite to the conductivity type of the first region 1, i.e. the ion type implanted in the first drift region 3 is opposite to the ion type doped in the first region. The type of ion implantation of the first drift region 3 is N-type impurity ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions and antimony ions.
In one embodiment, the material of the first pattern layer is a photoresist material. After the first drift region 3 is formed, the first pattern layer is removed by using a wet photoresist removal or ashing process.
Further, in one example, the method steps may further include: a second drift region 4 is formed below the first drift region 3. The second drift region 4 may be a High Voltage N drift (HVNF) region formed by doping N-type impurity ions through an ion implantation process. And the HVNF layer is used for improving the carrier migration performance of the device. The type of ion implantation of the second drift region 4 is N-type impurity ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions and antimony ions.
As shown in fig. 5, an isolation structure 5 is formed at one side of the first drift region 3. The Isolation structure 5 may form a Shallow Trench Isolation (STI) by an etching process. In one embodiment, the isolation structure 5 comprises: a trench formed at one side of the first drift region 3 and silicon dioxide filled in the trench.
As shown in fig. 6, a well region 7 having the first conductivity type is formed in the second region 2; the first drift region 3 and the well region 7 are spaced apart by the second region 2. Specifically, the formation of the well region 7 may adopt an ion implantation process: first, a second pattern layer (not shown) is formed on the surface of the second region 2, the second pattern layer covers the second region 2 and has an opening exposing a portion of the second region 2, and ion implantation is performed along the opening into the exposed second region 2 by using the second pattern layer as a mask to form a well region 7. The type of ion implantation in the well region 7 is P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions and indium ions. The material of the second pattern layer is the same as that of the first pattern layer and is a photoresist material. In addition, after the well region 7 is formed, the second pattern layer is removed by a wet photoresist removal or ashing process.
It should be noted that, in the actual manufacturing process, the two process sequences of forming the first drift region 3 and forming the well region 7 may be interchanged, that is, the well region 7 is formed first, and then the first drift region 3 is formed.
As shown in fig. 7, next, a source region 9 may be formed in the well region 7 and a drain region 11 may be formed in the first drift region 3 by a doping process. The source region 9 and the drain region 11 are on either side of the gate structure 8. The source region 9 and the drain region 11 may be formed by an ion implantation process.
Specifically, the process for forming the source region 9 and the drain region 11 in the second region 2 includes: first, a third pattern layer (not shown) is formed on the surface of the second region 2, the third pattern layer has an opening exposing a portion of the well region 7 and a portion of the first drift region 3, and ion implantation is performed along the opening into the exposed well region 7 and the exposed first drift region 3, respectively, with the third pattern layer as a mask, so as to form a drain region 11 in the first drift region 3, and form a source region 9 in the well region 7. After the source region 9 and the drain region 11 are formed, the third pattern layer is removed. The material of the third pattern layer may be a photoresist material, and the removal process of the photoresist material is as described above and is not described herein again.
In the process of forming the source region 9 and the drain region 11, the type of implanted ions implanted into the source region 9 and the drain region 11 is N-type impurity ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions and antimony ions.
As shown in fig. 8, a body region 10 is formed in the well region 7, the body region 10 being contiguous with the source region 9. The process of forming the body region 10 is an ion implantation process, and the specific process flow is similar to the specific forming process of the source region 9 and the drain region 11, and is not described herein again.
In the process of forming the body region 10, the ion type of the body region 10 is P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions and indium ions.
In addition, during the formation of the semiconductor structure, after the formation of the drain region 11, the source region 9 and the contact region, a thermal annealing process is usually performed, so as to repair crystal lattices and activate doped ions.
As shown in fig. 9, a gate structure 8 is formed over the second region 2, and the gate structure 8 may include: a gate insulator layer 801 on the first region 1, a gate 802 on the gate insulator layer 801, and a spacer 803 on a side of the gate 802; a portion of the gate 802 and a portion of the spacer 803 are located over the isolation structure 5.
Specifically, the process for forming the gate structure 8 includes: forming spacers 803 on both sides of the gate structure 8 by deposition and etching processes; forming a gate insulating layer 801 on the second region 2 by using a chemical vapor deposition or physical vapor deposition process between the spacers 803 on both sides; after the gate insulating layer 801 is formed, a semiconductor layer is formed on the gate insulating layer 801, and the semiconductor layer is planarized by chemical mechanical polishing or the like to form a gate electrode 802 located between the spacers 803.
As shown in fig. 10, doping is performed below the isolation structure 5 to form a third region 6 having the first conductivity type. The third region 6 adjoins the boundary of the first drift region 3. The conductivity type of the third region 6 is the same as the conductivity type of the first region 1. Specifically, the process of forming the third region 6 is: covering a dielectric layer 12 above the isolation structure 5; by utilizing an etching process, penetrating through the dielectric layer 12 and extending into the groove body to form an isolation contact hole 13; through the isolation contact hole 13, the third region 6 is formed under the isolation structure 5 using an ion implantation process. The third region 6 may be P-ring, and the doping concentration range thereof is: 1e12～1e14(ii) a The doping area of the third region 6 can be 0.35-0.7um in depth and 0.02-0.05um in width. In the scheme, after the isolation contact hole 13 is formed, the P-ring can be formed below the isolation structure 5 through the isolation contact hole 13 by using an ion implantation process without adding a mask process, so that the forming process of the semiconductor device is simplified.
After the third region 6 is formed, covering photoresist on the dielectric layer 12, wherein the photoresist has openings for exposing partial dielectric layer 12, and the openings respectively correspond to the positions of the source region 9, the gate electrode 802 and the drain region 11; etching is performed along the openings to form contact holes communicating with the source region 9, the body region 10, the drain region 11 and the gate electrode 802, respectively, as shown in fig. 1. After the contact holes are formed, the photoresist is removed.
Through simulation experiments, the on-resistance/breakdown voltage performance of the LDMOS semiconductor device is more excellent, and compared with a transmission STI structure, the on-resistance/breakdown voltage performance can be improved by more than 18%.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (14)

1. An LDMOS semiconductor device, comprising:
a first region having a first conductivity type;
a second region of a second conductivity type on the first region;
a first drift region of the second conductivity type located within the second region;
a trench isolation structure is arranged on one side of the first drift region;
a third region of the first conductivity type located under the isolation structure;
a drain region of the second conductivity type located in the first drift region; a source region having a second conductivity type in the second region; and the source region and the drain region are respectively positioned at two sides of the isolation structure.
2. The LD of claim 1The MOS semiconductor device is characterized in that the doping concentration range of the third region is as follows: 1e12～1e14。
3. The LDMOS semiconductor device set forth in claim 1 wherein said first conductivity type is P-type and said second conductivity type is N-type; or, the first conductive type is an N type, and the second conductive type is a P type.
4. The LDMOS semiconductor device set forth in claim 1 wherein said first drift region has a second drift region thereunder.
5. The LDMOS semiconductor device set forth in claim 1 further comprising:
a well region of the first conductivity type located in the second region;
the first drift region and well region are spaced apart by a second region;
the source region and the body region adjacent to one side of the source region far away from the isolation structure are both positioned in the well region.
6. The LDMOS semiconductor device set forth in claim 1 further comprising: a gate structure located on the second region;
the gate structure includes: a gate insulating layer on the second region, a gate on the gate insulating layer, and spacers on sides of the gate; wherein a portion of the gate and a portion of the spacer are over the isolation structure.
7. The LDMOS semiconductor device set forth in claim 1 further comprising: isolating the contact hole; the isolation contact hole penetrates through the dielectric layer covering the isolation structure and extends into the groove body;
the third region is formed by implantation doping of the isolation contact hole.
8. A method of fabricating an LDMOS semiconductor device, the method comprising the steps of:
providing a first region having a first conductivity type as a substrate;
forming a second region having a second conductivity type on the substrate;
forming a first drift region in the second region;
forming an isolation structure on one side of the first drift region;
doping is carried out below the isolation structure, and a third region with the first conduction type is formed;
forming a drain region having a second conductivity type in the first drift region; forming a source region having a second conductivity type in the second region; and the source region and the drain region are respectively positioned at two sides of the isolation structure.
9. The method of claim 8, wherein the third region has a doping concentration range of: 1e12～1e14。
10. The method of claim 8, wherein the first conductivity type is P-type and the second conductivity type is N-type; or, the first conductive type is an N type, and the second conductive type is a P type.
11. The method of claim 8, wherein a second drift region is formed below the first drift region.
12. The method of claim 8, wherein the method steps further comprise: forming a well region having a first conductivity type in the second region; the first drift region and well region are spaced apart by a second region;
and the source region and the body region adjacent to one side of the source region far away from the isolation structure are formed in the well region.
13. The method of claim 8, wherein the method steps further comprise: forming a gate structure on the second region;
a gate insulating layer on the second region, a gate on the gate insulating layer, and spacers on sides of the gate; wherein a portion of the gate and a portion of the spacer are over the isolation structure.
14. The method of claim 8, wherein doping beneath the isolation structure to form a third region having the first conductivity type comprises:
covering a dielectric layer above the isolation structure;
utilizing an etching process to penetrate through the dielectric layer and extend into the groove body to form an isolation contact hole;
and doping below the isolation structure through the isolation contact hole by using an ion implantation process to form a third region.
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