KR20110037030A - Semiconductor device and a method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to increase the break down voltage margin by forming a first conductive impurity layer in the second conductive well on the lower of the element isolation layer. CONSTITUTION: A second conductive well is formed on the first conductivity semiconductor substrate. An element isolation film(130) is formed within the second conductive well. The first conductive dopant layer is formed within the second conductive well of the lower part of the element isolation layer. A gate(150) is formed on upper part the second conductive well in order to be overlapped with the one side of the element isolation layer.

Description

Semiconductor device and a method for manufacturing the same

The present invention relates to a semiconductor device, and more particularly to a lateral diffused MOS (LDMOS) that can reduce the on resistance between the source and drain.

As the power semiconductor device, a device capable of operating at a high voltage close to the theoretical breakdown voltage of the semiconductor is preferable. Accordingly, when an external system using a high voltage is controlled by an integrated circuit, the integrated circuit needs a semiconductor device for high voltage control therein. Such a high voltage semiconductor device requires a structure having a high breakdown voltage.

In other words, in a drain or source of a transistor to which a high voltage is directly applied, the punch-through voltage between the drain and the source and the semiconductor substrate and the breakdown voltage between the drain and the source and the well or the substrate must be greater than the high voltage to which the transistor is applied. do.

Lateral diffused MOS (LDMOS) is a representative high voltage MOS among high voltage semiconductor devices. In order to flow current horizontally, the LDMOS horizontally arranges a drain and a drift region between the channel and the drain to secure a high breakdown voltage.

For high voltage semiconductor devices such as LDMOS, research is being conducted to increase the breakdown voltage and to lower the on resistance (eg, specific on-resistance) between the source and the drain.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device capable of reducing on-resistance and increasing breakdown voltage, and a method of manufacturing the same.

The semiconductor device according to the embodiment of the present invention for achieving the above object is a second conductive well formed in the first conductive semiconductor substrate, a device isolation film formed in the second conductive well, the lower portion of the device isolation film A first conductive impurity layer is formed in the second conductive well, and a gate is formed on the second conductive well so as to overlap a portion of one side of the device isolation layer. In addition, the semiconductor device may further include a source and a drain formed on the semiconductor substrate at both sides of the gate.

The semiconductor device may further include a second conductive second epitaxial layer formed between the semiconductor substrate and the second conductive well. The semiconductor device may further include a second conductive first epitaxial layer formed on the surface of the second conductive well, and the gate may be formed on the second conductive first epitaxial layer.

The semiconductor device may further include a first conductive type body formed on an inner surface of the second conductive type first epitaxial layer and the second conductive type well so as to overlap a portion of one side of the gate. In addition, the semiconductor device may include a source formed on a surface of a first conductive type body adjacent to one side of the gate, and a drain formed on inner surfaces of a first conductive type first epi layer and a second conductive type well on the other side of the device isolation layer. It may further include.

The semiconductor device may further include a second conductive buried layer formed between the semiconductor substrate and the second conductive well.

The first conductivity type impurity layer may be formed in a second conductivity type well adjacent to the bottom of the device isolation layer, or may be formed in a second conductivity type well adjacent to the bottom and sidewalls of the device isolation layer.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming a second conductive well in a first conductive semiconductor substrate, and forming a first conductive type in the second conductive well. Forming an impurity layer, forming an isolation layer on a surface of the second conductivity type well above the first conductivity type impurity layer so as to contact the first conductivity type impurity layer, and overlapping a portion of one side of the isolation layer Forming a gate over the second conductivity type well.

The method of manufacturing the semiconductor device may further include forming a source and a drain on the semiconductor substrate at both sides of the gate. The method of manufacturing the semiconductor device may further include forming a second conductive first epitaxial layer on the first conductive semiconductor substrate after forming the device isolation layer and before forming the gate.

The method of manufacturing the semiconductor device may further include forming a first conductive body on an inner surface of the second conductive well so as to overlap a portion of one side of the gate.

The method of manufacturing the semiconductor device may further include forming a first conductive body on an inner surface of the second conductive first epitaxial layer and the second conductive well so as to overlap a portion of one side of the gate. can do. The method of manufacturing the semiconductor device may further include forming a source by injecting a second conductivity type impurity into an inner surface of the first conductivity type body adjacent to the gate, and a second conductivity type agent adjacent to the other side of the device isolation layer. The method may further include forming a drain on the inner surface of the first epitaxial layer and the second conductivity type well.

A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention can form an additional epitaxial layer on a semiconductor substrate on which an isolation layer is formed, and form a current flow passage through the additional epitaxial layer to improve the overall current density. There is.

In addition, the first conductive impurity layer may be formed in the second conductive well under the device isolation layer to increase the breakdown voltage margin and increase the concentration of the second conductive well as the breakdown voltage margin increases. There is an effect that can improve the on-resistance.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

1 is a cross-sectional view of an LDMOS (Lateral Diffused Metal-Oxide Semiconductor) device according to an embodiment of the present invention. Referring to FIG. 1, the LDMOS device may include a second conductive first epitaxial layer 115, a second conductive well 120, and a first conductive impurity layer 125 formed on the first conductive semiconductor substrate 110. ), A device isolation layer 130, a second conductive second epitaxial layer 135, a first conductive body 140, a gate 150, and a second conductive source and drain 165 and 175. In this case, the first conductivity type may be P type and the second conductivity type may be N type.

The second conductivity type first epitaxial layer 115 is formed on the first conductivity type semiconductor substrate 110, and the second conductivity type well 120 is formed on the first conductivity type first epitaxial layer 115. .

The device isolation layer 125 is formed in a portion of the surface of the second conductivity type well 120. The first conductivity type impurity layer 125 is formed in the second conductivity type well 120 under the device isolation layer 125. The first conductivity type impurity layer 125 is formed in the second conductivity type well 120 adjacent to the bottom of the device isolation layer 125 and is spaced apart from the second conductivity type first epitaxial layer 115. .

The second conductivity type second epitaxial layer 135 is formed on the surface of the second conductivity type well 120 on which the device isolation layer 130 is formed. Although the device isolation layer 130 illustrated in FIG. 1 has a structure formed by a shallow trench isolation (STI) method, the present invention is not limited thereto, and the device isolation layer may be in the form of a field oxide film formed by a LOCOS (LOCal Oxidation of Silicon) method. Can be. In this case, the second conductivity type second epitaxial layer 135 is also formed on the device isolation layer 130.

The second conductive body 140 is formed to be spaced apart from the device isolation layer 130 in another portion of the surface of the second conductive type second epitaxial layer 135 and the second conductive type well 120.

The gate 150 is formed on the second conductive second epitaxial layer 135 so as to partially overlap with each of the device isolation layer 130 and the first conductive type body 140. For example, some regions of one side of the gate 150 overlap with some regions of one side of the device isolation layer 135, and some regions of the other side of the gate 150 are part of the first conductivity type body 135. And may be formed on the second conductivity type second epitaxial layer 135 so as to overlap with each other.

The gate 150 may include a gate oxide layer 152 and a gate electrode 154 that are sequentially stacked, and spacers 156 formed on sidewalls of the gate electrode 155.

The drain 175 is formed on the surface of the second conductivity type second epi layer 135 and the second conductivity type well 120 on the other side of the device isolation layer 130. Source 165 is also formed in the surface of first conductive body 140 adjacent to the other side of gate 150.

The second conductivity type second epitaxial layer 135 formed on the device isolation layer 130 between the source 165 and the drain 175 may form a current flow path 182.

2 is a cross-sectional view of an LDMOS device according to another embodiment of the present invention. In the LDMOS illustrated in FIG. 2, a first conductive buried layer 210 is formed instead of the second conductive epitaxial layer 115 illustrated in FIG. 1. That is, an N- buried layer (NBL) 210 may be formed between the first conductive semiconductor substrate 110 and the second conductive well 120.

1 and 2, the LDMOS (Lateral Diffused Metal-Oxide Semiconductor) forms a first current flow path 184 around the device isolation layer 130 on which the first conductivity type impurity layer 125 is formed. In addition, the second current flow passage 182 passing through the second conductive type second epitaxial layer 135 is formed on the device isolation layer 130.

As described above, the LDMOS of the present invention shown in FIGS. 1 and 2 forms the multi-current flow passages 182 and 184, thereby reducing the on resistance between the source 165 and the drain 175 (eg, specific on-resistance). Can be reduced.

In addition, the breakdown voltage may be increased by reducing a surface electric field by the first conductivity type impurity layer 125 formed under the device isolation layer 130.

That is, a depletion layer may be additionally formed near the junction between the first conductivity type impurity layer 125 and the second conductivity type well 120 at the reverse bias, thereby reducing the surface electric field.

As the surface electric field is reduced and the breakdown voltage margin is increased, the drift length can be reduced. In addition, as the breakdown voltage margin is increased, the concentration of the second conductivity type well, which is a drift region, may be increased, thereby improving on resistance.

4 is a cross-sectional view of an LDMOS device according to another embodiment of the present invention. The LDMOS device shown in FIG. 4 is the same as the LDMOS device shown in FIG. 1 except for the first conductivity type impurity layer 410.

The first conductivity type impurity layer 410 illustrated in FIG. 4 is formed in the second conductivity type well 125 adjacent to the bottom and sidewalls of the device isolation layer 125. Since the length of the junction is longer than that shown in FIG. 1, the length of the depletion layer may be increased to increase the surface electric field reduction effect.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 3A, a first conductivity type semiconductor substrate 310 is prepared. The second conductive epitaxial layer is grown on the first conductive semiconductor substrate 310. For example, the second conductive epitaxial layer can be formed by an epitaxial growth method. In this case, the first conductivity type may be P type and the second conductivity type may be N type.

A second conductive well 320, for example, an N-type well 320, is formed in the upper region of the second conductive epitaxial layer grown by implanting and diffusing a second conductive impurity into the upper region of the grown second conductive epitaxial layer. Form. That is, the implanted impurities may be diffused only in the upper region of the second conductive epitaxial layer 320 to form the second conductive well 320. As a result, the second conductive well layer 320 may be formed in the upper region of the grown second conductive epitaxial layer, and the second conductive first epitaxial layer 315 may be formed in the lower region. That is, a structure in which the second conductivity type first epitaxial layer 315 and the second conductivity type well 320 are sequentially stacked on the semiconductor substrate 310 may be formed.

3A illustrates a structure in which the second conductive type first epitaxial layer 315 and the second conductive type well 320 are sequentially stacked on the semiconductor substrate 310, but embodiments of the present disclosure are not limited thereto. As illustrated in FIG. 2, a structure in which the second conductive buried layer 210 and the second conductive well 120 are sequentially stacked on the semiconductor substrate 310 may be formed. For example, after injecting a second conductivity type impurity into the semiconductor substrate 310, the second conductivity type epitaxial layer is grown. In addition, a second conductivity type impurity is additionally implanted into the grown upper region of the second conductivity type epi layer. A second conductive buried layer 210 is formed in the lower region of the second conductive epitaxial layer by performing a diffusion process on the impurities injected into each of the semiconductor substrate and the grown second conductive epitaxial upper region. The second conductivity type well 120 may be formed in the region.

Next, as shown in FIG. 3B, a trench 325 is formed on the surface of the second conductivity type well 320. In addition, a first conductivity type impurity layer 330 is formed by implanting a first conductivity type impurity into the second conductivity type well 320 below the trench 325.

For example, selective impurity implantation may be performed in the second conductivity type well 320 under the trench 325 so that the first conductivity type impurity layer 330 may be adjacent to the bottom of the trench 235. It can only be formed inside.

Also, by adjusting a range in which impurities are injected into the second conductivity type well 320 under the trench 325, the first conductivity type impurity layer 410 is formed on the bottom and sidewalls of the trench 235 as shown in FIG. 4. It may be formed in the adjacent second conductivity type well 320. In this case, the first conductivity type impurity layer 410 may be formed to be spaced apart from each of the second conductivity type second epitaxial layer 135 and the drain 175.

Next, as shown in FIG. 3C, an isolation material is embedded in the trench 325 to form the device isolation layer 340. For example, the isolation layer 340 may be formed by depositing an insulating material, for example, an oxide layer, on the entire surface of the semiconductor substrate 310 on which the trench 325 is formed, and then performing a planarization process.

Next, as shown in FIG. 3D, a second conductive second epitaxial layer 345 is formed on the entire surface of the semiconductor substrate 310 on which the second conductive well 320 having the device isolation layer 340 is formed. In this case, the thickness of the second conductive second epitaxial layer 345 may be smaller than the thickness of the second conductive first epitaxial layer 315. In addition, the second conductivity type second epitaxial layer 345 is also formed on the device isolation layer 340.

Next, as shown in FIG. 3E, first conductive impurities are selectively injected into a portion of the second conductive second epi layer 345 and the second conductive well 320 to be spaced apart from the device isolation layer 340. The first conductive body 350 is formed. In this case, the first conductivity type body 350 may be formed in a portion of the surface of the second conductivity type second epi layer 345 and the second conductivity type well 320.

Next, as shown in FIG. 3F, the gate 360 is formed on the second conductive second epitaxial layer 345.

The gate 360 is formed to partially overlap each of the first conductivity type body 350 and the device isolation layer 340. For example, a portion of one side of the gate 360 may overlap a portion of one side of the isolation layer 340, and a portion of the other side may overlap a portion of the first conductivity type body 350.

The gate 360 may include a gate oxide layer 362, a gate electrode 364, and a spacer 366.

For example, an oxide film and polysilicon are sequentially formed on the entire surface of the second conductivity-type second epitaxial layer 345. The oxide layer and the polysilicon are patterned using photo and etching processes to form a gate oxide layer 362 and a gate electrode 364 partially overlapping each of the device isolation layer 340 and the first conductive type body 350. can do. A spacer 366 is formed on sidewalls of the gate oxide film 362 and the gate electrode 364.

That is, a portion of one side of each of the gate oxide layer 362 and the gate electrode 364 overlaps with a portion of one side of the isolation layer 340, and a portion of the other side of the gate oxide layer 362 and a portion of the first conductivity type body 350 It can be patterned to overlap with.

Next, a second conductive type impurity is implanted into the inner surface of the first conductive type body 350 adjacent to the gate 360 to form a source 375, and a second epi adjacent to the other side of the device isolation layer 340. A drain 377 is formed on the inner surface of the layer 345 and the second conductivity type well 320. In this case, the source 375 and the drain 377 may be simultaneously formed through one impurity implantation process.

As described above, according to the method of manufacturing a semiconductor device, that is, an LDMOS device, an additional epitaxial layer 345 is formed on a semiconductor substrate on which an isolation layer 340 is formed, and a current flow path 382 passes through the additional epitaxial layer 345. ) To improve the overall current density.

In addition, the first conductivity type impurity layer 330 may be formed in the second conductivity type well 320 under the device isolation layer 340 to increase the breakdown voltage margin. Since the concentration of the mold well 320 may be increased, the on resistance may be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view of an LDMOS device according to an embodiment of the present invention.

2 is a sectional view of an LDMOS device according to another embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4 is a sectional view of an LDMOS device according to another embodiment of the present invention.

Claims (18)

A second conductivity type well formed on the first conductivity type semiconductor substrate; An isolation layer formed in the second conductivity type well; A first conductivity type impurity layer formed in a second conductivity type well under the device isolation layer; And And a gate formed over the second conductivity type well so as to overlap a portion of one side of the device isolation layer. The method of claim 1, wherein the semiconductor device, The semiconductor device further comprises a source and a drain formed on the semiconductor substrate on both sides of the gate. The method of claim 1, wherein the semiconductor device, And a second conductivity type first epitaxial layer formed between the semiconductor substrate and the second conductivity type well. The method of claim 1, wherein the semiconductor device, And a second conductive second epitaxial layer formed on the surface of the second conductivity type well in which the device isolation layer is formed. And the gate is formed on the second conductive second epitaxial layer. The method of claim 4, wherein the semiconductor device, And a first conductive type body formed on an inner surface of the second conductive type second epitaxial layer and the second conductive type well so as to overlap a portion of one side of the gate. The method of claim 5, wherein the semiconductor device, A source formed on a first conductive body surface adjacent to one side of the gate; And And a drain formed on an inner surface of the second conductive type second epitaxial layer and the second conductive type well of the other side of the device isolation layer. The method of claim 4, wherein the semiconductor device, And a second conductive buried layer formed between the semiconductor substrate and the second conductive well. The method of claim 1, wherein the first conductivity type impurity layer, And a second conductivity type well adjacent the bottom of the device isolation layer. The method of claim 1, wherein the first conductivity type impurity layer, And a second conductivity type well adjacent to the bottom and sidewalls of the device isolation layer. Forming a second conductivity type well in the first conductivity type semiconductor substrate; Forming a first conductivity type impurity layer in the second conductivity type well; Forming a device isolation layer in a second conductivity type well above the first conductivity type impurity layer to contact the first conductivity type impurity layer; And  Forming a gate over the second conductivity type well so as to overlap a portion of one side of the device isolation layer. The method of claim 10, wherein the manufacturing method of the semiconductor device is And forming a source and a drain in the semiconductor substrate at both sides of the gate. The method of claim 10, wherein the manufacturing method of the semiconductor device is Before forming the second conductivity type well in the first conductivity type semiconductor substrate, forming a second conductivity type first epi layer under the second conductivity type well. . The method of claim 10, wherein the manufacturing method of the semiconductor device is Forming a second conductivity type second epitaxial layer on the surface of the second conductivity type well formed in the device isolation layer; And the gate is formed on the second conductive second epitaxial layer. The method of claim 13, wherein the manufacturing method of the semiconductor device is And forming a first conductive body on an inner surface of the second conductive second epitaxial layer and the second conductive well so as to overlap a portion of the gate side. Manufacturing method. The method of claim 14, wherein the manufacturing method of the semiconductor device is Implanting a second conductivity type impurity into the inner surface of the first conductivity type body adjacent the gate to form a source; And And forming a drain on an inner surface of the second conductive type second epitaxial layer and the second conductive type well adjacent to the other side of the isolation layer. Forming a second conductivity type first epi layer and a second conductivity type well that are sequentially stacked on the first conductivity type semiconductor substrate; Forming a trench in the second conductivity type well; Forming a first conductivity type impurity layer by injecting a first conductivity type impurity into the second conductivity type well under the trench; Embedding an insulating material in the trench to form an isolation layer; Forming a second conductive second epitaxial layer on a surface of the semiconductor substrate on which the device isolation layer is formed; And And forming a gate on the second conductive second epitaxial layer to overlap a portion of one side of the device isolation layer. The method of claim 16, wherein the forming of the first conductivity type impurity layer comprises: And forming the first conductivity type impurity layer only in a second conductivity type well adjacent to the bottom of the trench. The method of claim 17, wherein the forming of the first conductivity type impurity layer comprises: And forming the first conductivity type impurity layer in a second conductivity type well adjacent to the bottom and sidewalls of the trench.

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