JP7253523B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device including a high-voltage field effect transistor and a method for manufacturing the semiconductor device.

a first region having a source, drain and gate formed in a well structure of a first conductivity, at least one of the source and drain being of a second conductivity opposite the first conductivity and forming a first drift region; A field effect transistor is disclosed having a second region that is biconductive and has a higher dopant concentration than the first region, and a third region that is second conductive and has a higher dopant concentration than the second region. ).

Also, a multi-gate laterally diffused metal-oxide semiconductor (LDMOS) device, a semiconductor-on-insulator (SOI) support structure in which substantially symmetrical inner LDMOS regions and asymmetric edge-near LDMOS regions are located; deep trench isolation (DTI) walls extending into the structure and substantially terminating the edge-proximal LDMOS region; a drain region of a first conductivity type proximate the top surface of the asymmetric edge-proximal LDMOS region; a doped SC buried layer (BL) region underlying a portion of the asymmetric edge-proximal LDMOS region and proximate a deep trench isolation wall of opposite conductivity type to the drain region of the asymmetric edge-proximal LDMOS region; A structure has been disclosed (Patent Document 2). Providing a doped SC buried layer (BL) region is said to enhance the electric field exhibited by the second LDMOS region associated with the DTI wall and avoid source-drain breakdown.

Also, an asymmetric heterodoped metal oxide ( ^AH2MOS ) semiconductor device comprising: an insulated gate on top of a substrate and disposed between a source region and a drain region; a heterodoped tub region having a dopant of a second conductivity type and a source region disposed within the tub region and having a dopant of a first conductivity type opposite to the second conductivity type; a buffer region having a dopant of a second conductivity type heterodoped and a drift region disposed inside the buffer region having a dopant of the first conductivity type; and a high concentration of the dopant of the first conductivity type disposed in the drift region. A semiconductor device comprising a drain tap region comprising a heavily doped region is disclosed in US Pat.

Vertical capacitive depletion field effect transistors (VDCFETs) including interleaved drift and gate regions, with an insulator separating the gate region from the drift region to capacitively deplete the drift region Japanese Patent Laid-Open No. 2002-200000 discloses a configuration in which a gate region is configured as a drift region with a graded or non-uniform doping profile, and a source electrode is coupled to the drift region to form an ohmic or Schottky connection. The vertical capacitive depletion field effect transistor is said to be capable of providing a high breakdown voltage and a lower conduction resistance.

U.S. Pat. No. 9,748,383 JP 2014-11455 A Japanese Patent Application Laid-Open No. 2008-507140 Chinese Patent Publication No. 102184952

As indicated in the above prior art, it is desired to achieve a high breakdown voltage in semiconductor devices comprising field effect transistors. On the other hand, in order to increase the capacity of the field effect transistor, it is desirable to be able to increase the current flowing between the source and the drain.

One aspect of the present invention is a semiconductor device comprising a substrate of a first conductivity type, a drift region within said substrate of a second conductivity type opposite said first conductivity type, and within said drift region said a field effect transistor having a drain region that is of the second conductivity type and has a higher dopant concentration than a peripheral portion of the drift region; The drain region is spaced apart from the gate electrode by a predetermined distance, and the dopant concentration of the second conductivity type in the channel region including at least part of the region overlapping the gate electrode in the drift region is A profile in which the dopant concentration increases from the end of the drift region in the channel region under the gate electrode toward the drain region, then the dopant concentration increase rate decreases, and then the dopant concentration increase rate increases again. A semiconductor device characterized by:

Here, after the concentration of the dopant of the second conductivity type in the channel region increases from the end portion of the drift region in the channel region under the gate electrode toward the drain region to a first concentration, The dopant concentration may exhibit a stepped profile in which the dopant concentration rate of increase decreases to maintain the first concentration, and then the dopant concentration increase rate increases again to a second concentration higher than the first concentration. preferred.

Moreover, it is preferable that the operating voltage is 20 V or more and 60 V or less.

Also, it is preferable to have a second insulating region between the channel region and the drain region in the drift region.

Moreover, it is preferable that at least part of the second insulating region is arranged so as to overlap the gate electrode.

Further, in the drift region, an intermediate doped region of the second conductivity type is provided between the drain region and the dopant concentration of the second conductivity type in the intermediate doped region is higher than that of the drift region. It is preferably higher and lower than the dopant concentration of the drain region.

Further, the device further comprises a first insulating region for insulating the drift region, the drain region and the gate electrode from other peripheral elements, wherein the drift region is formed from the surface of the substrate to a position deeper than the first insulating region. It is preferred that

a guard ring region of the first conductivity type that extends from the inside to the surface of the substrate, overlaps with a portion of the gate electrode, and surrounds the drift region and the gate electrode; and a source region disposed in a surface region within the region, wherein the source region and the drain region are preferably disposed on both sides of the gate electrode.

Moreover, it is preferable that the source region is provided adjacent to the gate insulating layer.

Another aspect of the present invention is a method of manufacturing a semiconductor device, wherein a mask having at least two opening regions separated along a movement direction of a channel is provided on a surface of a substrate of a first conductivity type, and the opening an ion implantation step of ion implanting a dopant of a second conductivity type opposite to the first conductivity type into the region; and diffusing the dopant implanted in the ion implantation step into the substrate to be of the second conductivity type. an ion diffusion step to form a drift region;
a gate electrode forming step of forming a gate electrode overlapping at least a part of the drift region with a gate insulating layer interposed therebetween; and a drain region forming step of forming a drain region spaced apart from the gate electrode by a predetermined distance; After the dopant concentration of the second conductivity type increases from the end of the drift region in the channel region under the gate electrode toward the drain region, the rate of increase in dopant concentration decreases, and then the dopant concentration increases again. A method of manufacturing a semiconductor device characterized by exhibiting a profile with increasing rate of concentration increase.

Here, due to the overlap of the diffusion regions of the dopants implanted in the two opening regions, the dopant concentration of the second conductivity type in the channel region is reduced to the edge of the drift region in the channel region under the gate electrode. from the drain region to the first concentration, the rate of increase of the dopant concentration decreases to maintain the first concentration, and then the rate of increase of the dopant concentration increases again to the first concentration. A method of fabricating a semiconductor device characterized by exhibiting a stepped profile to a second concentration higher than the concentration of .

Further, of the two opening regions of the mask, the length of the opening region on the side of the gate electrode along the moving direction of the channel is 1.2 μm or less, and the length of the opening region between the two opening regions of the mask is 1.2 μm or less. Preferably, the length of the channel along the moving direction is 1.2 μm or less.

Moreover, it is preferable to include a second insulating region forming step of forming a second insulating region between the channel region and the drain region in the drift region.

In addition, it is preferable that the second insulating region forming step forms the second insulating region at a position at least partially overlapping with the gate electrode.

Further, an intermediate doped region forming an intermediate doped region between the drift region and the drain region, the dopant concentration of the second conductivity type being higher than the dopant concentration of the drift region and lower than the dopant concentration of the drain region. It is preferred to have a forming step.

The method further comprises a first insulating region forming step of forming a first insulating region for insulating the drift region, the drain region and the gate electrode from other peripheral elements, wherein the drift region extends from the surface of the substrate to the first insulating region. It is preferable to form to a position deeper than one insulating region.

Further, in the ion implantation step before the ion diffusion step, the guard ring region of the first conductivity type extending from the inner side to the surface of the substrate overlaps with a part of the gate electrode, and the drift region and the Preferably, the first conductivity type dopant is implanted into the substrate using a patterned mask to form a guard ring region surrounding the gate electrode.

Simultaneously with the step of forming the drain region, the source region of the second conductivity type is formed in the surface region within the guard ring, and the source region and the drain region are arranged on both sides of the gate electrode. It is preferred that

According to the present invention, the breakdown characteristics of field effect transistors can be improved.

It is a cross-sectional schematic diagram which shows the basic composition of the semiconductor device in embodiment of this invention. 1 is a schematic plan view showing the basic configuration of a semiconductor device according to an embodiment of the present invention; FIG. It is a figure which shows the suitable dimension in the basic composition of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacturing method of the basic composition of the semiconductor device in embodiment of this invention. It is a figure explaining the dopant concentration profile of the drift region of the basic structure of the semiconductor device in embodiment of this invention. It is a figure explaining the characteristic of the basic composition of the semiconductor device in an embodiment of the invention. It is a figure explaining the characteristic of the basic composition of the semiconductor device in an embodiment of the invention. It is a figure explaining the characteristic of the basic composition of the semiconductor device in an embodiment of the invention. It is a cross-sectional schematic diagram which shows the semiconductor device in embodiment of this invention. It is a figure explaining the dopant concentration profile of the drift region of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor device in embodiment of this invention. It is a figure which shows the resist layer for forming a drain region in embodiment of this invention. It is a figure which shows the resist layer for forming a drain region in embodiment of this invention. It is a figure explaining the characteristic of the semiconductor device in embodiment of this invention. It is a figure which shows the example which measured the characteristic of the semiconductor device in embodiment of this invention. 3 is a schematic cross-sectional view showing a semiconductor device in Modification 1; FIG. FIG. 10 is a diagram showing a resist layer for forming a drain region in Modification 1; FIG. 11 is a schematic cross-sectional view showing a semiconductor device in modification 2; FIG. 11 is a schematic cross-sectional view showing a semiconductor device in modification 2;

[Basic configuration]
FIG. 1 shows a schematic cross-sectional view of the basic configuration of a semiconductor device 100 including an asymmetric high voltage field effect transistor (HVMOS: High Voltage MOS). FIG. 2 shows a schematic plan view of the basic configuration of the semiconductor device 100. As shown in FIG. The HVMOS preferably has an operating voltage of, for example, 20 V or more and 60 V or less. The semiconductor device 100 is used, for example, as a display driver. FIG. 3 shows the dimensions of each part of the semiconductor device 100. As shown in FIG.

1 and 2 are schematic diagrams for explaining the basic configuration of the HVMOS of the semiconductor device 100, emphasizing each part constituting the semiconductor device 100, and showing the dimension and thickness of each part in the plane direction. Directional dimensions may not indicate actual ratios. Also, in FIG. 2, a part of the configuration of the semiconductor device 100 (mainly the insulator layer) is excluded for clarity of explanation.

In the following description, the preferred dimensions of each part are the length direction (X direction) along the movement direction of the channel and the film thickness direction (Z direction) in the cross-sectional schematic diagram of the basic configuration of the semiconductor device 100. Show dimensions. Note that the dimension along the width direction (Y direction) may be appropriately set according to the maximum capacitance required in the HVMOS.

Semiconductor device 100 includes semiconductor substrate 10 , drift region 12 , guard ring region 14 , source region 16 , drain region 18 , tap region 20 , insulating region 22 , insulating region 24 , gate insulating layer 26 and gate electrode 28 . be done.

Hereinafter, the HVMOS included in the semiconductor device 100 will be described as an n-channel HVMOS. In this case, in the following description, the first conductivity type is p-type, and the second conductivity type opposite to the first conductivity type is n-type. However, the HVMOS included in the semiconductor device 100 is not limited to the n-type channel HVMOS, and may be a p-type channel HVMOS. In this case, the first conductivity type is n-type, and the second conductivity type opposite to the first conductivity type is p-type.

A semiconductor substrate 10 is a substrate on which a semiconductor device 100 is formed. The semiconductor substrate 10 can be, for example, a silicon substrate. The semiconductor substrate 10 is of the first conductivity type.

The drift region 12 is a region where a depletion layer is formed and carriers are drifted during operation of the semiconductor device 100 . Drift region 12 is of a second conductivity type opposite to the first conductivity type. The dopant concentration of the drift region 12 is preferably 5×10 ¹⁶ /cm ³ or more and 5×10 ¹⁸ /cm ^{3 or} less. One end of the drift region 12 is near the center under the gate electrode 28 and the other end is preferably located at a distance of 2.5 μm or more and 4 μm or less from the edge of the gate electrode 28 .

Guard ring region 14 surrounds the device region, including drift region 12, gate insulating layer 26, and gate electrode 28 of semiconductor device 100, and is a well for isolating HVMOS from other devices. The guard ring region 14 is of the first conductivity type. The dopant concentration of the guard ring region 14 is preferably 5×10 ¹⁶ /cm ³ or more and 1×10 ¹⁸ /cm ^{3 or} less. The guard ring region 14 on the side where the source region 16 is provided extends to a region overlapping the gate insulating layer 26 and the gate electrode 28, and this region functions as a first conductivity type well of HVMOS.

Source region 16 is a region that serves as the source of semiconductor device 100 . The source region 16 is arranged in a region overlapping or adjacent to the gate insulating layer 26 and the gate electrode 28 within the guard ring region 14 . Source region 16 is of the same conductivity type as drift region 12, ie, the second conductivity type. The dopant concentration of the source region 16 is preferably 1×10 ¹⁹ /cm ³ or more and 1×10 ²¹ /cm ^{3 or} less. The length (X direction) of the source region 16 is preferably 0.6 μm or more and 0.9 μm or less.

The drain region 18 is a region that serves as the drain of the semiconductor device 100 . Drain region 18 is located within drift region 12 in a region spaced from gate insulating layer 26 and gate electrode 28 . Drain region 18 is of the same conductivity type as drift region 12, ie, the second conductivity type. The dopant concentration of the drain region 18 is preferably 1×10 ¹⁹ /cm ³ or more and 1×10 ²¹ /cm ^{3 or} less. The length (X direction) of the drain region 18 is preferably 0.3 μm or more and 0.5 μm or less.

The tap region 20 is a region for applying voltage to the guard ring region 14 . Tap region 20 is formed within guard ring region 14 and is arranged to surround the device region including drift region 12 , gate insulating layer 26 and gate electrode 28 . The tap region 20 has the same conductivity type as the guard ring region 14, that is, the first conductivity type. The dopant concentration of the tap region 20 is preferably 1×10 ¹⁹ /cm ³ or more and 1×10 ²¹ /cm ^{3 or} less. The length (X direction) of the tap region 20 is preferably 0.3 μm or more and 0.5 μm or less.

The insulating region 22 is an insulator region provided to relax the electric field between the drain region 18 and the gate electrode 28 . The isolation regions 22 may be, but are not limited to, shallow trench isolation regions (STI regions). If the semiconductor substrate 10 is silicon, the insulating region 22 can be a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), or the like. The insulating region 22 is arranged in the drift region 12 from a region overlapping the gate insulating layer 26 and the gate electrode 28 to a region close to the drain region 18 . The thickness of the insulating region 22 in the depth direction of the semiconductor substrate 10 is preferably 250 nm or more and 300 nm or less. Also, the length (X direction) of the insulating region 22 is preferably 2 μm or more and 3 μm or less. Moreover, it is preferable that the insulating region 22 is arranged so that the central position of the length (X direction) is positioned near the end of the gate electrode 28 .

The insulating region 24 is a region for insulating components of the semiconductor device 100 from each other. If the semiconductor substrate 10 is silicon, the insulating region 24 can be a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), or the like. The length (X direction) of the insulating region 24 provided between the source region 16 and the tap region 20 is preferably 0.4 μm or more and 0.8 μm or less. Also, the length (X direction) of 24 provided between the drain region 18 and the tap region 20 is preferably 1.8 μm or more and 3.2 μm.

The gate insulating layer 26 is an insulating layer forming the gate of the HVMOS. If the semiconductor substrate 10 is silicon, the gate insulating layer 26 can be a silicon oxide layer ( _SiO2 ), a silicon nitride layer (SiN), or a silicon oxynitride (SiOxNy). The gate insulating layer 26 is provided on a region extending over the well region of the guard ring region 14 , part of the drift region 12 and the insulating region 22 . The film thickness of the gate insulating layer 26 is preferably 70 nm or more and 90 nm or less.

The gate electrode 28 is an electrode for applying a gate voltage to the gate insulating layer 26 . The gate electrode 28 can be made of a polysilicon layer, a metal layer, a silicide, or a laminate structure thereof. A gate electrode 28 is provided in a region on the gate insulating layer 26 . When the gate electrode 28 is a polycrystalline silicon layer, the film thickness of the gate electrode 28 is preferably 100 nm or more and 200 nm or less. Also, the length of the gate region of the gate electrode 28 is set to 2 μm or more and 3 μm or less. Moreover, it is preferable that the end portion of the gate electrode 28 extends to the vicinity of the center of the insulating region 22 . Note that, of the region where the gate electrode 28 is provided with the gate insulating layer 26 interposed in the semiconductor substrate 10, the region from the source region 16 to the edge of the drift region 12 is the channel region.

[Manufacturing method of basic configuration]
FIG. 4 shows a method of manufacturing the semiconductor device 100 . 4A and 4B are schematic diagrams showing a method of manufacturing the HVMOS of the semiconductor device 100. Each part constituting the semiconductor device 100 is emphasized. may not be shown.

A method of manufacturing a semiconductor device 100 including an n-channel HVMOS will be described below. The semiconductor substrate 10 will be described as a silicon substrate doped with p-type as the first conductivity type. When the semiconductor device 100 includes a p-type channel HVMOS, the first conductivity type can be read as n-type, and the second conductivity type can be read as p-type.

In step S10, implantation regions 12a are formed by ion implantation of dopants into the drift region 12. As shown in FIG. A resist layer R functioning as a mask is formed on the surface of the semiconductor substrate 10, the region corresponding to the drift region 12 being an opening region. The resist layer R can be patterned using a photolithographic technique. When the second conductivity type is the n-type, an n-type dopant (phosphorus P or arsenic As) is ion-implanted into the surface of the semiconductor substrate 10 using the resist layer R as a mask. Here, it is preferable to perform two-step implantation in which ion implantation into a shallow region and ion implantation into a deeper region using a higher implantation energy than the ion implantation into the shallow region are combined. For example, in ion implantation into a shallow region, phosphorus P (or arsenic As) is ion-implanted at an ion implantation energy of 200 keV to 300 keV to a density of 1×10 ¹² to 2×10 ¹² /cm ² . Further, in ion implantation into a deeper region, ions are implanted at a density of 4×10 ¹² to 6×10 ¹² /cm ² at an ion implantation energy of 600 keV to 700 keV. However, the density of the dopant to be ion-implanted, the implantation depth, etc. may be appropriately set according to the size and characteristics of the HVMOS. After the ion implantation, the resist layer R is removed.

In step S12, a dopant ion implantation process into the guard ring region 14 is performed. A resist layer R is formed so that a region corresponding to the guard ring region 14 in the semiconductor substrate 10 becomes an opening region. The resist layer R can be patterned using a photolithographic technique. When the first conductivity type is p-type, ions of a p-type dopant (boron B or boron difluoride BF ₂ ) are implanted into the surface of the semiconductor substrate 10 using the resist layer R as a mask. Here, it is preferable to perform two-step implantation in which ion implantation into a shallow region and ion implantation into a deeper region using a higher implantation energy than the ion implantation into the shallow region are combined. For example, in ion implantation into a shallow region, boron B (or boron difluoride BF ₂ ) is ion-implanted at an ion implantation energy of 100 keV or more and 150 keV or less so as to have a density of 1×10 ¹² or more and 2×10 ¹² /cm ² . inject. Further, in ion implantation into a deeper region, ions are implanted at a density of 1×10 ¹³ to 2×10 ¹³ /cm ² at an ion implantation energy of 300 keV to 400 keV. However, the density of the dopant to be ion-implanted, the implantation depth, etc. may be appropriately set according to the size and characteristics of the HVMOS. After the ion implantation, the resist layer R is removed.

In step S14, ion diffusion processing is performed. After implanting the dopant into the drift region 12 and the guard ring region 14, the semiconductor substrate 10 is annealed (heated) at a high temperature of about 900.degree. C. to 1300.degree. For example, annealing is performed at 1100° C. for 5 to 7 hours. However, the heating temperature and time may be appropriately set according to the size and characteristics of the HVMOS. The region into which the dopant of the second conductivity type is diffused becomes the drift region 12 , and the region into which the dopant of the first conductivity type is diffused becomes the guard ring region 14 .

FIG. 5 shows the diffusion state of the second conductivity type dopant in the drift region 12 and its peripheral region. In step S10, the dopant of the second conductivity type is uniformly implanted over the regions X2-X5. After that, the dopant is diffused by annealing in step S14 and spreads over the range of regions X1 to X6. Due to the diffusion of the dopant, the dopant concentration in the drift region 12 and its peripheral region has a profile that smoothly changes in the boundary regions X1 to X3 and the boundary regions X4 to X6.

In step S16, insulating regions 22 and 24 are formed. Isolation region 22 and isolation region 24 can be formed by existing LOCOS or STI processes using masks. In the LOCOS process, a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) is used as a mask and the semiconductor substrate 10 is heated while oxygen (O ₂ ) is supplied to form an opening region of the mask on the surface of the semiconductor substrate 10 . Insulating region 22 or insulating region 24 can be formed by thermal oxidation. In addition, in the STI process, an opening region is trench-etched, an insulating film is embedded in the trench using high-density plasma CVD or the like, and then the region is planarized by chemical mechanical polishing (CMP) to form an insulating region. 22 or insulating regions 24 may be formed.

In step S18, a gate insulating layer 26 and a gate electrode 28 are formed. The method of forming the gate insulating layer 26 is not particularly limited, but a thermal oxidation method using an oxygen-containing gas such as oxygen (O ₂ ) or a nitrogen-containing gas such as nitrogen (N ₂ ) may be applied. can be done. A gate electrode 28 is formed on the gate insulating layer 26 . The method of forming the gate electrode 28 is not particularly limited, but when forming a polycrystalline silicon layer, chemical vapor deposition (CVD) using a silicon-containing gas such as silane (SiH ₄ ) is adopted. be able to. When the gate electrode 28 is a metal layer, a vapor deposition method, a sputtering method, a chemical vapor deposition method (CVD method), or the like can be applied. When the gate electrode 28 is made of silicide, a method of depositing a metal such as Ti, Ta, Co, or Ni on polycrystalline silicon and heat-treating it, or a method of depositing a high-melting-point metal and silicon simultaneously by sputtering. can be applied. The gate insulating layer 26 other than the region under the gate electrode 28 is removed by etching the region other than the region of the gate electrode 28 before forming the gate electrode 28 using a mask formed by photolithography. At this time, the remaining area of the gate insulating layer 26 may be wider than the area of the gate electrode 28 by an overlap margin of about 0.1 μm to 0.15 μm.

In step S20, source region 16, drain region 18 and tap region 20 are formed. The source region 16 and the drain region 18 are subjected to an ion implantation process with dopants of the second conductivity type. A resist layer R is formed on the surface of the semiconductor substrate 10 such that regions corresponding to the source region 16 and the drain region 18 are opening regions. The resist layer R can be patterned using a photolithographic technique. When the second conductivity type is the n-type, an n-type dopant (phosphorus P or arsenic As) is ion-implanted into the surface of the semiconductor substrate 10 using the resist layer R as a mask. For example, arsenic As is ion-implanted at an ion implantation energy of 20 keV to 50 keV to a density of 2×10 ¹⁵ to 5×10 ¹⁵ /cm ² . Further, for example, phosphorus P is ion-implanted at an ion implantation energy of 30 keV to 40 keV to a density of 5×10 ¹³ to 1×10 ¹⁴ /cm ² . After the ion implantation, the resist layer R is removed. Next, the tap region 20 is ion-implanted with a dopant of the first conductivity type. A resist layer R is formed so that a region corresponding to the tap region 20 on the surface of the semiconductor substrate 10 becomes an opening region. The resist layer R can be patterned using a photolithographic technique. When the first conductivity type is p-type, ions of a p-type dopant (boron B or boron difluoride BF ₂ ) are implanted into the surface of the semiconductor substrate 10 using the resist layer R as a mask. For example, boron difluoride BF ₂ is ion-implanted at an ion implantation energy of 10 keV to 20 keV to a density of 1.5×10 ¹⁵ to 3×10 ¹⁵ /cm ² . Further, for example, boron B is ion-implanted at an ion implantation energy of 10 keV to 20 keV to a density of 2×10 ¹³ to 5×10 ¹³ /cm ² . After the ion implantation, the resist layer R is removed. Thereafter, the semiconductor substrate 10 is annealed (heated) at a high temperature of about 900.degree. C. to 1100.degree. For example, annealing is performed at 1000° C. for 20 to 30 seconds.

Through the above processes, the basic configuration of the HVMOS on the semiconductor substrate 10 can be formed.

[Characteristics of basic configuration]
FIG. 6 shows voltages applied to source region 16, drain region 18, tap region 20 (P-well region) and gate electrode 28 to measure the breakdown voltage for HVMOS on semiconductor substrate 10. FIG. A voltage of 0 V was applied to the source region 16, the tap region 20 and the gate electrode 28, and a voltage was applied to the drain region 18 so as to gradually increase from 0 to a positive voltage.

As the positive voltage applied to the drain region 18 increased, the electric field concentrated in the region A closer to the gate electrode 28 than the insulating region 22 in the drift region 12 under the gate electrode 28, causing breakdown. In this case, the high dopant concentration in the drift region 12 exacerbates the electric field concentration. That is, in order to achieve a high breakdown voltage, the dopant concentration of the drift region 12 should be lowered.

On the other hand, in the HVMOS of the semiconductor substrate 10, it is also necessary to consider characteristics in an operating state in which a high voltage is applied to both the gate electrode 28 and the drain region 18 at the same time.

Therefore, as shown in FIG. 7, the gate electrode 28 and the drain region 18 are electrically connected, and a voltage is applied to both the gate electrode 28 and the drain region 18 so as to gradually increase the positive voltage from 0. is applied.

In this case, the electric field was concentrated under the drain region 18 in the drift region 12, that is, in the region B on the side of the drain region 18 from the insulating region 22 in the drift region 12, and breakdown occurred. In this case, the low dopant concentration in the drift region 12 exacerbates the electric field concentration. That is, in order to achieve a high breakdown voltage, the dopant concentration of the drift region 12 should be increased. If a well region having a lower dopant concentration than the drain region 18 and a higher dopant concentration than the drift region 12 is provided under the drain region 18, the region B is under the well region. Although the breakdown voltage is increased by providing the well region, the low dopant concentration of the drift region 12 still deteriorates the electric field concentration in the region B. FIG.

Thus, it is difficult to maintain a high HVMOS breakdown voltage in both operating conditions. In order to improve the breakdown voltage, the channel lengths L1 and L2 shown in FIG. 8 may be lengthened _. Another problem arises that

[Configuration in the first embodiment]
FIG. 9 shows a schematic cross-sectional view of a semiconductor device 200 including an asymmetric high voltage field effect transistor (HVMOS: High Voltage MOS) in the first embodiment. A plan view of the semiconductor device 200 is similar to the basic configuration of the semiconductor device 100 shown in FIG. The HVMOS preferably has an operating voltage of, for example, 20 V or more and 60 V or less. The semiconductor device 200 is used, for example, as a display driver.

FIG. 9 is a schematic diagram for explaining the configuration of the HVMOS of the semiconductor device 200, and shows each part constituting the semiconductor device 200 with emphasis. It may not show the actual ratio.

A semiconductor device 200 according to the present embodiment includes a semiconductor substrate 10, a drift region 30, a guard ring region 14, a source region 16, a drain region 18, a tap region 20, an insulating region 22, an insulating region 24, a gate insulating layer 26 and a gate electrode. 28. Semiconductor device 200 has the same configuration as semiconductor device 100 except that drift region 30 is provided instead of drift region 12 . Therefore, in the following description, the drift region 30 will be mainly described, and descriptions of other components will be omitted.

The HVMOS included in the semiconductor device 200 will be described as an n-channel HVMOS. In this case, in the following description, the first conductivity type is p-type, and the second conductivity type opposite to the first conductivity type is n-type. However, the HVMOS included in the semiconductor device 200 is not limited to the n-type channel HVMOS, and may be a p-type channel HVMOS. In this case, the first conductivity type is n-type, and the second conductivity type opposite to the first conductivity type is p-type.

The drift region 30 is a region where a depletion layer is formed and carriers are drifted during operation of the semiconductor device 200 . Drift region 30 is of a second conductivity type opposite to the first conductivity type. The dopant concentration of the drift region 30 is preferably 5×10 ¹⁶ /cm ³ or more and 5×10 ¹⁸ /cm ^{3 or} less. One end of the drift region 30 is near the center under the gate electrode 28 and the other end is preferably located at a distance of 2.5 μm or more and 4 μm or less from the edge of the gate electrode 28 .

FIG. 10 shows the dopant concentration profile of the drift region 30 and surrounding regions of the semiconductor device 200 . The drift region 30 of the semiconductor device 200 according to the present embodiment has a different dopant concentration profile than the drift region 12 of the semiconductor device 100 having the basic configuration described above. In the drift region 12 of the semiconductor device 100 of the basic configuration, the dopant concentration monotonically increases from the edge of the drift region 12 below the gate electrode 28 . On the other hand, in the drift region 30 of the semiconductor device 200, the dopant concentration increases from the end portion of the drift region 30 under the gate electrode 28, and after the rate of increase decreases, the rate of increase increases again. Profile.

That is, as shown in FIG. 10, the dopant concentration is gradually increased from the position X1 at the edge of the drift region 30 under the gate electrode 28 toward the insulating region 22 to the position X2 near the insulating region 22 at the first concentration. Increases up to N1. Subsequently, the rate of dopant increase is reduced such that the dopant concentration is maintained at approximately the first concentration N1 from location X2 near the insulating region 22 to location X7 near the edge of the insulating region 22. FIG. After that, the dopant increase rate increases again, and the dopant concentration gradually increases from the position X7 to the position X9 under the insulating region 22 via the position X8 to the second concentration N2. The second concentration N2 of dopant is higher than the first concentration N1. The dopant concentration maintains the second concentration N2 from the position X9 through the position X10 under the drain region 18 to the position X4 beyond the drain region 18, and the drift region 30 and the guard ring region 14 from the position X4. The dopant concentration gradually decreases toward the position X6 beyond the boundary region. In the vicinity of the boundary between the drift region 30 and the guard ring region 14, the first conductivity type dopant ion-implanted into the guard ring region 14 side and the second conductivity type dopant ion-implanted into the drift region 30 side are mixed. The boundary between the guard ring region 14 of the first conductivity type and the drift region 30 of the second conductivity type is determined as a whole.

In this embodiment, the dopant concentration under and in the vicinity of the gate electrode 28 has a profile in which the dopant concentration clearly changes stepwise from the concentration N1 to the concentration N2. Any profile may be used as long as the rate of increase decreases once and then increases. That is, it is preferable to have an inflection point in the dopant concentration change in the region where the dopant concentration changes from the concentration N1 to the concentration N2 under and near the gate electrode 28 . Also, the dopant concentration in the region from the position X2 to the position X7 may be constant at the first concentration N1, or may slightly increase or decrease.

[Manufacturing method in the first embodiment]
FIG. 11 shows a method of manufacturing a semiconductor device 200. As shown in FIG. 11A and 11B are schematic diagrams showing the method of manufacturing the HVMOS of the semiconductor device 200. Each part constituting the semiconductor device 200 is shown with emphasis. may not be shown.

A method of manufacturing a semiconductor device 200 including an n-channel HVMOS will be described below. The semiconductor substrate 10 will be described as a silicon substrate doped with p-type as the first conductivity type. When the semiconductor device 200 includes a p-type channel HVMOS, the first conductivity type can be read as n-type, and the second conductivity type can be read as p-type.

In the manufacturing method of the semiconductor device 200, the only difference from the semiconductor device 100 of the basic configuration is the step of forming the drift region 30. FIG. Therefore, in the following description, the step of forming the drift region 30 will be mainly described, and the description of the steps of forming other components will be omitted.

In step S30, implantation regions 30a are formed by ion implantation of dopants into the drift region 30. As shown in FIG. A resist layer R is formed on the surface of the semiconductor substrate 10 so that the region corresponding to the drift region 30 has two opening regions. That is, the resist layer R is formed so as to have at least two opening regions separated along the X direction, which is the direction of movement of the channel. The resist layer R can be patterned using a photolithographic technique.

FIG. 12 shows the relationship between the opening region of the resist layer R, the region of the implantation region 30a into which the dopant is ion-implanted, and the dopant concentration profile of the drift region 30 finally formed. The injection region 30a is the region from the position X2 to the position X7 and the region from the position X8 to the position X5 in the above description. The area from position X2 to position X7 is assumed to be narrower than the area from position X8 to position X5. Here, the length (X direction) of the resist layer R provided from the position X7 to the position X8 is preferably 1.2 μm or less, for example. Also, the length (X direction) of the region from the position X2 to the position X7, which is the opening region, is preferably 1.2 μm or less, for example.

13(a) and 13(b) show examples of planar layouts of the resist layer R. FIG. As shown in FIG. 13(a), the resist layer R is formed so that the region from the position X2 to the position X7, which is the opening region, is completely separated from the region from the position X8 to the position X5, which is another opening region. may Further, as shown in FIG. 13B, the resist layer R from the position X7 to the position X8 is formed in an island shape, and the region from the position X2 to the position X7 and the region from the position X8 to the position X5 are connected to each other. A resist layer R may be formed. At this time, the width Wr (Y direction) of the island-shaped resist layer R can be 80% or more of the width of the channel region or 70% or more of the width W (Y direction) of the opening region of the resist layer R. preferred.

The island-shaped resist layer R may be divided into two or more along the width direction. In this case, the total value of the width Wr (Y direction) of the divided island-shaped resist layers R is 80% or more of the width of the channel region, or 70% of the width W (Y direction) of the opening region of the resist layer R. It is preferable to set it as above.

When the second conductivity type is the n-type, an n-type dopant (phosphorus P or arsenic As) is ion-implanted into the surface of the semiconductor substrate 10 using the resist layer R as a mask to form an implantation region 30a. Here, it is preferable to perform two-step implantation in which ion implantation into a shallow region and ion implantation into a deeper region using a higher implantation energy than the ion implantation into the shallow region are combined. For example, in ion implantation into a shallow region, phosphorus P (or arsenic As) is ion-implanted at an ion implantation energy of 200 keV to 300 keV to a density of 1×10 ¹² to 2×10 ¹² /cm ² . Further, in ion implantation into a deeper region, ions are implanted at a density of 4×10 ¹² to 6×10 ¹² /cm ² at an ion implantation energy of 600 keV to 700 keV. However, the density of the dopant to be ion-implanted, the implantation depth, etc. may be appropriately set according to the size and characteristics of the HVMOS. After the ion implantation, the resist layer R is removed.

Thereafter, steps S12 to S20 may be processed in the same manner as in the semiconductor device 100 described above.

The dopant implanted into the drift region 30 in step S30 is diffused into the semiconductor substrate 10 by the ion diffusion process of step S14, and the dopant concentration profile in the drift region 30 of the semiconductor device 200 described in FIG. 10 is realized.

[Characteristics in the first embodiment]
Characteristics of the semiconductor device 200 according to the present embodiment will be described below with reference to FIG. In FIG. 14, the dopant concentration profile in the drift region 30 of the semiconductor device 200 is indicated by a thick solid line, and the dopant concentration profile in the drift region 12 of the semiconductor device 100 is indicated by a thick dashed line for comparison.

In the semiconductor device 200, the dopant concentration of the region A in the drift region 30 under the gate electrode 28 closer to the gate electrode 28 than the insulating region 22 is lower than the dopant concentration in the region A of the semiconductor device 100 of the basic configuration. Therefore, in the semiconductor device 200, when 0 V is applied to the source region 16, the tap region 20, and the gate electrode 28, and a voltage is applied to the drain region 18 so as to gradually increase the positive voltage from 0, the region The concentration of the electric field on A is lessened than in the semiconductor device 100 of the basic configuration. Then, in region A, the semiconductor device 200 according to the present embodiment has a higher breakdown voltage than the semiconductor device 100 having the basic configuration.

On the other hand, in the semiconductor device 200, the dopant concentration of the region B below the drain region 18 in the drift region 30, that is, the region B on the side of the drain region 18 from the insulating region 22 in the drift region 30 is the same as that in the region B of the semiconductor device 100 of the basic configuration. Equal to the dopant concentration. Therefore, when the gate electrode 28 and the drain region 18 are electrically connected and a voltage is applied to both the gate electrode 28 and the drain region 18 so as to gradually increase the positive voltage from 0, the basic configuration In the semiconductor device 200 of the present embodiment, the concentration of the electric field in the region B does not change, in contrast to the semiconductor device 100 of FIG. Then, in region B, the breakdown voltage of the semiconductor device 200 according to the present embodiment does not change from that of the semiconductor device 100 having the basic configuration.

That is, the breakdown voltage in region A can be improved while the breakdown voltage in region B is maintained. Further, it is not necessary to extend the channel length from the source 16 region to the drift region 30 or the length of the drift region 30 in order to improve the breakdown voltage, so that the drain-source current I _DS can be prevented from decreasing.

FIG. 15 shows the results of measuring the breakdown voltages of the semiconductor device 100 of the basic configuration and the semiconductor device 200 of the present embodiment. Specifically, the distance A from the end position X2 of the injection region 30a to the end of the insulating region 22 on the gate electrode 28 side is set to 0.4 μm, and the length X of the insulating region 22 is set to 2.4 μm to 3.4 μm. shows the results when the semiconductor device 200 of the present embodiment is formed. FIG. 15(a) shows the measurement results of the semiconductor device 100 having the basic configuration. FIG. 15(b) shows the measurement results of the semiconductor device 200 of this embodiment. In FIG. 15B, in the ion implantation process of step S30 of the manufacturing process of the semiconductor device 200, the length of the resist layer R provided from the position X7 to the position X8 is set to 0.8 μm, and the position X2 which becomes the opening region is set to 0.8 μm. The measurement results are shown when the length of the region from to position X7 is set to 0.8 μm.

As shown in FIG. 15A, in the semiconductor device 100 having the basic configuration, breakdown occurred at a gate voltage of about 1.6 V (marked by a circle in the figure). In contrast, as shown in FIG. 15(b), breakdown did not occur until the gate voltage reached 4V in the semiconductor device 200 of the present embodiment.

When the gate voltage was set to 0V and the drain voltage was increased, breakdown occurred at about 58V. On the other hand, when the semiconductor device 100 having the basic configuration was formed with the same dimensions, when the gate voltage was set to 0V and the drain voltage was increased, breakdown occurred at about 51V.

[Modification 1]
FIG. 16 is a schematic cross-sectional view showing the configuration of a semiconductor device 202 in Modification 1. As shown in FIG. In the semiconductor device 202 , two HVMOS are arranged line-symmetrically with respect to the drain region 18 . That is, in the semiconductor device 202, one drain region 18 is shared by two HVMOSs.

In this case, in the dopant ion implantation process into the drift region 30 in step S30, as shown in FIG. An area should be provided. FIG. 17 also shows the dopant concentration profile in the drift region 30 finally formed by the ion implantation and ion diffusion processes.

Even in the configuration in which the drain region 18 is provided in common for the two HVMOSs as in this modification, the breakdown voltage under the gate electrode 28 can be improved without lowering the breakdown voltage near the drain region 18. can.

[Modification 2]
FIG. 18 is a schematic cross-sectional view showing the configuration of a semiconductor device 204 in Modification 2. As shown in FIG. FIG. 18 also shows the dopant concentration profile in the drift region 30 .

The semiconductor device 204 differs from the semiconductor device 200 of the above embodiment in that the insulating region 22 is not provided. Semiconductor device 204 can be realized by not forming insulating region 22 in step S16.

In the semiconductor device 204, the length L3 (X direction) of the region of the drift region 30 that overlaps the gate electrode 28 is preferably 0.3 μm or more and 0.6 μm or less, for example. Also, the distance L4 (X direction) from the end of the gate electrode 28 to the drain region 18 is preferably 2 μm or more and 3 μm or less.

According to the semiconductor device 204, similarly to the semiconductor device 200 of the above embodiment, the dopant concentration in the drift region 30 under and near the gate electrode 28 is made lower than the dopant concentration in other regions, thereby reducing the dopant concentration. Breakdown characteristics can be improved compared to flattening the profile.

[Modification 3]
FIG. 19 is a schematic cross-sectional view showing the configuration of a semiconductor device 206 according to Modification 3. As shown in FIG. FIG. 19 also shows the dopant concentration profile in the drift region 30 .

In semiconductor device 206 , intermediate doped region 32 is provided between drift region 30 and drain region 18 . The dopant concentration in intermediate doped region 32 is higher than the dopant concentration in drift region 30 and lower than the dopant concentration in drain region 18 .

The intermediate doped region 32 is formed by forming a resist layer R with the intermediate doped region 32 as an opening region between steps S16 and S18, and then forming the intermediate doped region 32 so as to have a dopant concentration higher than that of the drift region 30 and lower than that of the drain region 18. can be formed by ion-implanting a dopant of the second conductivity type into the .

In this modification, the length L3 (X direction) of the region of the drift region 30 that overlaps the gate electrode 28 is preferably 0.3 μm or more and 0.6 μm or less, for example. Also, the distance L4 (X direction) from the end of the gate electrode 28 to the drain region 18 is preferably 2 μm or more and 3 μm or less. Further, the width L5 (X direction) of the intermediate doped region 32 surrounding the drift region 30 is preferably 0.1 μm or more and 0.2 μm.

According to the semiconductor device 206, the electric field concentration in the vicinity of the drain region 18 can be more relaxed by placing the intermediate doped region 32 between the drift region 30 and the drain region 18. FIG. Therefore, the breakdown voltage in the vicinity of the drain region 18 can be further improved.

10 semiconductor substrate 12 drift region 14 guard ring region 16 source region 18 drain region 20 tap region 22 insulating region 24 insulating region 26 gate insulating layer 28 gate electrode 30 drift region 32 intermediate doped region , 100, 200, 202, 204, 206 semiconductor devices.

Claims (16)

A semiconductor device,
a substrate of first conductivity type;
a drift region of a second conductivity type opposite the first conductivity type within the substrate;
a drain region of the second conductivity type in the drift region and having a higher dopant concentration than a peripheral portion of the drift region;
a gate electrode overlapping at least part of the drift region with a gate insulating layer interposed therebetween;
a field effect transistor having
the drain region is spaced apart from the gate electrode by a predetermined distance,
The dopant concentration of the second conductivity type in the channel region including at least a part of the region overlapping the gate electrode in the drift region increases from the end of the drift region in the channel region under the gate electrode to the drain region. After increasing the dopant concentration toward
The dopant concentration of the second conductivity type in the channel region increases from the edge of the drift region in the channel region under the gate electrode toward the drain region to a first concentration, and then the dopant concentration decreases. The rate of increase decreases to maintain the first concentration, then the rate of increase in dopant concentration increases again to a second concentration higher than the first concentration, to maintain the second concentration, and then the dopant A semiconductor device exhibiting a stepped profile of decreasing concentration. A semiconductor device according to claim 1, wherein
A semiconductor device having an operating voltage of 20 V or more and 60 V or less. 3. A semiconductor device according to claim 1 or 2,
A semiconductor device comprising a second insulating region within said drift region between said channel region and said drain region. A semiconductor device according to claim 3, wherein
A semiconductor device according to claim 1, wherein at least a portion of said second insulating region is arranged to overlap said gate electrode. A semiconductor device according to any one of claims 1 to 4,
In the drift region, having an intermediate doped region of the second conductivity type between the drain region and
A semiconductor device, wherein a dopant concentration of said second conductivity type in said intermediate doped region is higher than a dopant concentration in said drift region and lower than a dopant concentration in said drain region. A semiconductor device according to any one of claims 1 to 5,
further comprising a first insulating region for insulating the drift region, the drain region and the gate electrode from other peripheral elements;
The semiconductor device according to claim 1, wherein the drift region is formed from the surface of the substrate to a position deeper than the first insulating region. A semiconductor device according to any one of claims 1 to 6,
a guard ring region of the first conductivity type extending from the inside to the surface of the substrate, the guard ring region overlapping a part of the gate electrode and surrounding the drift region and the gate electrode;
a source region located in a surface region within the guard ring region;
further comprising
1. A semiconductor device according to claim 1, wherein said source region and said drain region are arranged on both sides of said gate electrode. A semiconductor device according to claim 7, wherein
The semiconductor device of claim 1, wherein the source region is adjacent to the gate insulating layer. A method of manufacturing a semiconductor device, comprising:
A mask having at least two opening regions separated along the direction of movement of the channel is provided on a surface of a substrate of a first conductivity type, and a dopant of a second conductivity type opposite to the first conductivity type is provided in the opening regions. an ion implantation step of ion implanting
an ion diffusion step of diffusing the dopant implanted in the ion implantation step into the substrate to form a drift region of the second conductivity type;
a gate electrode forming step of forming a gate electrode overlapping at least part of the drift region with a gate insulating layer interposed therebetween;
a drain region forming step of forming a drain region which is of the second conductivity type in the drift region, has a higher dopant concentration than a peripheral portion of the drift region, and is spaced apart from the gate electrode by a predetermined distance;
with
The dopant concentration of the second conductivity type in a channel region including at least part of a region of the drift region overlapping with the gate electrode is increased from the end of the drift region in the channel region below the gate electrode to the drain region. After increasing the dopant concentration toward
Due to the overlap of the diffusion regions of the dopant implanted in the two opening regions, the dopant concentration of the second conductivity type in the channel region is increased from the edge of the drift region in the channel region under the gate electrode to the Towards the drain region, after increasing to a first concentration, the rate of increase of the dopant concentration decreases to maintain said first concentration, and then the rate of increase of the dopant concentration increases again to above said first concentration. A method of fabricating a semiconductor device comprising: exhibiting a stepped profile with a second high concentration, maintaining said second concentration, and then decreasing dopant concentration. A method for manufacturing a semiconductor device according to claim 9,
Of the two opening regions of the mask, the opening region on the side of the gate electrode has a length of 1.2 μm or less along the moving direction of the channel,
A method of manufacturing a semiconductor device, wherein the length along the moving direction of the channel of the mask between the two opening regions is 1.2 μm or less. A method for manufacturing a semiconductor device according to claim 9 or 10,
A method of manufacturing a semiconductor device, comprising: forming a second insulating region between the channel region and the drain region in the drift region. A method for manufacturing a semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the second insulating region forming step forms the second insulating region at a position at least partially overlapping with the gate electrode. A method for manufacturing a semiconductor device according to any one of claims 9 to 12,
forming an intermediate doped region between the drift region and the drain region, the intermediate doped region having a dopant concentration of the second conductivity type higher than the dopant concentration of the drift region and lower than the dopant concentration of the drain region; A method of manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device according to any one of claims 9 to 13,
further comprising a first insulating region forming step of forming a first insulating region for insulating the drift region, the drain region and the gate electrode from other peripheral elements;
A method of manufacturing a semiconductor device, wherein the drift region is formed from the surface of the substrate to a position deeper than the first insulating region. A method for manufacturing a semiconductor device according to any one of claims 9 to 14,
In the ion implantation step prior to the ion diffusion step, the guard ring region of the first conductivity type extending from the inside to the surface of the substrate overlaps with a portion of the gate electrode to form a gap between the drift region and the gate electrode. and implanting a dopant of said first conductivity type into said substrate using a patterned mask to form a guard ring region surrounding said substrate. A method for manufacturing a semiconductor device according to claim 15,
Simultaneously with the step of forming the drain region, forming the source region of the second conductivity type in the surface region within the guard ring;
A method of manufacturing a semiconductor device, wherein the source region and the drain region are arranged on both sides of the gate electrode.

Images