JP2009290140A - Power semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve drain breakdown voltage of a semiconductor device by relaxing concentration of electric fields in the vicinity of the boundary between a drain area and a drift area. <P>SOLUTION: A power semiconductor device 10 includes: a body area 70 including a channel area; a gate electrode 60 formed on the channel area via a gate insulating film 50; an N-type source area 130 formed in an area surrounded by the body area; and a drain area 140 formed so as to separated from the gate electrode 60. The surrounding of the drain area 140 is surrounded by a diffusion area 100 having lower impurity concentration than that of the drain area. Moreover, a drift area 80 having lower impurity concentration than that of the diffusion area 100 is formed between the diffusion area 100 and the lower area of the gate electrode 60. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power semiconductor device and a method for manufacturing the power semiconductor device.

  As a power semiconductor device, a DMOS (Double-Diffused Metal Oxide Semiconductor) type transistor having a high breakdown voltage and a large current capability is known. A DMOS transistor is a MOS field effect transistor having a structure that relaxes the electric field strength between a drain and a gate, and is widely used in a power supply circuit, a driver circuit, and the like.

As the DMOS transistor, there is an LD (Laterally Diffused) MOS transistor that conducts current in the lateral direction, and the structure of the LDMOS transistor has the following structure (see Patent Document 1). That is, for example, an N type epitaxial layer is provided, and a P type body region (P type well) is formed on the surface of the epitaxial layer. An N-type source region is formed so as to overlap with the body region. Further, a drain region in which a high concentration N-type impurity is diffused is formed on the surface of the epitaxial layer so as to face the source layer. The drain region is separated from the gate electrode, and a drift region in which a low-concentration N-type impurity is diffused is formed in a separated portion between the drain region and the gate electrode. A part of the body layer sandwiched between the source region and the drift region forms a channel region.
JP 2005-191052 A

  In a conventional power semiconductor device, a drain region having a high impurity concentration is in contact with a drift region having a low impurity concentration. For this reason, the electric field is concentrated in the vicinity of the boundary surface between the drain region and the drift region, and impact ionization occurs, resulting in a problem that the drain breakdown voltage is deteriorated.

  The present invention has been made in view of these problems, and an object thereof is to improve the drain withstand voltage of the power semiconductor device by relaxing the electric field concentration in the vicinity of the boundary between the drain region and the drift region.

  One embodiment of the present invention is a power semiconductor device. The power semiconductor device includes a second conductivity type body region including a channel region formed in a first conductivity type semiconductor layer, a gate electrode formed on the channel region via a gate insulating film, and a channel region. A first conductivity type source region formed in the body region on one side, and a first conductivity type formed in the first conductivity type semiconductor layer spaced apart from the gate electrode on the other side of the channel region. Between the first impurity region having a lower impurity concentration than the drain region formed between the channel region and the drain region, and between the first impurity region and the drain region. And a second impurity region of a first conductivity type having an impurity concentration higher than that of the first impurity region and lower than that of the drain region.

  According to this aspect, the second impurity region having an N-type impurity concentration higher than the first impurity region and lower than the drain region is formed between the drain region and the first impurity region. Therefore, the electric field concentration between the drain region and the first impurity region is alleviated, so that the pressure resistance of the power semiconductor device can be improved.

  In the above aspect, the second impurity region may surround the drain region.

  Another aspect of the present invention is a method for manufacturing a power semiconductor device. The method for manufacturing the power semiconductor device includes a step of forming a gate insulating film on a first conductivity type semiconductor layer, a step of forming a gate electrode on the gate insulating film, and a channel region in a semiconductor layer on the source side. Forming a second conductivity type body region including the first conductivity type first impurity region in the drain side semiconductor layer, and forming a first conductivity type body region adjacent to the channel region on the source side. A step of forming a low-concentration impurity region of one conductivity type, and a second first conductivity type of which the impurity concentration is higher than that of the first impurity region so that the first impurity region is interposed in the channel region on the drain side. Forming a first conductivity type source region in the body region so that the low concentration impurity region is interposed in the channel region on the source side, and the drain side And forming a drain region having an impurity concentration higher than that of the second impurity region so that the first impurity region and the second impurity region are sequentially interposed with respect to the channel region. To do.

  According to this aspect, it is possible to manufacture a power semiconductor device in which electric field concentration between the drain region and the first impurity region is relaxed and the withstand voltage is improved.

  In the method for manufacturing the power semiconductor device of the above aspect, the step of forming the low concentration impurity region on the source side and the step of forming the second impurity region on the drain side may be performed in the same step.

  According to the present invention, since the electric field concentration between the drain region and the drift region is relaxed, the drain breakdown voltage of the power semiconductor device can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(Embodiment)
FIG. 1 is a sectional view showing a structure of a power semiconductor device according to an embodiment. The power semiconductor device 10 includes a P-type single crystal silicon substrate 20 and an N− type epitaxial layer 24 (semiconductor layer) formed on the silicon substrate 20. The epitaxial layer 24 is element-isolated by a pair of element isolation diffusion layers 26. Field oxide films 40a and 40b are formed on the pair of element isolation diffusion layers 26, respectively.

  Further, a P-type body region (P-type well) 70 is formed in the epitaxial layer 24. The body region 70 includes a channel region in contact with the lower surface of the gate insulating film 50 described later.

  In a region surrounded by the body region 70, an N + type source region 130 is formed which is shallower than the body region 70 and into which a high concentration N type impurity is diffused.

  In the region surrounded by the body region 70, a P + type diffusion region 150 in which a high concentration P type impurity is diffused is formed adjacent to the source region 130 on the field oxide film 40a side. The potential of the body region 70 is fixed by the P + type diffusion region 150. In the region surrounded by the body region 70, an N− type diffusion region 90 in which a low concentration N type impurity is diffused is formed adjacent to the source region 130 on the channel region side.

  Source contact regions 180 are provided on the surfaces of the source region 130 and the P + type diffusion region 150. As the source contact region 180, for example, metal silicide such as titanium silicide is used.

  In addition, an N − type drift region 80 is formed on the epitaxial layer 24 so as to be separated from the body region 70 and in which an N type impurity having a higher concentration than the epitaxial layer 24 is diffused.

  In a region surrounded by the drift region 80, an N− type diffusion region 100 in which an N-type impurity having a higher concentration than the drift region 80 is diffused is formed.

  Further, a drain region 140 in which an N-type impurity having a higher concentration than that of the diffusion region 100 is diffused is formed in a region surrounded by the diffusion region 100. In other words, in the power semiconductor device of the present embodiment, the concentration of the N-type impurity satisfies the drain region 140> the diffusion region 100> the drift region 80.

  A drain contact region 182 is provided on the surface of the drain region 140. As the drain contact region 182, for example, a metal silicide such as titanium silicide is used.

  A gate electrode 60 is provided above the channel region, which is a part of the body region 70, the exposed portion of the epitaxial layer 24, and the exposed portion of the drift region 80 via a gate insulating film 50. The gate electrode 60 is made of, for example, polysilicon. An insulating film 62 made of a silicon oxide film is formed on a part of the side surface and upper surface of the gate electrode 60, and a metal film is formed on the other part of the upper surface by metal silicide such as titanium silicide. A sidewall 110 is provided on the side surface of the gate electrode 60 with an insulating film 62 interposed therebetween.

  A silicide block 170 is formed so as to cover a part of the drain side of the insulating film 62 provided above the exposed surface of the drift region 80 and the diffusion region 100 and on the drain side sidewall 110 and the upper surface of the gate electrode 60. Yes. The silicide block 170 suppresses the lower resistance of the drift region 80 and the diffusion region 100 between the drain region 140 and the gate electrode 60, thereby improving the drain breakdown voltage.

  The drain breakdown voltage can be adjusted by changing the offset amount between the drain region 140 and the gate electrode 60. For example, by setting the offset amount between the drain region 140 and the gate electrode 60 to 0.4 μm, the drain withstand voltage can be set to 13V. Further, by setting the offset amount to 0.7 μm, the drain breakdown voltage can be set to 18V. The voltage applied to the gate electrode 60 is 3V.

  According to power semiconductor device 10 according to the present embodiment, diffusion region 100 between drain region 140 and drift region 80 has a higher N-type impurity concentration than drift region 80 and a lower N-type impurity concentration than drain region 140. Is formed. For this reason, since the electric field concentration between the drain region 140 and the drift region 80 is relaxed, the pressure resistance of the power semiconductor device 10 can be improved.

  Next, a method for manufacturing the power semiconductor device 10 according to the embodiment will be described. 2 to 8 are process cross-sectional views illustrating the method for manufacturing the power semiconductor device 10 according to the embodiment.

  First, as shown in FIG. 2A, for example, a P-type single crystal silicon substrate 20 is prepared as a P-type single crystal semiconductor substrate.

  Next, as shown in FIG. 2B, a resist 21 is formed on the silicon substrate 20 to mask the element formation region. Subsequently, B (boron) is ion-implanted into the upper surface of the silicon substrate 20 using the resist 21 as a mask, and the implanted B (boron) is activated by heat treatment. Thereby, an element isolation diffusion layer 26a that isolates the element formation region is formed. Thereafter, the resist 21 is removed.

  Next, as shown in FIG. 2C, an N − type epitaxial layer 24 is epitaxially grown above the silicon substrate 20. Subsequently, a resist (not shown) similar to that shown in FIG. 2B is formed, B (boron) is ion-implanted into the upper surface of the epitaxial layer 24, and the implanted B (boron) is heat-treated by heat treatment. To do. As a result, the upper element isolation diffusion layer 26b reaching the lower element isolation diffusion layer 26a is formed. Hereinafter, the element isolation diffusion layer 26 a and the element isolation diffusion layer 26 b are collectively referred to as an element isolation diffusion layer 26.

  Next, as shown in FIG. 3A, a pad oxide film 28 is formed using a dry thermal oxidation method, and silicon nitride is formed on the pad oxide film 28 using a low pressure CVD method or an LP-TEOS method. A film 29 is formed.

  Next, as shown in FIG. 3B, using a well-known photolithography method, a portion corresponding to the element isolation region becomes an opening 31, and a resist 30 having a predetermined pattern corresponding to the active region is formed. Subsequently, the pad oxide film 28, the silicon nitride film 29, the epitaxial layer 24 and the element isolation diffusion layer 26 in the field element isolation region are selectively removed using the resist 30 as a mask. Thereafter, the resist 30 is removed.

  Next, as shown in FIG. 3C, the field oxide films 40a and 40b are expanded and oxidized in a pair of element isolation regions sandwiching the active region, respectively, using a high temperature wet thermal oxidation method. Thereafter, the silicon nitride film 29 is removed.

  Next, as shown in FIG. 4A, after the pad oxide film 28 is removed, a gate insulating film 50 is formed on the epitaxial layer 24 using a dry thermal oxidation method. The film thickness of the gate insulating film 50 is, for example, 5 to 20 nm.

  Next, as shown in FIG. 4B, a polysilicon film 58 is formed by plasma CVD. The thickness of the polysilicon film 58 is, for example, 100 to 300 nm.

  Next, as shown in FIG. 4C, the resist 32 is patterned by using a well-known photolithography method so that the gate electrode formation region is masked. Subsequently, using the resist 32 as a mask, the polysilicon film 58 shown in FIG. 4B is selectively removed, and a gate electrode 60 is formed. After forming the gate electrode 60, the resist 32 is removed.

  Next, as shown in FIG. 5A, an insulating film 62 made of a silicon oxide film is formed on the upper surface and side surfaces of the gate electrode 60 by thermal oxidation.

Next, as shown in FIG. 5B, the resist 34 is patterned using a known photolithography method so that the portion corresponding to the P-type body region becomes the opening 33. Subsequently, B (boron) ions are implanted through the opening 33 formed in the resist 34 to form a P-type body region 70. The dose amount of B (boron) is, for example, 5E11 to 5E13 cm ⁻² .

Next, as shown in FIG. 5C, the resist 36 is patterned by using a well-known photolithography method so that portions corresponding to the low-concentration N-type region and the drain region become openings 35. Subsequently, P (phosphorus) ions are implanted through the opening 35 formed in the resist 36 to form a drift region 80. The dose amount of P (phosphorus) is, for example, 1E12 to 5E13 cm ⁻² .

Next, as shown in FIG. 6A, the resist 38 is patterned using a known photolithography method so that the portion corresponding to the source region becomes the opening 37a and the portion corresponding to the drain region becomes the opening 37b. Subsequently, P (phosphorus) is ion-implanted through the openings 37 a and 37 b formed in the resist 38 to form an N − -type diffusion region 90 and a diffusion region 100, respectively. The dose amount of P (phosphorus) is, for example, 5E12 to 1E14 cm ⁻² . Thus, by forming the N-type diffusion region 90 on the source side and the N-type diffusion region 100 for relaxing the electric field on the drain side in the same process, the manufacturing process is simplified, and the manufacturing time and the manufacturing cost are reduced. Can be reduced.

  Next, as shown in FIG. 6B, after a silicon oxide film (not shown) is formed by plasma CVD, sidewalls 110 are formed on the side surfaces of the gate electrode 60 by etch back.

  Next, as shown in FIG. 6C, a silicon nitride film 120 is formed using a CVD method or a plasma CVD method.

Next, as shown in FIG. 7A, a resist 122 having a predetermined pattern in which the source region and the drain region become openings is formed by using a well-known photolithography method. Subsequently, As (arsenic) is ion-implanted using the resist 122 as a mask, the source region 130 and the drain region 140 are formed by performing rapid thermal processing. At this time, the silicon nitride film 120 becomes a barrier layer, and the diffusion of As is suppressed. The dose amount of As (arsenic) is, for example, 8E14 to 8E15 cm ⁻² .

  After the source region 130 and the drain region 140 are formed, the resist 122 is removed.

  Next, as shown in FIG. 7B, a resist 124 having a predetermined pattern is formed by using a well-known photolithography method so that the region between the source region 130 and the field oxide film 40a becomes an opening. Subsequently, boron of high concentration is ion-implanted into the body region using the resist 124 as a mask to form a P + type diffusion region 150. After the P + type diffusion region 150 is formed, the resist 124 is removed.

  Next, as shown in FIG. 7C, a silicon oxide film 160 is formed on the entire surface by plasma CVD.

  Next, as shown in FIG. 8A, by using a photolithography method, an offset portion between the drain region 140 and the gate electrode 60, a side surface on the drain side of the gate electrode 60, and an upper surface on the drain side of the gate electrode 60 are used. A resist 126 having a predetermined pattern is formed so that the silicide block forming region corresponding to a part is masked. Further, using the resist 126 as a mask, the silicon oxide film 160 shown in FIG. 7C is selectively removed to form a silicide block 170. After the silicide block 170 is formed, the resist 126 is removed.

  Next, as shown in FIG. 8B, a titanium film is formed by physical vapor deposition (PVD), and then high-speed heat treatment is performed. As a result, silicon in the source region 130, the P-type diffusion region 150, and the drain region 140 reacts with the formed titanium, and the source contact region 180, the drain made of a titanium silicide film on the source side and the drain side, respectively. Contact region 182 is formed. At this time, since the silicide region 170 protects the drift region 80 and the diffusion region 100 between the drain region 140 and the gate electrode 60, the resistance of the region is prevented from being lowered, and the drain breakdown voltage is improved. A titanium silicide film 184 is formed on the exposed portion of the upper surface of the gate electrode 60.

  According to the above manufacturing process, the power semiconductor device according to the embodiment can be manufactured.

  The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. The form can also be included in the scope of the present invention.

  For example, in the above-described embodiment, an N-type power semiconductor device has been exemplified. However, it can be easily understood by those skilled in the art that the present invention can be applied to a P-type power semiconductor device.

  In the above-described embodiment, the N-type diffusion region 100 for relaxing the electric field on the drain side is formed in the same process as the formation of the N-type diffusion region 90 on the source side. A step of forming the N− type diffusion region 100 for relaxing the electric field on the side may be provided separately.

It is sectional drawing which shows the structure of the power semiconductor device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment.

Explanation of symbols

10 power semiconductor device, 20 silicon substrate, 24 epitaxial layer, 26 element isolation diffusion layer, 50 gate insulating film, 60 gate electrode, 70 body region, 80 drift region, 90 diffusion region, 100 diffusion region, 130 source region, 150 diffusion Region, 170 silicide block, 180 source contact region, 182 drain contact region.

Claims (4)

A second conductivity type body region including a channel region formed in the first conductivity type semiconductor layer;
A gate electrode formed on the channel region via a gate insulating film;
A source region of a first conductivity type formed in the body region on one side of the channel region;
A first conductivity type drain region formed in a first conductivity type semiconductor layer spaced apart from the gate electrode on the other side of the channel region;
A first impurity region of a first conductivity type formed between the channel region and the drain region and having an impurity concentration lower than that of the drain region;
A second impurity region of a first conductivity type interposed between the first impurity region and the drain region, having a higher impurity concentration than the first impurity region and a lower impurity concentration than the drain region;
A power semiconductor device comprising:   The power semiconductor device according to claim 1, wherein the second impurity region surrounds the drain region. Forming a gate insulating film on the semiconductor layer of the first conductivity type;
Forming a gate electrode on the gate insulating film;
Forming a second conductivity type body region including a channel region in the semiconductor layer on the source side;
Forming a first impurity region of a first conductivity type in the semiconductor layer on the drain side;
Forming a first conductivity type low concentration impurity region in the body region adjacent to the channel region on the source side;
Forming a second impurity region of a first conductivity type having an impurity concentration higher than that of the first impurity region so that the first impurity region is interposed in the channel region on the drain side;
Forming a source region of a first conductivity type in the body region such that the low concentration impurity region is interposed in the channel region on the source side;
Forming a drain region having an impurity concentration higher than that of the second impurity region such that the first impurity region and the second impurity region are sequentially interposed with respect to the channel region on the drain side;
A method for manufacturing a power semiconductor device, comprising:   4. The method of manufacturing a power semiconductor device according to claim 3, wherein the step of forming the low concentration impurity region on the source side and the step of forming the second impurity region on the drain side are performed in the same step. .

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