US10784337B2 - MOSFET and a method for manufacturing the same - Google Patents

MOSFET and a method for manufacturing the same Download PDF

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US10784337B2
US10784337B2 US16/529,990 US201916529990A US10784337B2 US 10784337 B2 US10784337 B2 US 10784337B2 US 201916529990 A US201916529990 A US 201916529990A US 10784337 B2 US10784337 B2 US 10784337B2
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source
drain
polysilicon gate
drain region
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Yu Chen
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Definitions

  • the present invention relates to the field of semiconductor integrated circuit, more particularly to a metal-oxide semiconductor field-effect transistor (MOSFET); the present invention further relates to a method for manufacturing the MOSFET.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • the existing MOSFET is structured as shown in FIG. 1 .
  • the existing MOSFET includes:
  • a gate dielectric layer such as a gate oxide layer 102 , and a polysilicon gate sequentially formed on the surface of said well region 101 .
  • Lightly doped drain regions 104 and heavily doped source/drain implanted regions 106 are formed in said well region 101 on both sides of said polysilicon gate 103 , wherein said lightly doped drain regions 104 are self-aligned with the sides of said polysilicon gate 103 , and said source/drain implanted regions 106 are self-aligned with the sides of said side walls 105 on both sides of said polysilicon gate 103 .
  • the overlap between said lightly doped drain region 104 and said source/drain implanted region 106 on one side of said polysilicon gate 103 constitutes the source region, and the overlap between said lightly doped drain region 104 and said source/drain implanted region 106 on the other side of said polysilicon gate 103 constitutes the drain region.
  • said source region and said drain region of the existing MOSFET are totally symmetrical and have identical performance, such as breakdown voltage, parasitic resistance and capacitance.
  • the breakdown voltage of the device needs to be raised by increasing the concentration of impurity in the source and drain regions, and the junction depths of the source and drain regions.
  • the channel of the device will have to be increased accordingly with the junction depths of the source and drain regions, so raising the breakdown voltage of the device is in contradiction with reducing the dimensions of the device.
  • the increase in the size of individual devices significantly influences the size of the whole chip.
  • the thickness of gate oxide layer 102 of the device needs to be reduced, in order to reduce the gate-induced drain leakage (GIDL) current, which is induced by the high electric field between gate and drain, around the border between the source and drain junctions and polysilicon gate 103 .
  • GIDL gate-induced drain leakage
  • the present invention aims to provide a MOSFET, which increases the breakdown voltage of the device while reducing its dimensions, and reduces the GIDL effect in the device while increasing its current driving capability.
  • the MOSFET provided in the present invention includes:
  • a gate dielectric layer and a polysilicon gate sequentially formed on the surface of the well region
  • the drain region is self-aligned with a first side of said polysilicon gate
  • the source region is self-aligned with a second side of said polysilicon gate.
  • the source region and the drain region are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of said drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
  • the gate dielectric layer is unsymmetrical in structure, wherein the gate dielectric layer includes a first gate dielectric section and a second gate dielectric section which are horizontally connected; the thickness of the first gate dielectric section is greater than that of the second gate dielectric section; horizontally, the drain region extends beyond the first side of the polysilicon gate to the bottom of the polysilicon gate, thereby forming an overlap between the drain region and the polysilicon gate, with the first gate dielectric section located therein; and the GIDL effect in the device can be reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of the second gate dielectric section.
  • the semiconductor substrate is a silicon substrate.
  • the source region is formed by a heavily doped source/drain implanted region having the first conductivity type
  • the drain region is formed by an overlap between the heavily doped source/drain implanted region and a lightly doped drain region having the first conductivity type
  • the source/drain implanted region of the source region and the source/drain implanted region of the drain region are formed by the same process, and the junction depth of the drain region is adjusted through the lightly doped drain region.
  • the gate dielectric layer is a gate oxide layer.
  • the second gate dielectric section is a thermal oxide layer or deposited oxide layer, and the first gate dielectric section adds a local oxide layer to the second gate dielectric section.
  • side walls are formed on the sides of the polysilicon gate.
  • the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
  • the method for manufacturing a MOSFET provided in the present invention includes:
  • Step 1 providing a semiconductor substrate and introducing dopant having the second conductivity type in the surface thereof to form a well region;
  • Step 2 forming a first oxide layer on the surface of the semiconductor substrate by thermal oxidation or chemical vapor deposition
  • Step 3 forming a polysilicon gate on the surface of the first oxide layer by chemical vapor deposition and photolithography, wherein the polysilicon gate covers the surface of the well region via the first oxide layer;
  • Step 4 forming a first dielectric layer by chemical vapor deposition, wherein the first dielectric layer is made of silicon nitride or silicon oxynitride;
  • Step 5 removing the first dielectric layer in the drain-forming region with photolithography and etching processes, while retaining the first dielectric layer in the source-forming region, wherein the drain-forming region is located outside a first side of the polysilicon gate, the source-forming region is located outside a second side of the polysilicon gate, the reserved part of the first dielectric layer further extends from the source-forming region to the top of the polysilicon gate, and the removed part of the first dielectric layer further extends from the drain-forming region to the top of the polysilicon gate.
  • Step 6 with the photoresist on the first dielectric layer and the top thereof as a mask, conducting ion implantation of dopants having the first conductivity type to form a lightly doped drain region, wherein the lightly doped drain region is self-aligned with the first side of the polysilicon gate; the junction depth of the drain region is adjusted through ion implantation of the lightly doped drain region; and horizontally, the lightly doped drain region extends from the first side of the polysilicon gate to the bottom thereof, thereby forming an overlap between the drain region and the polysilicon gate;
  • Step 7 removing the photoresist on the top of the first dielectric layer, and with the first dielectric layer as a mask, performing local thermal oxidation to form a local thermal oxide layer, wherein the local thermal oxide layer extends from the drain-forming region to the bottom of the polysilicon gate, and then removing the first dielectric layer;
  • the overlap between the local thermal oxide layer extending to the bottom of the polysilicon gate and the first oxide layer constitutes a first gate dielectric section, and the part of the first oxide layer located at the bottom of the polysilicon gate and not overlaid with the local thermal oxide layer constitutes a second gate dielectric section;
  • the first gate dielectric section and the second gate dielectric section are connected horizontally to form a gate dielectric layer; the first gate dielectric section is located in the overlap between the drain region and the polysilicon gate; the GIDL effect in the device can be reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of the second gate dielectric section.
  • Step 8 performing source/drain implantation of impurity having the first conductivity type to form heavily doped source/drain implanted regions on both sides of the polysilicon gate, wherein each the source/drain implanted region is self-aligned with a corresponding side of the polysilicon gate, the overlap between the source/drain implanted region on the first side of the polysilicon gate and the lightly doped drain region forms a drain region, and the source/drain implanted region on the second side of the polysilicon gate forms a source region.
  • the source region and the drain region are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
  • the semiconductor substrate is a silicon substrate.
  • the side walls on the two sides of the polysilicon gate are taken as the boundaries for self-alignment, the source/drain implantation is performed at a tilt angle, the source/drain implanted regions formed thereby extend horizontally to the bottom of the side walls, and the breadth of the horizontal extension of the source/drain implanted regions is greater than the maximum horizontal breadth of the side walls.
  • the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm ⁇ 2 in source/drain implantation.
  • the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm ⁇ 2 in ion implantation of dopants to form a lightly doped drain region in Step 6.
  • the thickness of the first dielectric layer is between 50 and 300 angstroms.
  • the thickness of the local thermal oxide layer is between 30 and 300 angstroms.
  • the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
  • the source region and the drain region being configured to be unsymmetrical in structure makes it possible to increase the breakdown voltage of the device by increasing the horizontal and vertical junction depths of the drain region alone; configured as independent of the drain region in the present invention, the source region needs not be able to endure a high voltage, so the junction depth of the source region is configured to be smaller than that of the drain region, which means the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region; that is to say, the source region in the present invention can adopt a relatively smaller junction depth, thereby reducing the dimensions of the device; therefore, the present invention can increase the breakdown voltage of the device while reducing the dimensions thereof.
  • the drain region adopts a relatively greater junction depth, and horizontally extends from the first side of the polysilicon gate to the bottom thereof, thereby forming an overlap between the drain region and the polysilicon gate.
  • the gate dielectric layer is divided into two sections, the location of the first gate dielectric section coincides with the overlap, and the relative position between the two can be adjusted by self-alignment to locate the first gate dielectric section in the overlap between the drain region and the polysilicon gate.
  • the GIDL effect in the device can be reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of the second gate dielectric section. Therefore, the present invention can reduce the GIDL effect in the device and at the same time increase its current driving capability.
  • FIG. 1 describes the structure of the existing (prior art) MOSFET
  • FIG. 2 describes the structure of the MOSFET in accordance with an embodiment of the present invention
  • FIGS. 3A-3E describe the device structures in each step of the manufacturing process for MOSFET in accordance with an embodiment of the present invention.
  • the MOSFET in accordance with the embodiment of the present invention includes:
  • the semiconductor substrate is a silicon substrate.
  • the source region is formed by a heavily doped source/drain implanted region 7 having the first conductivity type
  • the drain region is formed by an overlap between heavily doped source/drain implanted region 7 and a lightly doped drain region 5 having the first conductivity type
  • source/drain implanted region 7 of the source region and source/drain implanted region 7 of the drain region are formed by the same process, and the junction depth of the drain region is adjusted through lightly doped drain region 5 .
  • each source/drain implanted region 7 is self-aligned with the side wall 6 on the corresponding side of polysilicon gate 3 , and horizontally extends to the bottom of polysilicon gate 3 on the corresponding side, with the breadth of the horizontal extension of source/drain implanted regions 7 to the bottom of polysilicon gate 3 being greater than the maximum horizontal breadth of side walls 6 .
  • Lightly doped drain region 5 is self-aligned with the first side of polysilicon gate 3 , and horizontally extends from the first side of polysilicon gate 3 to the bottom thereof, thereby forming an overlap between the drain region and polysilicon gate 3 ;
  • the source region and the drain region are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
  • the gate dielectric layer is unsymmetrical in structure, wherein the gate dielectric layer includes a first gate dielectric section 4 and a second gate dielectric section 2 which are horizontally connected; the thickness of first gate dielectric section 4 is greater than that of second gate dielectric section 2 ; first gate dielectric section 4 is located in the overlap between the drain region and polysilicon gate 3 ; and the GIDL effect in the device can be reduced by increasing the thickness of first gate dielectric section 4 , and the driving current of the device can be increased by reducing the thickness of second gate dielectric section 2 .
  • second gate dielectric section 2 is a thermal oxide layer or deposited oxide layer, and first gate dielectric section 4 adds a local oxide layer to second gate dielectric section 2 .
  • the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
  • FIGS. 3A-3E describe the device structures in each step of the manufacturing process for MOSFET in accordance with an embodiment of the present invention.
  • Step 1 as shown in 3 A, providing a semiconductor substrate and introducing dopant having the second conductivity type in the surface thereof to form well region 1 .
  • said semiconductor substrate is a silicon substrate.
  • Step 2 as shown in 3 A, forming first oxide layer 2 on the surface of said semiconductor substrate by thermal oxidation or chemical vapor deposition.
  • Step 3 as shown in 3 A, forming polysilicon gate 3 on the surface of first oxide layer 2 by chemical vapor deposition and photolithography, wherein polysilicon gate 3 covers the surface of well region 1 via first oxide layer 2 .
  • Step 4 as shown in 3 B, forming a first dielectric layer 201 by chemical vapor deposition, wherein first dielectric layer 201 is made of silicon nitride or silicon oxynitride.
  • first dielectric layer 201 is made of silicon nitride or silicon oxynitride.
  • the thickness of first dielectric layer 201 is between 50 and 300 angstroms.
  • Step 5 as shown in FIG. 3C , forming the pattern of a photoresist 202 with photolithography, removing first dielectric layer 201 in the drain-forming region with etching process, while retaining first dielectric layer 201 in the source-forming region, wherein the drain-forming region is located outside the first side of polysilicon gate 3 , the source-forming region is located outside the second side of polysilicon gate 3 , the reserved part of first dielectric layer 201 further extends from the source-forming region to the top of polysilicon gate 3 , and the removed part of first dielectric layer 201 further extends from the drain-forming region to the top of polysilicon gate 3 .
  • Step 6 as shown in FIG. 3C , with photoresist 202 on first dielectric layer 201 and the top thereof as a mask, conducting ion implantation of dopants having the first conductivity type to form a lightly doped drain region 5 , wherein lightly doped drain region 5 is self-aligned with the first side of polysilicon gate 3 ; the junction depth of the drain region is adjusted through ion implantation of lightly doped drain region 5 ; and horizontally, lightly doped drain region 5 extends from the first side of polysilicon gate 3 to the bottom thereof, thereby forming an overlap between the drain region and polysilicon gate 3 .
  • the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm 2 in source/drain implantation.
  • Step 7 as shown in FIG. 3D , removing photoresist 202 on the top of first dielectric layer 201 , and using first dielectric layer 201 as a mask, performing local thermal oxidation to form a local thermal oxide layer 4 , wherein local thermal oxide layer 4 extends from the drain-forming region to the bottom of polysilicon gate 3 , and then removing first dielectric layer 201 .
  • the thickness of local thermal oxide layer 4 is between 30 and 300 angstroms.
  • first gate dielectric section 4 The overlap between local thermal oxide layer 4 extending to the bottom of polysilicon gate 3 and first oxide layer 2 constitutes first gate dielectric section 4 , and first oxide layer 2 located at the bottom of polysilicon gate 3 and not overlaid with local thermal oxide layer 4 constitutes second gate dielectric section 2 ;
  • First gate dielectric section 4 and second gate dielectric section 2 are horizontally connected to form the gate dielectric layer; first gate dielectric section 4 is located in the overlap between the drain region and polysilicon gate 3 ; the GIDL effect in the device can be reduced by increasing the thickness of first gate dielectric section 4 , and the driving current of the device can be increased by reducing the thickness of second gate dielectric section 2 .
  • Step 8 as shown in FIG. 3E , prior to performing source/drain implantation, side walls 6 are formed on the sides of polysilicon gate 3 with deposition and etching processes.
  • source/drain implanted regions 7 are formed on both sides of polysilicon gate 3 ; side walls 6 on the two sides of polysilicon gate 3 are taken as the boundaries for self-alignment, source/drain implantation is performed at a tilt angle, source/drain implanted regions 7 formed thereby extend horizontally to the bottom of side walls 6 , and the breadth of the horizontal extension of source/drain implanted regions 7 is greater than the maximum horizontal breadth of side walls 6 .
  • the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm ⁇ 2 in source/drain implantation.
  • source/drain implanted region 7 on the first side of polysilicon gate 3 and lightly doped drain region 5 forms the drain region
  • source/drain implanted region 7 on the second side of polysilicon gate 3 forms the source region
  • the source and drain regions are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
  • the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type.
  • the MOSFET may be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

Abstract

A method of manufacturing a MOSFET is presented. The method includes forming the MOSFET wherein a source region and a drain region are unsymmetrical in structure, with the horizontal junction depth of the drain region greater than the source region, and the vertical junction depth of the drain region greater than the source region; the breakdown voltage of the device is raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device is diminished by reducing the horizontal and vertical junction depths of the source region. In one embodiment, the formed MOSFET includes a gate dielectric layer that is unsymmetrical in structure—and the GIDL effect in the device is reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device is increased by reducing the thickness of the second gate dielectric section.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
The present application is a divisional application of U.S. patent application Ser. No. 15/363,288, filed on Nov. 29, 2016, which claims priority to Chinese Patent Application No. 201610566545.8, filed on Jul. 19, 2016. The entireties of these patent documents are incorporated by reference herein.
TECHNICAL FIELD
The present invention relates to the field of semiconductor integrated circuit, more particularly to a metal-oxide semiconductor field-effect transistor (MOSFET); the present invention further relates to a method for manufacturing the MOSFET.
BACKGROUND OF THE INVENTION
For MOS devices frequently used in current semiconductor fabrication technology, the existing MOSFET is structured as shown in FIG. 1. Taking an N-type MOSFET as an example, the existing MOSFET includes:
P-type well region 101 formed in the surface of the semiconductor substrate.
A gate dielectric layer, such as a gate oxide layer 102, and a polysilicon gate sequentially formed on the surface of said well region 101.
Side walls 105 formed on both sides of said polysilicon gate 103.
Lightly doped drain regions 104 and heavily doped source/drain implanted regions 106 are formed in said well region 101 on both sides of said polysilicon gate 103, wherein said lightly doped drain regions 104 are self-aligned with the sides of said polysilicon gate 103, and said source/drain implanted regions 106 are self-aligned with the sides of said side walls 105 on both sides of said polysilicon gate 103. The overlap between said lightly doped drain region 104 and said source/drain implanted region 106 on one side of said polysilicon gate 103 constitutes the source region, and the overlap between said lightly doped drain region 104 and said source/drain implanted region 106 on the other side of said polysilicon gate 103 constitutes the drain region.
As described in FIG. 1, said source region and said drain region of the existing MOSFET are totally symmetrical and have identical performance, such as breakdown voltage, parasitic resistance and capacitance.
For the existing structure, the breakdown voltage of the device needs to be raised by increasing the concentration of impurity in the source and drain regions, and the junction depths of the source and drain regions. To avoid source/drain punch through, the channel of the device will have to be increased accordingly with the junction depths of the source and drain regions, so raising the breakdown voltage of the device is in contradiction with reducing the dimensions of the device. For power-related applications which need an array of devices, the increase in the size of individual devices significantly influences the size of the whole chip.
At the same time, in prior art, the thickness of gate oxide layer 102 of the device needs to be reduced, in order to reduce the gate-induced drain leakage (GIDL) current, which is induced by the high electric field between gate and drain, around the border between the source and drain junctions and polysilicon gate 103. However, the thickening of gate oxide layer 102 will be accompanied by the weakening of the current driving capability of the device, so in the existing structure, reducing GIDL is in contradiction with increasing the current driving capability of the device.
SUMMARY OF THE INVENTION
The present invention aims to provide a MOSFET, which increases the breakdown voltage of the device while reducing its dimensions, and reduces the GIDL effect in the device while increasing its current driving capability.
To solve e.g., the above technological problems, the MOSFET provided in the present invention includes:
A well region of the second conductivity type formed in the surface of the semiconductor substrate;
A gate dielectric layer and a polysilicon gate sequentially formed on the surface of the well region;
A doped source region of the first conductivity type and a doped drain region of the first conductivity type respectively formed in the surface of the well region;
Wherein, the drain region is self-aligned with a first side of said polysilicon gate, and the source region is self-aligned with a second side of said polysilicon gate.
The source region and the drain region are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of said drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
The gate dielectric layer is unsymmetrical in structure, wherein the gate dielectric layer includes a first gate dielectric section and a second gate dielectric section which are horizontally connected; the thickness of the first gate dielectric section is greater than that of the second gate dielectric section; horizontally, the drain region extends beyond the first side of the polysilicon gate to the bottom of the polysilicon gate, thereby forming an overlap between the drain region and the polysilicon gate, with the first gate dielectric section located therein; and the GIDL effect in the device can be reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of the second gate dielectric section.
As a further improvement, the semiconductor substrate is a silicon substrate.
As a further improvement, the source region is formed by a heavily doped source/drain implanted region having the first conductivity type, the drain region is formed by an overlap between the heavily doped source/drain implanted region and a lightly doped drain region having the first conductivity type, the source/drain implanted region of the source region and the source/drain implanted region of the drain region are formed by the same process, and the junction depth of the drain region is adjusted through the lightly doped drain region.
As a further improvement, the gate dielectric layer is a gate oxide layer.
As a further improvement, the second gate dielectric section is a thermal oxide layer or deposited oxide layer, and the first gate dielectric section adds a local oxide layer to the second gate dielectric section.
As a further improvement, side walls are formed on the sides of the polysilicon gate.
As a further improvement, the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
To solve the above technological problems, the method for manufacturing a MOSFET provided in the present invention includes:
Step 1: providing a semiconductor substrate and introducing dopant having the second conductivity type in the surface thereof to form a well region;
Step 2: forming a first oxide layer on the surface of the semiconductor substrate by thermal oxidation or chemical vapor deposition;
Step 3: forming a polysilicon gate on the surface of the first oxide layer by chemical vapor deposition and photolithography, wherein the polysilicon gate covers the surface of the well region via the first oxide layer;
Step 4: forming a first dielectric layer by chemical vapor deposition, wherein the first dielectric layer is made of silicon nitride or silicon oxynitride;
Step 5: removing the first dielectric layer in the drain-forming region with photolithography and etching processes, while retaining the first dielectric layer in the source-forming region, wherein the drain-forming region is located outside a first side of the polysilicon gate, the source-forming region is located outside a second side of the polysilicon gate, the reserved part of the first dielectric layer further extends from the source-forming region to the top of the polysilicon gate, and the removed part of the first dielectric layer further extends from the drain-forming region to the top of the polysilicon gate.
Step 6: with the photoresist on the first dielectric layer and the top thereof as a mask, conducting ion implantation of dopants having the first conductivity type to form a lightly doped drain region, wherein the lightly doped drain region is self-aligned with the first side of the polysilicon gate; the junction depth of the drain region is adjusted through ion implantation of the lightly doped drain region; and horizontally, the lightly doped drain region extends from the first side of the polysilicon gate to the bottom thereof, thereby forming an overlap between the drain region and the polysilicon gate;
Step 7: removing the photoresist on the top of the first dielectric layer, and with the first dielectric layer as a mask, performing local thermal oxidation to form a local thermal oxide layer, wherein the local thermal oxide layer extends from the drain-forming region to the bottom of the polysilicon gate, and then removing the first dielectric layer;
The overlap between the local thermal oxide layer extending to the bottom of the polysilicon gate and the first oxide layer constitutes a first gate dielectric section, and the part of the first oxide layer located at the bottom of the polysilicon gate and not overlaid with the local thermal oxide layer constitutes a second gate dielectric section;
The first gate dielectric section and the second gate dielectric section are connected horizontally to form a gate dielectric layer; the first gate dielectric section is located in the overlap between the drain region and the polysilicon gate; the GIDL effect in the device can be reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of the second gate dielectric section.
Step 8: performing source/drain implantation of impurity having the first conductivity type to form heavily doped source/drain implanted regions on both sides of the polysilicon gate, wherein each the source/drain implanted region is self-aligned with a corresponding side of the polysilicon gate, the overlap between the source/drain implanted region on the first side of the polysilicon gate and the lightly doped drain region forms a drain region, and the source/drain implanted region on the second side of the polysilicon gate forms a source region.
The source region and the drain region are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
As a further improvement, the semiconductor substrate is a silicon substrate.
As a further improvement, prior to performing the source/drain implantation in Step 8, side walls are formed on the sides of the polysilicon gate by deposition and etching processes.
When performing source/drain implantation, the side walls on the two sides of the polysilicon gate are taken as the boundaries for self-alignment, the source/drain implantation is performed at a tilt angle, the source/drain implanted regions formed thereby extend horizontally to the bottom of the side walls, and the breadth of the horizontal extension of the source/drain implanted regions is greater than the maximum horizontal breadth of the side walls.
As a further improvement, the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm−2 in source/drain implantation.
As a further improvement, the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm−2 in ion implantation of dopants to form a lightly doped drain region in Step 6.
As a further improvement, the thickness of the first dielectric layer is between 50 and 300 angstroms.
As a further improvement, the thickness of the local thermal oxide layer is between 30 and 300 angstroms.
As a further improvement, the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
In the present invention, the source region and the drain region being configured to be unsymmetrical in structure makes it possible to increase the breakdown voltage of the device by increasing the horizontal and vertical junction depths of the drain region alone; configured as independent of the drain region in the present invention, the source region needs not be able to endure a high voltage, so the junction depth of the source region is configured to be smaller than that of the drain region, which means the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region; that is to say, the source region in the present invention can adopt a relatively smaller junction depth, thereby reducing the dimensions of the device; therefore, the present invention can increase the breakdown voltage of the device while reducing the dimensions thereof.
In the present invention, the drain region adopts a relatively greater junction depth, and horizontally extends from the first side of the polysilicon gate to the bottom thereof, thereby forming an overlap between the drain region and the polysilicon gate. The gate dielectric layer is divided into two sections, the location of the first gate dielectric section coincides with the overlap, and the relative position between the two can be adjusted by self-alignment to locate the first gate dielectric section in the overlap between the drain region and the polysilicon gate. In accordance with the present invention, the GIDL effect in the device can be reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of the second gate dielectric section. Therefore, the present invention can reduce the GIDL effect in the device and at the same time increase its current driving capability.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be described in detail by reference to the accompanying drawings and specific embodiments:
FIG. 1 describes the structure of the existing (prior art) MOSFET;
FIG. 2 describes the structure of the MOSFET in accordance with an embodiment of the present invention;
FIGS. 3A-3E describe the device structures in each step of the manufacturing process for MOSFET in accordance with an embodiment of the present invention.
 DETAILED DESCRIPTION OF THE EMBODIMENTS
As shown in FIGS. 3A-3E, which describe the device structures in each step of the manufacturing process for MOSFET in accordance with the embodiment of the present invention, the MOSFET in accordance with the embodiment of the present invention includes:
A well region 1 of the second conductivity type formed in the surface of the semiconductor substrate. Preferably, the semiconductor substrate is a silicon substrate.
A gate dielectric layer and a polysilicon gate 3 sequentially formed on the surface of well region 1.
A doped source region of the first conductivity type and a doped drain region of the first conductivity type respectively formed in the surface of well region 1. Preferably, the source region is formed by a heavily doped source/drain implanted region 7 having the first conductivity type, the drain region is formed by an overlap between heavily doped source/drain implanted region 7 and a lightly doped drain region 5 having the first conductivity type, source/drain implanted region 7 of the source region and source/drain implanted region 7 of the drain region are formed by the same process, and the junction depth of the drain region is adjusted through lightly doped drain region 5.
Side walls 6 formed on the sides of polysilicon gate 3, wherein the drain region is self-aligned with the first side of polysilicon gate 3 and the source region is self-aligned with the other side of polysilicon gate 3. Preferably, each source/drain implanted region 7 is self-aligned with the side wall 6 on the corresponding side of polysilicon gate 3, and horizontally extends to the bottom of polysilicon gate 3 on the corresponding side, with the breadth of the horizontal extension of source/drain implanted regions 7 to the bottom of polysilicon gate 3 being greater than the maximum horizontal breadth of side walls 6. Lightly doped drain region 5 is self-aligned with the first side of polysilicon gate 3, and horizontally extends from the first side of polysilicon gate 3 to the bottom thereof, thereby forming an overlap between the drain region and polysilicon gate 3;
As shown in FIG. 2, in accordance with an embodiment of the present invention, the source region and the drain region are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
The gate dielectric layer is unsymmetrical in structure, wherein the gate dielectric layer includes a first gate dielectric section 4 and a second gate dielectric section 2 which are horizontally connected; the thickness of first gate dielectric section 4 is greater than that of second gate dielectric section 2; first gate dielectric section 4 is located in the overlap between the drain region and polysilicon gate 3; and the GIDL effect in the device can be reduced by increasing the thickness of first gate dielectric section 4, and the driving current of the device can be increased by reducing the thickness of second gate dielectric section 2. Preferably, second gate dielectric section 2 is a thermal oxide layer or deposited oxide layer, and first gate dielectric section 4 adds a local oxide layer to second gate dielectric section 2.
In accordance with an embodiment of the present invention, the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
FIGS. 3A-3E describe the device structures in each step of the manufacturing process for MOSFET in accordance with an embodiment of the present invention. A method of manufacturing the MOSFET in accordance with an embodiment, comprising the steps of
Step 1: as shown in 3A, providing a semiconductor substrate and introducing dopant having the second conductivity type in the surface thereof to form well region 1. Preferably, said semiconductor substrate is a silicon substrate.
Step 2: as shown in 3A, forming first oxide layer 2 on the surface of said semiconductor substrate by thermal oxidation or chemical vapor deposition.
Step 3: as shown in 3A, forming polysilicon gate 3 on the surface of first oxide layer 2 by chemical vapor deposition and photolithography, wherein polysilicon gate 3 covers the surface of well region 1 via first oxide layer 2.
Step 4: as shown in 3B, forming a first dielectric layer 201 by chemical vapor deposition, wherein first dielectric layer 201 is made of silicon nitride or silicon oxynitride. Preferably, the thickness of first dielectric layer 201 is between 50 and 300 angstroms.
Step 5: as shown in FIG. 3C, forming the pattern of a photoresist 202 with photolithography, removing first dielectric layer 201 in the drain-forming region with etching process, while retaining first dielectric layer 201 in the source-forming region, wherein the drain-forming region is located outside the first side of polysilicon gate 3, the source-forming region is located outside the second side of polysilicon gate 3, the reserved part of first dielectric layer 201 further extends from the source-forming region to the top of polysilicon gate 3, and the removed part of first dielectric layer 201 further extends from the drain-forming region to the top of polysilicon gate 3.
Step 6: as shown in FIG. 3C, with photoresist 202 on first dielectric layer 201 and the top thereof as a mask, conducting ion implantation of dopants having the first conductivity type to form a lightly doped drain region 5, wherein lightly doped drain region 5 is self-aligned with the first side of polysilicon gate 3; the junction depth of the drain region is adjusted through ion implantation of lightly doped drain region 5; and horizontally, lightly doped drain region 5 extends from the first side of polysilicon gate 3 to the bottom thereof, thereby forming an overlap between the drain region and polysilicon gate 3. Preferably, the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm2 in source/drain implantation.
Step 7: as shown in FIG. 3D, removing photoresist 202 on the top of first dielectric layer 201, and using first dielectric layer 201 as a mask, performing local thermal oxidation to form a local thermal oxide layer 4, wherein local thermal oxide layer 4 extends from the drain-forming region to the bottom of polysilicon gate 3, and then removing first dielectric layer 201. Preferably, the thickness of local thermal oxide layer 4 is between 30 and 300 angstroms.
The overlap between local thermal oxide layer 4 extending to the bottom of polysilicon gate 3 and first oxide layer 2 constitutes first gate dielectric section 4, and first oxide layer 2 located at the bottom of polysilicon gate 3 and not overlaid with local thermal oxide layer 4 constitutes second gate dielectric section 2;
First gate dielectric section 4 and second gate dielectric section 2 are horizontally connected to form the gate dielectric layer; first gate dielectric section 4 is located in the overlap between the drain region and polysilicon gate 3; the GIDL effect in the device can be reduced by increasing the thickness of first gate dielectric section 4, and the driving current of the device can be increased by reducing the thickness of second gate dielectric section 2.
Step 8: as shown in FIG. 3E, prior to performing source/drain implantation, side walls 6 are formed on the sides of polysilicon gate 3 with deposition and etching processes.
As shown in FIG. 2, when performing source/drain implantation of impurity having the first conductivity type, heavily doped source/drain implanted regions 7 are formed on both sides of polysilicon gate 3; side walls 6 on the two sides of polysilicon gate 3 are taken as the boundaries for self-alignment, source/drain implantation is performed at a tilt angle, source/drain implanted regions 7 formed thereby extend horizontally to the bottom of side walls 6, and the breadth of the horizontal extension of source/drain implanted regions 7 is greater than the maximum horizontal breadth of side walls 6. Preferably, the angle between the ion beam and the vertical direction is greater than 10 degrees, and the implantation dose exceeds 5E14 cm−2 in source/drain implantation.
The overlap between source/drain implanted region 7 on the first side of polysilicon gate 3 and lightly doped drain region 5 forms the drain region, and source/drain implanted region 7 on the second side of polysilicon gate 3 forms the source region.
The source and drain regions are unsymmetrical in structure, wherein the horizontal junction depth of the drain region is greater than that of the source region, and the vertical junction depth of the drain region is greater than that of the source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of the source region.
In accordance with the embodiment of the present invention, the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In alternative embodiments, the MOSFET may be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
The present invention has been described in great detail by reference to a specific embodiment. But this does not intend to limit the scope of the present invention. Without departing from the spirit of the present invention, a person having ordinary skills in the art may make various modifications and improvements, which shall be considered to fall within the scope of the present invention.

Claims (8)

What is claimed is:
1. A method of manufacturing the MOSFET, comprising the steps of:
step 1: providing a semiconductor substrate and introducing dopant having the second conductivity type in the surface thereof to form a well region;
step 2: forming a first oxide layer on the surface of said semiconductor substrate by thermal oxidation or chemical vapor deposition;
step 3: forming a polysilicon gate on the surface of the first oxide layer by chemical vapor deposition and photolithography, wherein said polysilicon gate covers the surface of said well region via said first oxide layer;
step 4: forming a first dielectric layer by chemical vapor deposition, wherein said first dielectric layer is made of silicon nitride or silicon oxynitride;
step 5: removing said first dielectric layer in a formation region of a drain region with photolithography and etching processes, while retaining said first dielectric layer on the surface of the first oxide layer on the semiconductor substrate in a formation region of a source region, wherein said formation region of the drain region is located outside a first side of said polysilicon gate, said formation region of the source region is located outside a second side of said polysilicon gate, the reserved part of said first dielectric layer further extends from formation region of the source region to the top of said polysilicon gate, and a region where the first dielectric layer is removed further extends from said formation region of the drain region to the top of said polysilicon gate;
step 6: with a photoresist formed in photolithography process on said first dielectric layer and the top thereof as a mask, conducting ion implantation of dopants having the first conductivity type to form a lightly doped drain region, wherein said lightly doped drain region is self-aligned with the first side of said polysilicon gate; the junction depth of the drain region is adjusted through ion implantation of said lightly doped drain region; and horizontally, said lightly doped drain region extends from the first side of said polysilicon gate to the bottom thereof, thereby forming an overlap between said drain region and said polysilicon gate;
step 7: removing the photoresist on the top of said first dielectric layer, and with said first dielectric layer as a mask, performing local thermal oxidation to form a local thermal oxide layer, wherein said local thermal oxide layer extends from said formation region of the drain region to the bottom of said polysilicon gate, and then removing said first dielectric layer;
said first oxide layer located at the bottom of said polysilicon gate and not overlaid with said local thermal oxide layer constitutes a second gate dielectric section and said local thermal oxide layer extending to the bottom of said polysilicon gate constitutes a first gate dielectric section;
said first gate dielectric section and said second gate dielectric section are connected horizontally to form a gate dielectric layer; said first gate dielectric section is located in the overlap between said drain region and said polysilicon gate; the GIDL effect in the device can be reduced by increasing the thickness of said first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of said second gate dielectric section;
step 8: performing source/drain implantation of impurity having the first conductivity type to form heavily doped source/drain implanted regions on both sides of said polysilicon gate, wherein each said source/drain implanted region is self-aligned with a corresponding side of said polysilicon gate, the overlap between said source/drain implanted region on the first side of said polysilicon gate and said lightly doped drain region forms a drain region, and said source/drain implanted region on the second side of said polysilicon gate forms a source region;
said source region and said drain region are unsymmetrical in structure, wherein the horizontal junction width of said drain region is greater than that of said source region, and the vertical junction depth of said drain region is greater than that of said source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of said drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of said source region.
2. The method of manufacturing a MOSFET of claim 1, wherein said semiconductor substrate is a silicon substrate.
3. The method of manufacturing the MOSFET of claim 1, wherein prior to performing said source/drain implantation in Step 8, side walls are formed on the sides of said polysilicon gate by deposition and etching processes;
when performing said source/drain implantation, said side walls on the two sides of said polysilicon gate are taken as the boundaries for self-alignment, said source/drain implantation is performed at a tilt angle, said source/drain implanted regions formed thereby extend horizontally to the bottom of said side walls, and the breadth of the horizontal extension of said source/drain implanted regions is greater than the maximum horizontal breadth of said side walls.
4. The method of manufacturing a MOSFET of claim 3, wherein the angle between the ion beam and the vertical direction is greater than 10 degrees and the implantation dose exceeds 5E14 cm−2 in said source/drain implantation.
5. The method of manufacturing a MOSFET of claim 1, wherein the angle between the ion beam and the vertical direction is greater than 10 degrees and the implantation dose exceeds 5E14 cm−2in said ion implantation of dopants to form a lightly doped drain region in Step 6.
6. The method of manufacturing a MOSFET of claim 1, wherein the thickness of said first dielectric layer is between 50 and 300 angstroms.
7. The method of manufacturing a MOSFET of claim 1, wherein the thickness of said local thermal oxide layer is between 30 and 300 angstroms.
8. The method of manufacturing a MOSFET of claim 1, wherein the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.
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Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5741737A (en) * 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
US5801416A (en) 1995-03-13 1998-09-01 Samsung Electronics Co., Ltd. FET having gate insulating film of nonuniform thickness and asymmetrical source and drain structures
US6110783A (en) * 1997-06-27 2000-08-29 Sun Microsystems, Inc. Method for forming a notched gate oxide asymmetric MOS device
US20030141559A1 (en) * 2001-12-20 2003-07-31 Stmicroelectronics S.R.I. Metal oxide semiconductor field-effect transistor and associated methods
US20060194380A1 (en) 2005-02-25 2006-08-31 Yi-Cheng Chen Method for fabricating asymmetric semiconductor device
US20090321824A1 (en) 2008-06-25 2009-12-31 Fujitsu Microelectronics Limited Semiconductor device
US20100148258A1 (en) * 2008-12-11 2010-06-17 Cho Cheol Ho Semiconductor device and method of manufacturing the same
US20110241112A1 (en) * 2010-03-31 2011-10-06 Zuniga Marco A LDMOS Device with P-Body for Reduced Capacitance
US20120273879A1 (en) * 2011-04-27 2012-11-01 Shekar Mallikarjunaswamy Top drain ldmos
US8324042B2 (en) * 2004-07-15 2012-12-04 Fairchild Semiconductor Corporation Integrated complementary low voltage RF-LDMOS
US8809952B2 (en) * 2011-12-06 2014-08-19 Infineon Technologies Ag Lateral transistor component and method for producing same
US8822291B2 (en) * 2012-01-17 2014-09-02 Globalfoundries Singapore Pte. Ltd. High voltage device
CN104037223A (en) 2013-03-04 2014-09-10 上海华虹宏力半导体制造有限公司 Radio frequency (RF) N-type LDMOS device and manufacture method thereof
US20140252499A1 (en) 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-Oxide-Semiconductor Field-Effect Transistor with Extended Gate Dielectric Layer
US20160027899A1 (en) 2014-07-24 2016-01-28 Dongbu Hitek Co., Ltd. Semiconductor Device and Method of Manufacturing the Same
US20160315198A1 (en) 2013-12-16 2016-10-27 Japan Advanced Institute Of Science And Technology Semiconductor device, method for producing same and aliphatic polycarbonate
US9698258B2 (en) * 2014-12-23 2017-07-04 Magnachip Semiconductor, Ltd. Semiconductor device

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801416A (en) 1995-03-13 1998-09-01 Samsung Electronics Co., Ltd. FET having gate insulating film of nonuniform thickness and asymmetrical source and drain structures
US5741737A (en) * 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
US6110783A (en) * 1997-06-27 2000-08-29 Sun Microsystems, Inc. Method for forming a notched gate oxide asymmetric MOS device
US20030141559A1 (en) * 2001-12-20 2003-07-31 Stmicroelectronics S.R.I. Metal oxide semiconductor field-effect transistor and associated methods
US8324042B2 (en) * 2004-07-15 2012-12-04 Fairchild Semiconductor Corporation Integrated complementary low voltage RF-LDMOS
US20060194380A1 (en) 2005-02-25 2006-08-31 Yi-Cheng Chen Method for fabricating asymmetric semiconductor device
US8080845B2 (en) 2008-06-25 2011-12-20 Fujitsu Semiconductor Limited Semiconductor device
US20090321824A1 (en) 2008-06-25 2009-12-31 Fujitsu Microelectronics Limited Semiconductor device
US20100148258A1 (en) * 2008-12-11 2010-06-17 Cho Cheol Ho Semiconductor device and method of manufacturing the same
US20110241112A1 (en) * 2010-03-31 2011-10-06 Zuniga Marco A LDMOS Device with P-Body for Reduced Capacitance
US20120273879A1 (en) * 2011-04-27 2012-11-01 Shekar Mallikarjunaswamy Top drain ldmos
US8809952B2 (en) * 2011-12-06 2014-08-19 Infineon Technologies Ag Lateral transistor component and method for producing same
US8822291B2 (en) * 2012-01-17 2014-09-02 Globalfoundries Singapore Pte. Ltd. High voltage device
CN104037223A (en) 2013-03-04 2014-09-10 上海华虹宏力半导体制造有限公司 Radio frequency (RF) N-type LDMOS device and manufacture method thereof
US20140252499A1 (en) 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-Oxide-Semiconductor Field-Effect Transistor with Extended Gate Dielectric Layer
US20160315198A1 (en) 2013-12-16 2016-10-27 Japan Advanced Institute Of Science And Technology Semiconductor device, method for producing same and aliphatic polycarbonate
US20160027899A1 (en) 2014-07-24 2016-01-28 Dongbu Hitek Co., Ltd. Semiconductor Device and Method of Manufacturing the Same
US9698258B2 (en) * 2014-12-23 2017-07-04 Magnachip Semiconductor, Ltd. Semiconductor device

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
Final Office Action issued in corresponding U.S. Appl. No. 15/363,288 dated Dec. 8, 2017.
Final Office Action issued in corresponding U.S. Appl. No. 15/363,288 dated May 3, 2019.
First Examination Report issued in correspondinging Chinese Patent Application No. 201610566545.8, dated Oct. 8, 2018.
Non-Final Office Action issued in corresponding U.S. Appl. No. 15/363,288 dated Jul. 21, 2017.
Non-Final Office Action issued in corresponding U.S. Appl. No. 15/363,288 dated Nov. 13, 2018.
Search Report issued in corresponding Chinese Patent Application No. 2016105665458 dated Jan. 28, 2016.
Third Examination Report issued in correspondinging Chinese Patent Application No. 201610566545.8, dated May 5, 2019.

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