TW201011913A - Lateral diffused metal oxide semiconductor device - Google Patents

Lateral diffused metal oxide semiconductor device Download PDF

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TW201011913A
TW201011913A TW97133800A TW97133800A TW201011913A TW 201011913 A TW201011913 A TW 201011913A TW 97133800 A TW97133800 A TW 97133800A TW 97133800 A TW97133800 A TW 97133800A TW 201011913 A TW201011913 A TW 201011913A
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region
type
conductivity type
buffer
dopant concentration
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TW97133800A
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TWI416725B (en
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Po-An Chen
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Nuvoton Technology Corp
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Abstract

A lateral diffused metal oxide semiconductor (LDMOS) device is provided. The LDMOS device includes a substrate having a first conductive type, a deep well region having a second conductive type in the substrate, a buffer region in the deep well, a body region having the first conductive type in the buffer region, a source region having the second conductive type in the body region, a contact region having the first conductive type in the body region, a first lightly doped region having the second conductive type in the deep well region, a drain region having the second conductive type in the first lightly doped region, a channel region in a portion of the body region between the source region and the drain region, a gate structure covering the channel region and a portion of the buffer region and the second lightly doped region having the second conductive type between the source region and the channel region.

Description

〇 16 ltwf.doc/n 201011913 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種半導體元件,且特別是關於一種 橫向擴散金氧半導體元件。 【先前技術】 考κ 向擴散金氧半(lateral diffused metal oxide ❹ semiconduct〇r ; LDMOS)電晶體在操作時具有高崩潰電壓 (breakdown voltage)以及低的開啟電阻(〇n_state resistance ; Ron)。因此,不論是在典型的電源積體電路上, 或疋在智慧型電源積體電路上’ LDMOS電晶體都扮演著 極為重要的角色。 早期的LDMOS電晶體,由於其汲極端的高電場與高 及極電流會形成更多帶有更高能量的熱電子去擊穿閘介電 層,常造成電晶體壽命的減損。為提升電晶體的壽命,在 汲極與閘極之間通常會形成場氧化層,以降低電場的影 #° ^而’場氧化層的形成卻會導致開啟電阻增加,造成 飽和電流下降。雖然,增加没極區與通道區之間的漂移區 的摻質濃度可以降低元件的開啟電阻,但是卻會使得漂移 區無法完全空乏,而導致崩潰電壓下降。 為克服上述問題,因而發展出—種被稱之為雙重減少 表面電場(double Reduced Surface Field ; RESURF)結構之 LDMOS電晶體,其相關内容請參考u s卩舡% 6,〇87,232。由於麵娜結構之橫向擴散金氧半導體電晶 5 〇i61twf.doc/n 201011913 體在操作時可以使得源極區與汲極區所在的深井區完全空 乏,使源極區與汲極區之間形成均勻的電場,元件的崩潰 電壓可因此而提升,故,RESURF結構之LDM〇s電晶體 已成為目前LDMOS電晶體的主流。 然而,除了 RESURF結構之LDM〇s電晶體之外,目 前還需發展更多種可關時降低體電場_k fidd)以及表 面電場,提升崩潰電壓’使得元件具有均句的表面電場, 參 以被廣泛應用的橫向擴散金氣半導體元件。 【發明内容】 本發明實施例提供-種橫向擴散金氧半導體元件以及 此元件之製造方法。 依照本發明一實施例,提出一種橫向擴散金氧半導體 讀。此元件包括具有第-導電型之基底、财第二導電 &之深井區、緩衝區、具有第—導電型之基體區、具有第 -導電型之源極區、具有第—導電型之接觸區、 導電型之第-雜雜區、具有第二導電型之汲極區、通道 區、閘極結構以及具有第二導電型之第二淡摻雜區。深井 ^立於基底中。緩衝區位於深井區中。基·位於 中。源極區位於基體區中。接觸區位於基體區中。 摻雜區餅深井區中。祕區位於第—淡摻雜區中。通道 區位於源麵與祕區之_縣紐區巾。_ ^區與部份緩衝區。第二淡摻雜區位於源極區與通道 6 201011913 5i6ltwf.doc/n —依照本發明另—實補,提出―雜向 體兀件的製造方法。首先,在具有第—導型美底 第二導電型之第一淡摻雜區。之;形成具有 區。繼之,於緩衝區中形成具有第一 後’於部絲體區與緩衝區上軸閘極結構,_ ς e 覆蓋之基體區定義為通道區。然後,於基體區中1形:具J 第-導電型之第二淡摻雜,第二淡摻雜 巴 之後,於絲區與第-歸雜㈣分卿錢導 !==;_區。其後’於基體區中形成具有第- 本發明實施例所述之橫向擴散金氧半導體元件,其 ^作時可關時降低體電場以及表面電場,提升元件㈣ 潰電壓。 【實施方式】 ❹横向擴散金氣丰導體开件 #圖1為錄本㈣-實施例所緣示之一種橫向擴散金 氧半導體元件的剖面圖與部分上視圖。 請參照圖1,橫向擴散金氧半導體元件ί〇包括具有第 一導電型之基底100、具有第二導電型之深井區1〇2、閘極 結構150、具有第二導電型之源極區142、具有第二導電型 之汲極區144、具有第一導電型之接觸區146、具有第二導 電型之淡摻雜區118、緩衝區124、具有第一導電型之基體 7 6i61twf.doc/n 201011913 區134、具有第二導電型之淡摻雜區136以及通道區148。 第一導電型可為P型或N型,當第一導電型為p型時, 第二導電型為N型。當第一導電型為N型時,第二導電 型為P型。為方便說明,以下以P型來表示第一導電型, 以N型來表示第二導電型。〇 16 ltwf.doc/n 201011913 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor element, and more particularly to a laterally diffused MOS device. [Prior Art] The lateral diffused metal oxide ❹ semiconductor (LDMOS) transistor has a high breakdown voltage and a low turn-on resistance (〇n_state resistance; Ron) during operation. Therefore, LDMOS transistors play an extremely important role in either a typical power supply integrated circuit or on a smart power integrated circuit. Early LDMOS transistors, due to their extremely high electric field and high and extreme currents, formed more hot electrons with higher energy to break through the gate dielectric, often resulting in loss of transistor lifetime. In order to improve the life of the transistor, a field oxide layer is usually formed between the drain and the gate to reduce the influence of the electric field. The formation of the field oxide layer causes an increase in the on-resistance and a decrease in the saturation current. Although increasing the dopant concentration of the drift region between the non-polar region and the channel region can reduce the on-resistance of the device, it can make the drift region not completely depleted, resulting in a drop in breakdown voltage. In order to overcome the above problems, an LDMOS transistor called a double reduced surface field (RESURF) structure has been developed, and the related content is referred to u s 卩舡 % 6, 〇 87, 232. Due to the lateral diffusion of the face-structure, the MOS semiconductor crystal 5 〇i61twf.doc/n 201011913 can make the deep well region where the source region and the bungee region are completely depleted during operation, so that the source region and the bungee region are between Forming a uniform electric field, the breakdown voltage of the component can be improved accordingly. Therefore, the LDM 〇s transistor of the RESURF structure has become the mainstream of the current LDMOS transistor. However, in addition to the LDM 〇s transistor of the RESURF structure, it is necessary to develop more kinds of MOSFETs to reduce the body electric field _k fidd) and the surface electric field, and to increase the breakdown voltage, so that the component has a surface electric field of a uniform sentence. Widely used laterally diffused gold-gas semiconductor components. SUMMARY OF THE INVENTION Embodiments of the present invention provide a laterally diffused MOS device and a method of fabricating the same. In accordance with an embodiment of the invention, a laterally diffused oxy-oxide semiconductor read is presented. The component includes a substrate having a first conductivity type, a deep well region of a second conductivity & a buffer region, a substrate region having a first conductivity type, a source region having a first conductivity type, and a contact having a first conductivity type a region, a conductivity-type first-hetero-depletion region, a second conductivity-type drain region, a channel region, a gate structure, and a second lightly doped region having a second conductivity type. Deep wells stand in the basement. The buffer zone is located in the deep well area. Base is located in the middle. The source region is located in the base region. The contact zone is located in the base zone. The doped zone cake is in the deep well zone. The secret zone is located in the first light-doped zone. The channel area is located in the source area and the secret area of the county. _ ^ area and partial buffer. The second lightly doped region is located in the source region and the channel 6 201011913 5i6ltwf.doc/n - in accordance with the present invention, a method of manufacturing a "hybrid body" is proposed. First, in the first lightly doped region having the first conductivity type second conductivity type. Formed with zones. Then, a first gate structure is formed in the buffer region, and a body gate region covered by the _ ς e is defined as a channel region. Then, in the base region, the shape is 1; the second light doping with the J-first conductivity type, and the second light doping after the bar, and the first and the second (four) are divided into the !==; Thereafter, a laterally diffused MOS device having the first embodiment of the present invention is formed in the substrate region, which reduces the body electric field and the surface electric field when the device is turned off, and raises the element (4) breakdown voltage. [Embodiment] ❹Transversely diffused gold gas conductor opening member Fig. 1 is a cross-sectional view and a partial top view of a laterally diffused MOS device as shown in the recording (four)-embodiment. Referring to FIG. 1, a laterally diffused MOS device includes a substrate 100 having a first conductivity type, a deep well region 2 having a second conductivity type, a gate structure 150, and a source region 142 having a second conductivity type. a drain region 144 having a second conductivity type, a contact region 146 having a first conductivity type, a lightly doped region 118 having a second conductivity type, a buffer region 124, and a substrate having a first conductivity type 7 6i61twf.doc/ n 201011913 region 134, lightly doped region 136 having a second conductivity type, and channel region 148. The first conductivity type may be a P type or an N type, and when the first conductivity type is a p type, the second conductivity type is an N type. When the first conductivity type is an N type, the second conductivity type is a P type. For convenience of explanation, the first conductivity type is denoted by P type and the second conductivity type by N type.

P型基底100可為矽基底或其他半導體基底。N型深 井區102位於P型基底1〇〇中。緩衝區位於深井區1〇2 中。P型基體區134位於緩衝區124中。N型源極區142 位於P型基體區134_。P型接觸區146位於基體區134 中。N型淡摻雜區118位於深井區102中。n型汲極區M4 位於N型淡摻雜區118中。通道區148位於源極區142與 /及極區144之間的部分基體區134中。閘極結構bo覆蓋 通道區148與部分的緩衝區124。N淡摻雜區136位於源 極區142與通道區148之間。 、' 前述之緩衝區124設置在P型基體區134與1^型深井 區102的接面之間。換言之,緩衝區124設置在n型深 區102之中,且使得p型基體區134位於其中。 緩衝區124可以是全部為無摻雜區(例如可為所謂的i 層(uayer))、P型超淡摻雜區(所·π⑹或N型超淡 區(所謂的v層)。所述的超淡摻雜區係指其摻f濃二' 型基體區m與n型深井區1〇2的摻質濃度 ^質、* 可為0至1X1017W之間。 /、穋貝辰度 前述之無摻雜區可以是該區域中的N型擦 質上恰等於P型摻質的濃度,其N型摻f#p型推質ς互 8 61twf.doc/n 201011913 補偵,而使該區域呈無摻雜。當緩衝區124為p型超淡摻 雜區時’其p型摻質濃度實質上低於p型基體區丨34的摻 質濃度。當緩衝區124為N型超淡摻雜區時,其摻質濃度 實質上低於N型深井區1〇2之摻質濃度。 月’J述緩衝區124的存在,可使得元件操作時所形成的 空乏區的寬度(通舰丨48+簡區m)寬於習知(無緩衝區 124)P型基體區134與N型深井區1〇2之間所產生的空乏The P-type substrate 100 can be a germanium substrate or other semiconductor substrate. The N-type deep well region 102 is located in the P-type substrate 1〇〇. The buffer zone is located in the depth of 1〇2. The P-type base region 134 is located in the buffer region 124. The N-type source region 142 is located in the P-type base region 134_. P-type contact region 146 is located in substrate region 134. The N-type lightly doped region 118 is located in the deep well region 102. The n-type drain region M4 is located in the N-type lightly doped region 118. Channel region 148 is located in a portion of base region 134 between source region 142 and/or pole region 144. The gate structure bo covers the channel region 148 and a portion of the buffer region 124. The N lightly doped region 136 is located between the source region 142 and the channel region 148. The aforementioned buffer zone 124 is disposed between the junction of the P-type base region 134 and the 1^-type deep well region 102. In other words, the buffer region 124 is disposed in the n-type deep region 102 with the p-type base region 134 located therein. The buffer region 124 may be all undoped regions (for example, may be so-called i-layers), P-type ultra-dilute doped regions (··π(6) or N-type ultra-dark regions (so-called v-layers). The ultra-light doped zone refers to the doping concentration of the n-type n-type matrix region m and the n-type deep well region, and the range of * can be between 0 and 1X1017W. The undoped region may be such that the N-type smear in the region is exactly equal to the concentration of the P-type dopant, and the N-type doped f#p-type ς ς ς 8 61 twf.doc/n 201011913 It is undoped. When the buffer region 124 is a p-type super-dilute doped region, its p-type dopant concentration is substantially lower than the dopant concentration of the p-type matrix region 丨34. When the buffer region 124 is N-type super-diffusion In the heterogeneous zone, the doping concentration is substantially lower than the doping concentration of 1〇2 in the N-type deep well zone. The presence of the buffer zone 124 can make the width of the depletion zone formed during the operation of the component. 48+ simple area m) wider than the conventional (no buffer 124) gap between the P-type base area 134 and the N-type deep well area 1〇2

^的寬度。如此-來,可降低表面電場與體電場,使得元 件的崩潰電壓大幅增加。 — u 疋坌邵為無摻雜區、P型超淡摻 型超淡摻雜區之外,亦可以是由無摻雜區、?型 超淡摻雜區或N型超淡摻舰組合而成的區域。 請參照圖2 ’在另-實施例中,緩衝區124是由多個p =淡摻雜區124a與多前型超歸_隱交替排列 mb 舰雜區ma與各個N魏淡摻雜區 撕之延伸方向與通道148長度L之 仃。在緩衝區124中,P型超淡摻雜區 2 區m之摻質咖型超淡摻雜區= 質辰度低於Ν型深井區102之摻質濃度。 穋 =照圖3 ’在又一實施例中:除〜 ^型超淡摻雜區_:=== 體區Hi參質濃度介於P型超淡摻雜區咖與“ 〇161twf.doc/n 201011913 圖2與圖3之實施例所示之橫向擴散金 =衝區124,除了可使元件在操作時,產生= =外’亦可透過交替設置的p型超淡摻雜區ma與N 錢淡摻純⑽使得電場的分佈更為均自。如此一來, 可使得元件的崩潰電壓大幅且均勻地增加。 請再參考圖1〜3,橫向擴散金氧半導體元件仞可 括隔離結構110a、_與11Ge,用以界定主動區。隔離 結構ll〇a覆蓋部份深井區1()2、基體區m、緩衝區124 與基底100。隔離結構!勘覆蓋部份深井區1〇2盘淡推雜 區118。隔離結構110c覆蓋部份深井區1〇2、淡推雜區⑽ 與基底卿。隔離結構11()a與隔離結構職彼此之間的 區域界定為主動區112a ;隔離結構11Gb與隔離結構聰 之間的區域界定為主動區112b。除了可界定主動區外,隔 離結構11Gb亦可減少絲㊣144料的影響,提升元件的The width of ^. In this way, the surface electric field and the electric field can be reduced, so that the breakdown voltage of the element is greatly increased. — u 疋坌 Shao is an undoped region, P-type ultra-diffused super-dilute doped region, or can be an undoped region,? A combination of ultra-light doped areas or N-type super-light-mixed ships. Referring to FIG. 2 'in another embodiment, the buffer region 124 is composed of a plurality of p = lightly doped regions 124a and a plurality of pre-type super-returns - implicitly arranged mb ship-like regions ma and respective N-wet-doped regions are torn. The direction of extension is the same as the length L of the channel 148. In the buffer region 124, the P-type super-dilute doping region 2 region m of the doped coffee type super-dilute doping region = the mass density is lower than the doping concentration of the Ν-type deep well region 102.穋 = according to Figure 3 'in another embodiment: except ~ ^ type super-dilute doped area _: === body area gin concentration is between P-type ultra-dilute doped area and " 〇161twf.doc/ n 201011913 The lateral diffusion gold = punching area 124 shown in the embodiment of FIG. 2 and FIG. 3, except that the element can be operated, the == outer ' can also pass through the alternately disposed p-type super-dilute areas ma and N. The light is purely doped (10) to make the distribution of the electric field more uniform. Thus, the breakdown voltage of the element can be greatly and uniformly increased. Referring again to FIGS. 1 to 3, the laterally diffused MOS device can include the isolation structure 110a. , _ and 11Ge, used to define the active area. The isolation structure ll 〇 a covers part of the deep well area 1 () 2, the base area m, the buffer area 124 and the substrate 100. Isolation structure! Survey part of the deep well area 1 〇 2 The dummy structure 118. The isolation structure 110c covers a part of the deep well area 1, 2, and the base area (10) and the base layer. The area between the isolation structure 11() a and the isolation structure is defined as the active area 112a; The area between the 11Gb and the isolation structure is defined as the active area 112b. In addition to the active area, the isolation structure 11Gb can also be reduced. Effect ㊣144 material, lifting element

禮盘擴量金氧丰導艚元件絮作方i 圖4A至4G是依照本發明—實施例所繪示之一種橫向 擴散金氧半導體元件的製造方法流程剖面示意圖。 请參照圖4A,在基底1〇〇中形成深井區1〇2。基底1〇〇 例如是P型基底;深井區1〇2例如是深井區。深井區 102可以藉由離子植入製程來形成之,其植入離子例如是 磷;植入劑量例如是lx10i2〜4xl〇12/cm2 ;植入能量例如是 150〜180 KeV。 接著,在基底100上形成罩幕層1〇4,裸露出預定形 6ltwf.d〇c/nFIG. 4A to FIG. 4G are schematic cross-sectional views showing a process of manufacturing a laterally diffused MOS device according to an embodiment of the present invention. Referring to FIG. 4A, a deep well region 1〇2 is formed in the substrate 1〇〇. The substrate 1〇〇 is, for example, a P-type substrate; the deep well region 1〇2 is, for example, a deep well region. The deep well region 102 can be formed by an ion implantation process, such as implanting ions such as phosphorus; the implant dose is, for example, lx10i2 to 4xl〇12/cm2; and the implantation energy is, for example, 150 to 180 KeV. Next, a mask layer 1〇4 is formed on the substrate 100 to expose a predetermined shape. 6ltwf.d〇c/n

之後,請參照圖4C,移除光阻層114。然後,形成另 -層光阻層12G,並進-步利賴影製程形成開口 122。開 口 122裸露出部分的主動區112a。然後,再進行離子植入 製程,在開口 122所裸露的主動區心中形成緩衝區 124。離子植人製程所植人之離子為p型,例如是刪;植 入能量例如是160〜200KeV。植入劑量則與緩衝區124 終的導電型有關。 當所欲形成之緩衝區124為無摻雜區,則所植入之p 型離子的劑罝必須實質上相當於N型深井區1〇2所植入之 N型離子狀齡,錢馳人的p _子恰时全補償 該處之深井區102之N型離子,以使得最終之緩衝區124 呈現無摻雜。 201011913 冓之區域。罩幕層刚例如是由墊氛化層廳盘 氮化矽層108所組成。 /、 接著’請參照圖4B,進行局部熱氧化製程,以在罩幕 層辦所裸露的區域形成隔離結構u〇a、u〇b、u〇c 後’移除罩幕層1G4,裸露出隔離結構UGa、lU)b之間的 主動區112a以及隔離結構η%、11〇c之間的主動區 ⑽。接著,形成光_ 114,並·微影製程形成開口 16’使裸露出主動區U2b。然後,再進行離子植入製程, 在開口 116所裸露的主動區112b中形成N型淡推雜區 118。離子植入製程所植入之離子例如是麟;植入劑量例如 是2x1012〜lxl〇13/cm2 ;植入能量例如是200〜250KeV。 當所欲形成之緩衝區124為p型超淡摻雜區,則所植 11 201011913 □ i61twf.doc/n 入之P型離子的劑量必須略大於深井區1〇2之劑量, 以使所植入的P型離子完全補償該處之深井區丨犯之^^型 離子,並留有少許未被補償之P型離子,以使得最線 衝區124呈現P型超淡摻雜。植入劑量例如是 2><1〇12〜8xl〇12/cm2 〇 相反地,當緩衝區124為N型超淡摻雜區,則所植入 之P型離子的劑量必須小於>1型深井區1〇2之劑量,以使 得該處深井區102中部分的\型離子被所植入的p型離子 所補償,且仍留有少許未被補償的N型離子,以使得最終 之緩衝區124呈現N型超淡摻雜。 、、 魯 若預定形成的緩衝區124是由如圖2所示之交替排列 之多個P型超淡摻雜區與多個N型超淡摻雜區所構成時, 則可以利賴似上述的方法,健過級圖案以及離子植 入條件的改變即可形成之。更具體地說,可以在基底ι〇〇 j先形成第一層光阻層(未繪示)。第一光阻層具有多個第 一開口,裸露出預定形成P型超淡摻雜區12如之區域然 $,以上述形成P型超淡摻雜區<方法’使Μ以完全^ 秘且略大於深井區1〇2iN型離子之植入劑量之ρ型離 製程來形成之。之後,將第—光阻層移除,再另 第二層光阻層(未繪示)。第二光阻層具有多個第二 口,裸露出預定形成N型超淡摻雜區124b之區域,然二 =述形成N型超淡摻雜區之方法,使用略小於且;以補 深井區搬之N型離子之植入劑量之p型離子植入 裏程來形成之。 12 «16ltwf.doc/n 201011913 - 擴散金氧半導體元件還包括第 (如圖3)時,則在移除光阻層12〇之後 後、灵形成閘介電層126之前,先形成圖案化的光阻層I 並利用微f彡製郷細口 131。接著,騎軒植入曰 於緩衝區m中形成第三超淡摻雜區125。離子植入$程 離子為p型,例如是爛;植入能量例如是12〇〜⑽ KeV,植入劑量例如是8xl〇u〜2xl〇U/cm2。之後,Thereafter, referring to FIG. 4C, the photoresist layer 114 is removed. Then, another layer of the photoresist layer 12G is formed, and the opening 122 is formed by the process. The opening 122 exposes a portion of the active area 112a. Then, an ion implantation process is performed to form a buffer 124 in the active core of the opening 122. The ion implanted in the ion implantation process is p-type, for example, deleted; the implantation energy is, for example, 160 to 200 KeV. The implant dose is related to the conductivity type of the buffer 124. When the buffer 124 to be formed is an undoped region, the implanted p-type ion must be substantially equivalent to the N-type ionic age implanted in the N-type deep well region 1,2, Qian Chiren The p _ sub-time fully compensates for the N-type ions of the deep well region 102 there, so that the final buffer 124 is undoped. 201011913 The area of 冓. The mask layer is, for example, composed of a layer of tantalum nitride 108. /, then 'please refer to FIG. 4B to perform a local thermal oxidation process to remove the mask layer 1G4 after forming the isolation structures u〇a, u〇b, u〇c in the exposed area of the mask layer. The active region 112a between the isolation structures UGA, lU)b and the active region (10) between the isolation structures η%, 11〇c. Next, light _114 is formed, and the lithography process forms an opening 16' to expose the active region U2b. Then, an ion implantation process is performed to form an N-type dimming region 118 in the active region 112b exposed by the opening 116. The ion implanted in the ion implantation process is, for example, a lin; the implantation dose is, for example, 2x1012 to lxl 〇 13/cm 2 ; and the implantation energy is, for example, 200 to 250 keV. When the buffer 124 to be formed is a p-type super-dilute doped region, the dose of the implanted P-type ions must be slightly larger than the dose of 1〇2 in the deep well region, so that the implanted The incoming P-type ions completely compensate for the ^^-type ions in the deep well area of the place, and leave a small amount of uncompensated P-type ions, so that the most line-punching area 124 exhibits P-type ultra-light doping. The implant dose is, for example, 2 <1〇12~8xl〇12/cm2 〇 Conversely, when the buffer 124 is an N-type super-dilute doped region, the dose of the implanted P-type ions must be less than >1 a dose of 1〇2 in the deep well zone such that some of the \-type ions in the deep well zone 102 are compensated by the implanted p-type ions, and still leave a small amount of uncompensated N-type ions, so that the final Buffer 124 exhibits an N-type ultra-light doping. The buffer 124 formed by Lu Ruo is formed by a plurality of P-type super-dilute doped regions and a plurality of N-type super-dilute doped regions alternately arranged as shown in FIG. 2, which may be regarded as The method, the pattern of the healthy level and the change of the ion implantation conditions can be formed. More specifically, a first photoresist layer (not shown) may be formed on the substrate ι〇〇j. The first photoresist layer has a plurality of first openings, and the exposed regions are formed to form a P-type ultra-dilute doped region 12, such as a region, to form a P-type super-dilute doped region, and the method is used to make the flaws completely And formed by a p-type separation process slightly larger than the implantation dose of the 1〇2iN type ion in the deep well area. Thereafter, the first photoresist layer is removed, and a second photoresist layer (not shown) is further removed. The second photoresist layer has a plurality of second openings exposing a region where the N-type super-dilute doping region 124b is formed, and the second method of forming the N-type super-dark doped region is used, and the method is slightly smaller than The p-type ion implantation mileage of the N-type implant implanted in the area is formed. 12 «16ltwf.doc/n 201011913 - When the diffused MOS device further includes the first (Fig. 3), after the photoresist layer 12 is removed, the patterned dielectric layer is formed before the gate dielectric layer 126 is formed. The photoresist layer I is made of micro-f彡. Next, the rider is implanted in the buffer m to form a third ultra-light doped region 125. The ion implantation ion is p-type, for example, rotten; the implantation energy is, for example, 12 〇 to (10) KeV, and the implantation dose is, for example, 8 x l 〇 u 〜 2 x l 〇 U / cm 2 . after that,

案化的光阻層127移除之。 其後’請參照圖4D ’移除光阻層12〇。然後,在基底 1〇〇之上形成閘介電層126與整層之閘極128。閘介電層 126之材質例如是氧切’形成的方法例如是熱氧化法: 閘,128之材質例如是摻雜多晶♦,形成的方法例如是化 學氣相沈積法。之後’在閘極128上形成光阻層13〇,並 利用微影製程形成開σ 132,以裸露出緩衝區m上部分 的閘極128。接著’將開口 132所裸露的閘極128以例如 姓刻製程歸,綱過財祕移除雜被移除之間極下 方的閘氧化層126。 接著,進行離子植入製程,再進行回火,以於緩衝區 124中形成P型基體區134。離子植入製程所植入之離子 為p型,例如是硼;植入能量例如是11〇〜15〇KeV;植入 劑量例如是lxlO13〜6xl〇13/em2。 之後,請參照圖4£,移除殘留的光阻層13〇,並以另 微衫與韻刻製程將整層的閘極丨28再次圖案化,以形成 閑極128。之後’以閘極mg為罩幕’進行n型離子植入 13 201011913— 製程,以在P型基體區134中形成N型淡摻雜區136。N 型離子植入製程所植入的離子例如是填或是坤;植入能量 例如是30〜60KeV ;植入劑量例如是2xl〇i2〜8xl〇i2/cm2。The patterned photoresist layer 127 is removed. Thereafter, the photoresist layer 12 is removed by referring to FIG. 4D. A gate dielectric layer 126 and a gate 128 of the entire layer are then formed over the substrate. The material of the gate dielectric layer 126 is, for example, a gas-cutting method. For example, the method of thermal oxidation: the gate, 128 is made of, for example, doped poly. The method of formation is, for example, chemical vapor deposition. Thereafter, a photoresist layer 13 is formed on the gate 128, and an opening σ 132 is formed by a lithography process to expose a portion of the gate 128 of the upper portion of the buffer m. Next, the gate 128 exposed by the opening 132 is returned by, for example, a last name, and the gate oxide layer 126 is removed from the bottom of the impurity. Next, an ion implantation process is performed, followed by tempering to form a P-type body region 134 in the buffer region 124. The ions implanted in the ion implantation process are p-type, for example, boron; the implantation energy is, for example, 11 〇 15 15 〇 KeV; and the implantation dose is, for example, lxlO13~6xl〇13/em2. Thereafter, referring to Fig. 4, the residual photoresist layer 13 is removed, and the entire gate 丨 28 is again patterned by another micro-shirt and rhyme process to form the idler 128. The n-type ion implantation 13 201011913 - process is then performed with the gate mg as a mask to form an N-type lightly doped region 136 in the P-type body region 134. The ions implanted in the N-type ion implantation process are, for example, filled or otherwise; the implantation energy is, for example, 30 to 60 KeV; and the implantation dose is, for example, 2 x 1 〇 i 2 to 8 x 1 〇 i 2 / cm 2 .

之後,請參照圖4F,在閘極128的側壁形成間隙壁 138。間隙壁138的形成方法例如是先形成一層間隙壁材料 層,然後,再進行非等向性蝕刻製程。在進行非等向性蝕 刻製程,或後續的清洗過程中,未被閘極128以及間隙壁 138所覆蓋的閘極介電層128將被移除。 然後,在基底1〇〇之上形成光阻層14〇。接著,進行 N型離子植人縣,以在p型基體區134中形成N型源極 區142,並在N型淡摻雜區118中形成N型沒極區144。 N型離子植人製程所植人的離子例如是鱗或是神;植入能 量例如是50〜65KeV ;植入劑量例如是2xl〇〗5〜5χ1〇= /cm2 。 其後,請參照圖4G ,將光阻層14〇移除,然後,於p 型基體區I34中形成P型接觸區。p型接觸區W妒 成的方法可以制—般形成摻雜區的方法,於此不再寶述二 、,在以上的實施例是以LDNM〇s來說明,然而,本^ 明亚不以此為限。本發亦可以應用於LDpM〇s中,发= 與製k方去僅需將上述導電型加以改變即可。更且 說LDmos僅需將上述⑶腿⑽中導電型為^型 雜區、淡摻雜區、超淡摻純變更為導電型為p換二 區、淡摻雜區、紐摻雜區;並將導電型為p型之換7 淡摻雜11、超歸純分別败料€縣N型^雜 14 u i61twf.doc/n 201011913 區、淡摻雜區、超淡摻雜區。Thereafter, referring to FIG. 4F, a spacer 138 is formed on the sidewall of the gate 128. The spacer 138 is formed by, for example, forming a layer of spacer material first, and then performing an anisotropic etching process. The gate dielectric layer 128 that is not covered by the gate 128 and the spacers 138 will be removed during the anisotropic etching process, or subsequent cleaning process. Then, a photoresist layer 14A is formed over the substrate 1A. Next, an N-type ion implanted county is performed to form an N-type source region 142 in the p-type base region 134, and an N-type non-polar region 144 is formed in the N-type doped region 118. The ions implanted in the N-type ion implantation process are, for example, scales or gods; the implantation energy is, for example, 50 to 65 KeV; and the implantation dose is, for example, 2 x l 〇 5 to 5 χ 1 〇 = / cm 2 . Thereafter, referring to FIG. 4G, the photoresist layer 14 is removed, and then a P-type contact region is formed in the p-type base region I34. The method of forming a p-type contact region can form a method of forming a doped region, which is not described above. In the above embodiment, LDNM〇s is used for explanation. However, this method does not This is limited. The present invention can also be applied to LDpM〇s, and it is only necessary to change the above-mentioned conductivity type. Moreover, it is said that LDmos only needs to change the conductivity type of the above (3) leg (10) into a type of impurity region, a lightly doped region, and a super-diffusion pure change to a conductivity type of p-sub-region, light-doped region, and neo-doped region; The conductivity type is p-type, 7 is lightly doped, and 11 is super-returned. The county is N-type heterogeneous 14 u i61twf.doc/n 201011913 area, lightly doped area, ultra-lightly doped area.

綜合以上所述,本發明實施例所述之橫向擴散金氧半 導體元件的製造方法簡易且可以與現有的製程整合。此 外,本發明實施例所述之橫向擴散金氧半導體元件,其在 ,作時可以同時降低體電場以及表面電場,提升崩潰電 ,。此外,本發明實施例所述之橫向擴散金氧半導體元件, 還可在操作時可以具有均勻的表面電場,使電位均勻分 布’以提升崩潰電壓。由於本發明實施綱述之橫向擴散 金氧半導體元件可錢得元件的崩潰電壓大幅增加,因 此,可以作為高壓元件。 雖然本發明已以實施例揭露如上,然其並非用以限定 =明^何熟習此技齡,在不脫離本發明之精神和範 冬田可作些权更動與潤飾’因此本發明之保護範園 虽視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 氧半^為=本發明—實施_繪示之—種橫向擴散金 導體70件的剖面與部分上視圖。 全氧:2依f本發明另一實施例所繪示之-種橫向擴散 金氧+導體辑的剖面與部分上視圖。 金氧示之-種_^ 散金種橫向機In summary, the method for fabricating the laterally diffused gold-oxygen semiconductor device according to the embodiment of the present invention is simple and can be integrated with existing processes. In addition, the laterally diffused MOS device according to the embodiment of the present invention can reduce the body electric field and the surface electric field at the same time, and improve the breakdown electric power. In addition, the laterally diffused MOS device according to the embodiment of the present invention may also have a uniform surface electric field during operation to uniformly distribute the potential to increase the breakdown voltage. Since the lateral diffusion of the laterally diffused MOS device of the present invention has a large increase in the breakdown voltage of the achievable component, it can be used as a high voltage component. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the skill of the present invention. Without departing from the spirit of the present invention, Fan Dongtian may make some changes and refinements. This is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The oxygen half is = the present invention - the implementation - the lateral cross-diffusion gold conductor 70 section and partial top view. Whole oxygen: 2 is a cross-sectional view and a partial top view of a laterally diffused gold oxide + conductor according to another embodiment of the invention. Gold Oxygen Show - Seed _^

Bi61twf.doc/n 201011913 【主要元件符號說明】 100 :基底 124b : N型超淡摻雜區 102 :深井區 126 閘介電層 104 :罩幕層 128 閘極 106 :墊氧化層 134 基體區 108 :氮化矽層 136 淡摻雜區 110a、110b、110c :隔離結構 138 間隙壁 112a、112b :主動區 142 源極區 114、127、130、140 :光阻層 144 没極區 116、122、m、132 :開口 146 接觸區 118 :淡摻雜區 150 :閘極結構 124 :缓衝區 124a、125 : P型超淡摻雜區Bi61twf.doc/n 201011913 [Description of main component symbols] 100: Substrate 124b: N-type super-dilute doping region 102: deep well region 126 Gate dielectric layer 104: mask layer 128 Gate 106: pad oxide layer 134 substrate region 108 : tantalum nitride layer 136 lightly doped regions 110a, 110b, 110c: isolation structure 138 spacers 112a, 112b: active region 142 source regions 114, 127, 130, 140: photoresist layer 144 non-polar regions 116, 122, m, 132: opening 146 contact region 118: lightly doped region 150: gate structure 124: buffer region 124a, 125: P-type super-damp-doped region

1616

Claims (1)

161twf.doc/n 201011913 申請專利範圍: 1. 一種横向擴散錢半導體元件,包括: 具有一第—導電型之-基底; 二U—v電型之—深井區,位於該基底中; 一緩衝區,位於該深井區中; 具有該第一導電型之—其辨 主又基體區,位於該緩衝區中; 具有該第二導電型之_、、β+ί:Ι_ φ ❹ 、之源極區,位於該基體區中; 具有該第一導電型之—4Λ Ag r- 接觸區’位於該基體區中; 具有該第二導電型之—筮 r- 中 又第一淡摻雜區位於該深井區 區中 具有該第二導電型之—祕區,位於該第-淡摻雜 9 基體區一中通道區’赌卿、極區與紐㈣1的部分該 -閘極結構’覆蓋該通道區與部份職衝區;以及 具有該第二導電型之—第二淡摻雜區 區與該通道區<間。 2· 專纖圍第丨韻述之橫向錄金氧半 體元件,其中該緩衝區為無摻雜區。 3. 如申請專利範圍第i項所述之橫向擴散 體元件,其巾魏_為具有該第—導電型之 摻雜區,其掺質濃度低於該基體區之摻質濃度。 /犬 4. *巾請專概圍第丨項所述之橫向擴散金氧 體7L件,其中該緩衝區為具有該第二導電型之一 乐一超淡 17 -»161twf.doc/n 201011913 摻雜區’其摻質濃度低於該深井區之摻質濃度。 5.如申叫專利範圍弟1項所述之橫向擴散金氧半 體元件,其中該缓衝區由具有該第一導電型之複數個第一 ,淡摻雜區與具有該第二導電型之複數個第二超淡推雜區 交替排列而成’該些第-超淡摻雜區與該些第二超淡 區的延伸方向與該通道之長度的延伸方向實質上平行。" m ―6·如申請專利範圍第5項所述之橫向擴散金氧 體兀件’其中該些第一超淡摻雜區之換質濃度低於該 區之摻質濃度’·該些第二超淡摻雜區之摻質濃度低於 井區之摻質濃度。 _ 冰 7· % f請專魏圍第6項所述之橫向擴散金 更包括具有第-導電型之-第三超淡摻雜區: 於該基體區與該緩衝區之間。 位 8.如申請專利範圍第7項所述之橫向 體,,其中該第三超淡摻雜區的摻質濃度介 从雜區的摻質濃度與該基體區的摻質濃度之間。弟超 辦元^巾料職目帛1項所狀辦触金氧半導 導電縣該第二導電型為n型。 ^^職财1項所叙制金氧半導 u:二直一導電型為該第二導電型為p型 體元件,更包括= 構第=之橫向擴散物^ 一第-部份,覆蓋部分該深井區 部分該基醜上;以及 I ”錢及 18 »i61twf.doc/n 201011913 不一部仍、,那接該汲核 井區與部分該第—淡摻雜區。°°側’錢蓋部分該深 12.如申請專利範圍第 導體元件,其中該隔離結 、所述之橫向擴散金氧半 =:源極區之間’覆 淡摻雜區上。 I刀该冰开k以及部分該第 _ 體元件,二項所述之橫向擴散金氧半導 賴與該深井===_介於該雜區之 體元件,專概圍第1項所述之獅擴散金氧半導 度。?該基體區之摻㈣度低於該源極區之摻質濃 括:5’種橫向擴散金氧半導體元件的製造方法,包 雜區; 電型井—區第一導電型之一基底中形成具有一第二導 ;於該深井區中形成具有該第二導電型之-第-淡摻 於該深井區中形成-緩衝區; 緩衝區中形成具有該第一導電型之一基體區; 部分該基體區與該緩衝區上形成一閘極結構,該 閘極結構所覆蓋之縣醜定㈣4道區; · 雜區,1該基體區中形成具有該第二導電型之一第二淡摻 '、°°,/、中該第二淡摻雜區鄰接該通道區; 19 201011913。 I61twf.doc/n 於該基體區錢苐—淡摻雜區中分別形 二導電型之-源極區與一汲極區;以及 、有該第 於該基體區中形成具有該第—導電型之 請專利範圍第15項所述之橫 1體=件的製造方法,其中該井區與該緩衝區氧半 第一離子植入製程與—第二離子植入製程製成:、,以— 17. 如申請專利範圍第16項所 φ 導體元件的製造方法,Α巾 、 ” °擴政金氧半 第-導電型之離子,其劑=二離=製程植入具有 製程所植入之具有該第-導雷刑相田於5亥第一離子植入 該緩衝區呈無摻ί 電型之離子的劑量’使最終之 18. 如申請專利範圍第 導體元件的製造方法,其中讀第金, 程所植入之具有該第二導電裂 子植入製 魯 ΐι導電型之離子’其劑量實質上入具有 ,使 區之摻質濃度。 …ζπ Μ度低於該基體 ΐ一2型之該緩衝區,該緩衝區的摻質濃度低,、該 導體範圍第16項所述之橫向擴散金氧半 魏法’其中糾—離子植人製程植入具有 程所植入之具有該第—1第二離子植入製 一道 導電I之離子的劑量,使形成具第 該緩衝區,區之摻質濃度低於該深井區 20161twf.doc/n 201011913 Patent Application Range: 1. A laterally diffused money semiconductor component comprising: a substrate having a first conductivity type; a deep well region of a second U-v type, located in the substrate; , in the deep well region; having the first conductivity type - the main and base regions are located in the buffer; having the second conductivity type _,, β + ί: Ι _ φ ❹, the source region Located in the base region; a 4 Λ Ag r-contact region having the first conductivity type is located in the base region; and a first lightly doped region having the second conductivity type 筮r- is located in the deep well The region has the second conductivity type-secret region, and is located in the first-light doped 9-base region, the middle channel region, the portion of the gambling, the polar region, and the new (four) 1 - the gate structure covers the channel region and the portion a job area; and a second lightly doped region having the second conductivity type and the channel region < 2· The special recording of the 丨 围 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向 横向3. The lateral diffuser element according to claim i, wherein the towel is a doped region having the first conductivity type, and the dopant concentration is lower than the dopant concentration of the substrate region. / Canine 4. * Towels please refer to the lateral diffusion gold oxide 7L piece mentioned in the third item, wherein the buffer zone has one of the second conductivity types, Le Yi Chao 17 -»161twf.doc/n 201011913 The doped region has a dopant concentration lower than the dopant concentration of the deep well region. 5. The laterally diffused oxy-half half element of claim 1, wherein the buffer zone comprises a plurality of first, lightly doped regions having the first conductivity type and having the second conductivity type The plurality of second ultra-light doped regions are alternately arranged to form a direction in which the first-super-dilute doped regions and the second ultra-dark regions extend substantially parallel to the extending direction of the length of the channel. " m ―6· as disclosed in claim 5, the laterally diffused gold oxide element 'where the first ultra-light doped region has a higher concentration of the dopant than the dopant concentration of the region' The dopant concentration of the second ultra-light doped region is lower than the dopant concentration of the well region. _ Ice 7· % f Please use the lateral diffusion gold described in item 6 of Weiwei to include a third-lightly doped region having a first conductivity type: between the substrate region and the buffer zone. 8. The lateral body of claim 7, wherein the dopant concentration of the third ultra-light doped region is between the dopant concentration of the hetero region and the dopant concentration of the substrate region. The younger than the yuan ^ towel material job 帛 1 item of the touch of gold and oxygen semi-conducting conductive county, the second conductivity type is n-type. ^^Occupation of gold oxide semi-conducting u: The two-conductor type is the p-type body element of the second conductivity type, and further includes the lateral diffusion material of the = structure = a first part, covering Part of the deep well area is partly ugly; and I "money and 18 »i61twf.doc/n 201011913 are not one, still connected to the 汲 nuclear well area and part of the first - lightly doped area. ° ° side' The cover portion is deep 12. As claimed in the patent scope, the conductor member, wherein the isolation junction, the lateral diffusion of the gold oxide half =: between the source regions is overlying the doped region. Part of the _ body element, the lateral diffusion MOS and the deep well === _ between the body elements of the miscellaneous area, the lion diffusion metal oxy-transductor described in the first item The doping of the base region is lower than the dopant of the source region: a manufacturing method of 5' laterally diffused MOS devices, a inclusion region; and one of the first conductivity types of the electric well region Forming a second guide in the base; forming a buffer-forming medium in the deep well region having the second conductivity type formed in the deep well region; a base region having the first conductivity type is formed in the punching zone; a portion of the base region and the buffer region form a gate structure, and the gate covered by the gate structure is a quaint (four) 4 channel region; · a miscellaneous region, 1 Forming, in the base region, a second light doping of the second conductivity type, °°, /, wherein the second lightly doped region is adjacent to the channel region; 19 201011913. I61twf.doc/n in the base region a light-doped region in which a source-dipole region and a drain region are respectively formed; and wherein the layer is formed in the substrate region and has a cross-section as described in claim 15 of the first conductivity type 1 body=piece manufacturing method, wherein the well region and the buffer oxygen half first ion implantation process and the second ion implantation process are made:, to - 17. as claimed in claim 16 The manufacturing method of the conductor element, the towel, the "degree expansion of the gold oxide semi-conducting type ion, the agent = two-off = the process implant has the process implanted with the first-guided Lei Xiang Xiang Tian in 5 Haidi An ion implanted in the buffer is a dose that is free of ionic ions, making the final 18. If applying for a patent A method of fabricating a range of conductor elements, wherein the reading of the gold, the ion implanted with the second conductive fission implanted in the conductive type is substantially inclusive of the dopant concentration of the region. ... ζ π Μ is lower than the buffer of the base ΐ 2 2, the buffer has a low dopant concentration, and the transverse diffusion oxy-semi-wei method described in item 16 of the conductor range The process implant has a dose implanted with the first ion implanted with the first ion implanted to form a first buffer zone, and the dopant concentration of the region is lower than the deep well region 20
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