CN101661955B - Transverse diffusion metal oxide semiconductor device and manufacturing method thereof - Google Patents
Transverse diffusion metal oxide semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN101661955B CN101661955B CN200810214469XA CN200810214469A CN101661955B CN 101661955 B CN101661955 B CN 101661955B CN 200810214469X A CN200810214469X A CN 200810214469XA CN 200810214469 A CN200810214469 A CN 200810214469A CN 101661955 B CN101661955 B CN 101661955B
- Authority
- CN
- China
- Prior art keywords
- conductivity type
- area
- light doped
- dopant concentration
- doped region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a transverse diffusion metal oxide semiconductor device and a manufacturing method thereof. The device comprises a substrate with a first conduction type, a deep trap with a second conduction type, a buffering area, a base body area with the first conduction type, a source electrode area with the second conduction type, a contact area with the first conduction type, a first nitrogen doping area with the second conduction type, a drain electrode area with the second conduction area, a channel area, a grid structure and a second nitrogen doping area with the second conduction type, wherein the deep trap is positioned in the substrate; the buffering area is positioned in the deep trap; the base body area is positioned in the buffering area; the source electrode area and the contact area are positioned in the base body area; the first nitrogen doping area is positioned in the deep trap; the drain electrode area is positioned in the first nitrogen doping area; the channel area is positioned in a part of the base body area between the source electrode area and the drain electrode area; the grid structure is used for covering the channel area and a part of the buffering area; and the second nitrogen doping area is positioned between the source electrode area and the channel area. When the device is operated, a body electric field and a surface electric field are reduced and the breakdown voltage of the device is enhanced.
Description
Technical field
The invention relates to a kind of semiconductor device, and particularly about a kind of transverse diffusion metal oxide semiconductor device and manufacture method thereof.
Background technology
Laterally Diffused Metal Oxide Semiconductor (lateral diffused metal oxide semiconductor; LDMOS) transistor has high-breakdown-voltage (breakdown voltage) and low opening resistor (on-state resistance when operation; Ron).Therefore, no matter be on typical power IC, or on the intelligent electric power integrated circuit, ldmos transistor is all being played the part of very important role.
Early stage ldmos transistor because the high electric field of its drain electrode end and high drain current can form and morely have more high-octane hot electron and remove to puncture gate dielectric layer, often causes the impairment of transistor life.For promoting the transistorized life-span, between drain electrode and grid, can form field oxide usually, to reduce electric field effects.Yet the formation of field oxide but can cause opening resistor to increase, and causes saturation current to descend.Though the dopant concentration that increases the drift region between drain region and the channel region can reduce the opening resistor of device, can make that but the drift region can't exhaust fully, and causes puncture voltage to descend.
For overcoming the problems referred to above, thus develop a kind of claimed be dual minimizing surface field (doubleReduced Surface Field; RESURF) ldmos transistor of structure, its related content please refer to U.S.Pat.No.6, and 087,232.Because the LDMOS transistor of RESURF structure can be so that the deep trap at source area and place, drain region exhausts fully when operation, make and form uniform electric field between source area and the drain region, therefore the puncture voltage of device can promote, so the ldmos transistor of RESURF structure has become the main flow of present ldmos transistor.
Yet, except the ldmos transistor of RESURF structure, also need develop at present and more kinds ofly can reduce bulk electric field (Bulk field) and surface field simultaneously, promote puncture voltage, make device have uniform surface field, with the transverse diffusion metal oxide semiconductor device that is widely used.
Summary of the invention
The embodiment of the invention provides the manufacture method of a kind of transverse diffusion metal oxide semiconductor device and this device.
According to one embodiment of the invention, a kind of transverse diffusion metal oxide semiconductor device is proposed.This device comprises the substrate with first conductivity type, the deep trap with second conductivity type, buffering area, have the matrix area of first conductivity type, have second conductivity type source area, have the contact zone of first conductivity type, the second light doped region that has the first light doped region of second conductivity type, drain region, channel region, grid structure and have second conductivity type with second conductivity type.Deep trap is arranged in substrate.Buffering area is arranged in deep trap.Matrix area is arranged in buffering area.Source area is arranged in matrix area.The contact zone is arranged in matrix area.The first light doped region is arranged in deep trap.The drain region is arranged in the first light doped region.In the part matrix area of channel region between source area and drain region.Grid structure covers channel region and part buffering area.The second light doped region is between source area and channel region.
According to another embodiment of the present invention, a kind of manufacture method of transverse diffusion metal oxide semiconductor device is proposed.At first, in substrate, form deep trap with second conductivity type with first conductivity type.Then, in deep trap, form the first light doped region with second conductivity type.Afterwards, in deep trap, form buffering area.Continue it, in buffering area, form matrix area with first conductivity type.Thereafter, form grid structure on part matrix area and buffering area, the matrix area that grid structure covered is defined as channel region.Then, form the second light doped region with second conductivity type in matrix area, the second light doped region is in abutting connection with channel region.Afterwards, in the matrix area and the first light doped region, form source area and drain region respectively with described second conductivity type.In matrix area in form contact zone with first conductivity type thereafter.
The described transverse diffusion metal oxide semiconductor device of the embodiment of the invention, it can reduce bulk electric field and surface field, the puncture voltage of boost device simultaneously when operation.
Description of drawings
Fig. 1 is section and part vertical view according to a kind of transverse diffusion metal oxide semiconductor device that one embodiment of the invention illustrated.
Fig. 2 is section and part vertical view according to a kind of transverse diffusion metal oxide semiconductor device that another embodiment of the present invention illustrated.
Fig. 3 is section and part vertical view according to a kind of transverse diffusion metal oxide semiconductor device that further embodiment of this invention illustrated.
Fig. 4 A to 4G is the manufacture method flow process generalized section of a kind of transverse diffusion metal oxide semiconductor device of illustrating according to the embodiment of the invention.
Drawing reference numeral
100: the super light doped region of substrate 124b:N type
102: deep trap 126: gate dielectric layer
104: mask layer 128: grid
106: pad oxide 134: matrix area
108: silicon nitride layer 136: light doped region
110a, 110b, 110c: isolation structure 138: clearance wall
112a, 112b: active region 142: source area
114,127,130,140: photoresist 144: drain region
Layer 146: contact zone
116,122,131,132: opening 148: channel region
118: light doped region 150: grid structure
124: buffering area
124a, the super light doped region of 125:P type
Embodiment
Transverse diffusion metal oxide semiconductor device
Fig. 1 is profile and part vertical view according to a kind of transverse diffusion metal oxide semiconductor device that one embodiment of the invention illustrated.
Please refer to Fig. 1, transverse diffusion metal oxide semiconductor device 10 comprises the substrate 100 with first conductivity type, the deep trap 102 with second conductivity type, grid structure 150, has the source area 142 of second conductivity type, has the drain region 144 of second conductivity type, the contact zone 146 with first conductivity type, the light doped region 118 with second conductivity type, buffering area 124, the matrix area 134 with first conductivity type, the light doped region 136 with second conductivity type and channel region 148.First conductivity type can be P type or N type, and when first conductivity type was the P type, second conductivity type was the N type.When first conductivity type was the N type, second conductivity type was the P type.For convenience of description, below represent first conductivity type, represent second conductivity type with the N type with the P type.
Described buffering area 124 is arranged between the knot of P mold base district 134 and N moldeed depth trap 102.In other words, buffering area 124 is arranged among the N moldeed depth trap 102, and makes P mold base district 134 be positioned at wherein.
Described undoped region can be the concentration that the concentration of the N type admixture in the described zone in fact just equals P type admixture, and its N type admixture and P type admixture compensate mutually, and make described zone be non-impurity-doped.When buffering area 124 was the super light doped region of P type, its P type dopant concentration was lower than the dopant concentration in P mold base district 134 in fact.When buffering area 124 was the super light doped region of N type, its dopant concentration was lower than the dopant concentration of N moldeed depth trap 102 in fact.
The existence of described buffering area 124, the width of formed depletion region in the time of can making device operation (channel region 148+ buffering area 124) is wider than the width of the depletion region that is produced between known (no-buffer 124) P mold base district 134 and the N moldeed depth trap 102.Thus, can reduce surface field and bulk electric field, make the puncture voltage of device significantly increase.
Please refer to Fig. 2, in another embodiment, buffering area 124 is alternately to be arranged by super light doped region 124a of a plurality of P types and the super light doped region 124b of a plurality of N type to form.The super light doped region 124a of each P type is parallel in fact with the bearing of trend of raceway groove 148 length L with the bearing of trend of the super light doped region 124b of each N type.In buffering area 124, the dopant concentration of the super light doped region 124a of P type is lower than the dopant concentration in P mold base district 134; The dopant concentration of the super light doped region 124b of N type is lower than the dopant concentration of N moldeed depth trap 102.
Please refer to Fig. 3, in another embodiment, except buffering area 124, transverse diffusion metal oxide semiconductor device 10 can more comprise the super light doped region 125 of P type.The super light doped region 125 of P type is disposed between P mold base district 134 and the buffering area 124, and its dopant concentration is between super light doped region 124a of P type and P mold base district 134.
The buffering area 124 of the transverse diffusion metal oxide semiconductor device 10 shown in the embodiment of Fig. 2 and Fig. 3, except making device when operating, produce outside the depletion region of broad, also can be by the P type that is arranged alternately super light doped region 124a and the super light doped region 124b of N type make that the distribution of electric field is more even.Thus, can make the puncture voltage of device significantly and equably increase.
Refer again to Fig. 1～3, transverse diffusion metal oxide semiconductor device 10 can more comprise isolation structure 110a, 110b and 110c, in order to define active region.Isolation structure 110a covers partly deep trap 102, matrix area 134, buffering area 124 and substrate 100.Isolation structure 110b covers partly deep trap 102 and light doped region 118.Isolation structure 110c covers partly deep trap 102, light doped region 118 and substrate 100.Isolation structure 110a and isolation structure 110b region deviding each other are active region 112a; Region deviding between isolation structure 110b and the isolation structure 110c is active region 112b.Except defining the active region, isolation structure 110b also can reduce drain region 144 electric field effects, the useful life of boost device.
The transverse diffusion metal oxide semiconductor device manufacture method
Fig. 4 A to 4G is the manufacture method flow process generalized section of a kind of transverse diffusion metal oxide semiconductor device of illustrating according to one embodiment of the invention.
Please refer to Fig. 4 A, in substrate 100, form deep trap 102.Substrate 100 for example is a P type substrate; Deep trap 102 for example is a N moldeed depth trap.Deep trap 102 can form by ion implantation technology, and it injects ion for example is phosphorus; Implantation dosage for example is 1 * 10
12～4 * 10
12/ cm2; Injecting energy for example is 150～180KeV.
Then, on substrate 100, form mask layer 104, expose the predetermined zone that forms isolation structure.Mask layer 104 for example is made up of pad oxide 106 and silicon nitride layer 108.
Then, please refer to Fig. 4 B, carry out partial thermal oxidation technology, to form isolation structure 110a, 110b, 110c in 104 exposed regions of mask layer.Afterwards, remove mask layer 104, expose active region 112a between isolation structure 110a, the 110b and the active region 112b between isolation structure 110b, the 110c.Then, form photoresist layer 114, and utilize photoetching process to form opening 116, make to expose active region 112b.Then, carry out ion implantation technology again, in the active region 112b that opening 116 is exposed, form the light doped region 118 of N type.The ion that ion implantation technology is injected for example is a phosphorus; Implantation dosage for example is 2 * 10
12～1 * 10
13/ cm2; Injecting energy for example is 200～250KeV.
Afterwards, please refer to Fig. 4 C, remove photoresist layer 114.Then, form another layer photoetching glue-line 120, and further utilize photoetching process to form opening 122.Opening 122 exposes the active region 112a of part.Then, carry out ion implantation technology again, in the active region 112a that opening 122 is exposed, form buffering area 124.The ion that ion implantation technology is injected is the P type, for example is boron; Injecting energy for example is 160～200KeV.Implantation dosage is then relevant with the final conductivity type of buffering area 124.
The buffering area 124 that forms when institute's desire is a undoped region, the dosage of the P type ion that is then injected must be equivalent in fact N type ion that N moldeed depth trap 102 injected dosage, so that the N type ion of the deep trap 102 at the described place of being injected of the lucky full remuneration of P type ion, so that final buffering area 124 presents non-impurity-doped.
The buffering area 124 that forms when institute's desire is the super light doped region of P type, the dosage of the P type ion that is then injected must be slightly larger than the dosage of N moldeed depth trap 102, so that the N type ion of the deep trap 102 at the described place of being injected of P type ion full remuneration, and leave the P type ion that a little is not compensated, so that final buffering area 124 presents the super light doping of P type.Implantation dosage for example is 2 * 10
12～8 * 10
12/ cm
2
On the contrary, when buffering area 124 is the super light doped region of N type, the dosage of the P type ion that is then injected must be less than the dosage of N moldeed depth trap 102, so that the N type ion of part is compensated by the P that is injected type ion in the described place deep trap 102, and still leave the N type ion that a little is not compensated, so that final buffering area 124 presents the super light doping of N type.
If the predetermined buffering area 124 that forms is when being made of as shown in Figure 2 super light doped region of alternately arranging of a plurality of P types and the super light doped region of a plurality of N types, then can utilize similar above-mentioned method, only the change by photoresist pattern and ion implanting conditions can form.More particularly, can on substrate 100, form ground floor photoresist layer (not illustrating) earlier.First photoresist layer has a plurality of first openings, expose the predetermined zone that forms the super light doped region 124a of P type, then, with the method for the super light doped region of above-mentioned formation P type, use the P type ion implantation technology of implantation dosage be enough to full remuneration and be slightly larger than the N type ion of deep trap 102 to form.Afterwards, first photoresist layer is removed, form second layer photoresist layer (not illustrating) more in addition.Second photoresist layer has a plurality of second openings, expose the predetermined zone that forms the super light doped region 124b of N type, then, with the method for the super light doped region of above-mentioned formation N type, use the P type ion implantation technology of the implantation dosage of the N type ion be slightly less than and can compensated part deep trap 102 to form.
Please refer to Fig. 4 C-1, when transverse diffusion metal oxide semiconductor device also comprises three super light doped region 125 (as Fig. 3), then after removing photoresist layer 120, before the follow-up formation gate dielectric layer 126, form the photoresist layer 127 of patterning earlier, and utilize photoetching process to form opening 131.Then, carry out ion implantation technology, in buffering area 124, form three super light doped region 125.The ion that ion implantation technology is injected is the P type, for example is boron; Injecting energy for example is 120～160KeV; Implantation dosage for example is 8 * 10
12～2 * 10
13/ cm2.Afterwards, again the photoresist layer 127 of patterning is removed.
, please refer to Fig. 4 D, remove photoresist layer 120 thereafter.Then, on substrate 100, form the grid 128 of gate dielectric layer 126 and whole layer.The material of gate dielectric layer 126 for example is a silica, and the method for formation for example is a thermal oxidation method.The material of grid 128 for example is a doped polycrystalline silicon, and the method for formation for example is a chemical vapor deposition method.Afterwards, on grid 128, form photoresist layer 130, and utilize photoetching process to form opening 132, to expose the grid 128 on buffering area 124 tops.Then, the grid 128 that opening 132 is exposed removes with for example etching technics, also will remove the gate oxide 126 of the grid below that partly is removed in the etching process.
Then, carry out ion implantation technology, anneal again, in buffering area 124, to form P mold base district 134.The ion that ion implantation technology is injected is the P type, for example is boron; Injecting energy for example is 110～150KeV; Implantation dosage for example is 1 * 10
13～6 * 10
13/ cm2.
Afterwards, please refer to Fig. 4 E, remove residual photoresist layer 130, and with another photoetching and etching technics with the grid 128 of whole layer patterning once more, to form grid 128.Afterwards, be mask with grid 128, carry out N type ion implantation technology, in P mold base district 134, to form the light doped region 136 of N type.The ion that N type ion implantation technology is injected for example is phosphorus or arsenic; Injecting energy for example is 30～60KeV; Implantation dosage for example is 2 * 10
12～8 * 10
12/ cm2.
Afterwards, please refer to Fig. 4 F, at the sidewall formation clearance wall 138 of grid 128.The formation method of clearance wall 138 for example is to form one deck spacer material layer earlier, then, carries out anisotropic etch process again.Carrying out anisotropic etch process, or in the follow-up cleaning process, the gate dielectric 128 that is covered by grid 128 and clearance wall 138 will not be removed.
Then, on substrate 100, form photoresist layer 140.Then, carry out N type ion implantation technology,, and in the light doped region 118 of N type, form N type drain region 144 with formation N type source area 142 in P mold base district 134.The ion that N type ion implantation technology is injected for example is phosphorus or arsenic; Injecting energy for example is 50～65KeV; Implantation dosage for example is 2 * 10
15～5 * 10
15/ cm
2
, please refer to Fig. 4 G, photoresist layer 140 is removed, then, in P mold base district 134, form P type contact zone 146 thereafter.The method that P type contact zone 146 forms can adopt the method for general formation doped region, repeats no more in this.
Illustrate with LDNMOS at above embodiment, yet the present invention is not as limit.This can also be applied among the LDPMOS, and its structure and manufacture method only need above-mentioned conductivity type change is got final product.More particularly, only to need conductivity type among the above-mentioned LDNMOS be that the doped region of N type, light doped region, super light doped region change to the doped region that conductivity type is the P type, light doped region, super light doped region to LDPMOS; And be that the doped region of P type, light doped region, super light doped region change to the doped region that conductivity type is the N type, light doped region, super light doped region respectively with conductivity type.
Comprehensive the above, the manufacture method of the described transverse diffusion metal oxide semiconductor device of the embodiment of the invention is simple and easy and can integrate with existing processes.In addition, the described transverse diffusion metal oxide semiconductor device of the embodiment of the invention, it can reduce bulk electric field and surface field simultaneously when operation, promote puncture voltage.In addition, the described transverse diffusion metal oxide semiconductor device of the embodiment of the invention also can have uniform surface field when operation, current potential is evenly distributed, to promote puncture voltage.Because therefore the transverse diffusion metal oxide semiconductor device of the embodiment of the invention can, can be used as high tension apparatus so that the puncture voltage of device significantly increases.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any art technology, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion with claim institute confining spectrum.
Claims (11)
1. a transverse diffusion metal oxide semiconductor device is characterized in that, described transverse diffusion metal oxide semiconductor device comprises:
Substrate with one first conductivity type;
Have a deep trap of one second conductivity type, be arranged in described substrate;
One buffering area is arranged in described deep trap;
Have a matrix area of described first conductivity type, be arranged in described buffering area;
Have the one source pole district of described second conductivity type, be arranged in described matrix area;
Have a contact zone of described first conductivity type, be arranged in described matrix area;
One first light doped region with described second conductivity type is arranged in described deep trap;
Drain region with described second conductivity type is arranged in the described first light doped region;
One channel region is in the described matrix area of part between described source area and described drain region;
One grid structure covers described channel region and the described buffering area of part; And
One second light doped region with described second conductivity type is between described source area and described channel region;
Wherein, described buffering area is a undoped region; Perhaps described buffering area is the first super light doped region with described first conductivity type, and its dopant concentration is lower than the dopant concentration of described matrix area; Perhaps described buffering area is the second super light doped region with described second conductivity type, and its dopant concentration is lower than the dopant concentration of described deep trap; Perhaps described buffering area is alternately arranged with a plurality of the second super light doped region with described second conductivity type by a plurality of the first super light doped region with described first conductivity type and is formed, described these the first super light doped regions are parallel with the bearing of trend of the length of described raceway groove with the bearing of trend of described these the second super light doped regions, the dopant concentration of described these the first super light doped regions is lower than the dopant concentration of described matrix area, and the dopant concentration of described these the second super light doped regions is lower than the dopant concentration of described deep trap.
2. transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterized in that, described transverse diffusion metal oxide semiconductor device further comprises the three super light doped region with first conductivity type, between described matrix area and described buffering area, described three the dopant concentration of super light doped region between the dopant concentration of the dopant concentration of described the first super light doped region and described matrix area.
3. transverse diffusion metal oxide semiconductor device as claimed in claim 1 is characterized in that, when described first conductivity type was the P type, described second conductivity type was the N type, and when described first conductivity type was the N type, described second conductivity type was the P type.
4. transverse diffusion metal oxide semiconductor device as claimed in claim 1 is characterized in that described transverse diffusion metal oxide semiconductor device further comprises an isolation structure, and described isolation structure comprises:
One first is on the described deep trap in cover part, the described buffering area of part and the described matrix area of part; And
One second portion, in abutting connection with a side of described drain region, and described deep trap in cover part and the part described first light doped region.
5. transverse diffusion metal oxide semiconductor device as claimed in claim 4, it is characterized in that, described isolation structure more comprises a third part, between described drain region and described source area, is covered on described deep trap of part and the part described first light doped region.
6. transverse diffusion metal oxide semiconductor device as claimed in claim 1 is characterized in that, the dopant concentration of the described first light doped region is between the dopant concentration of the dopant concentration of described drain region and described deep trap.
7. the manufacture method of a transverse diffusion metal oxide semiconductor device is characterized in that, the manufacture method of described transverse diffusion metal oxide semiconductor device comprises:
In a substrate, form a deep trap with one second conductivity type with one first conductivity type;
In described deep trap, form one first light doped region with described second conductivity type;
In described deep trap, form a buffering area;
In described buffering area, form a matrix area with described first conductivity type;
Form a grid structure on described matrix area of part and described buffering area, the described matrix area that described grid structure covered is defined as a channel region;
Form one second light doped region with described second conductivity type in described matrix area, the wherein said second light doped region is in abutting connection with described channel region;
In the described matrix area and the described first light doped region, form an one source pole district and a drain region respectively with described second conductivity type; And
In described matrix area, form a contact zone with described first conductivity type;
Wherein, described buffering area is a undoped region; Perhaps described buffering area is the first super light doped region with described first conductivity type, and its dopant concentration is lower than the dopant concentration of described matrix area; Perhaps described buffering area is the second super light doped region with described second conductivity type, and its dopant concentration is lower than the dopant concentration of described deep trap; Perhaps described buffering area is alternately arranged with a plurality of the second super light doped region with described second conductivity type by a plurality of the first super light doped region with described first conductivity type and is formed, described these the first super light doped regions are parallel with the bearing of trend of the length of described raceway groove with the bearing of trend of described these the second super light doped regions, the dopant concentration of described these the first super light doped regions is lower than the dopant concentration of described matrix area, and the dopant concentration of described these the second super light doped regions is lower than the dopant concentration of described deep trap.
8. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 7 is characterized in that, described deep trap and described buffering area are to make with one first ion implantation technology and one second ion implantation technology respectively.
9. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 8, it is characterized in that, described second ion implantation technology is injected the ion with first conductivity type, its dosage is equivalent to the dosage of the ion with described second conductivity type that described first ion implantation technology injects, and makes final described buffering area be non-impurity-doped.
10. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 8, it is characterized in that, described second ion implantation technology is injected the ion with first conductivity type, the dosage of the ion that its dosage injects greater than described first ion implantation technology with described second conductivity type, make the described buffering area that forms described first conductivity type of tool, the dopant concentration of described buffering area is lower than the dopant concentration of described matrix area.
11. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 8, it is characterized in that, described first ion implantation technology is injected the ion with second conductivity type, the dosage of the ion that its dosage injects less than described second ion implantation technology with described first conductivity type, make the described buffering area that forms tool second conductivity type, the dopant concentration of described buffering area is lower than the dopant concentration of described deep trap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810214469XA CN101661955B (en) | 2008-08-28 | 2008-08-28 | Transverse diffusion metal oxide semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810214469XA CN101661955B (en) | 2008-08-28 | 2008-08-28 | Transverse diffusion metal oxide semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101661955A CN101661955A (en) | 2010-03-03 |
| CN101661955B true CN101661955B (en) | 2011-06-01 |
Family
ID=41789854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810214469XA Active CN101661955B (en) | 2008-08-28 | 2008-08-28 | Transverse diffusion metal oxide semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101661955B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943665A (en) * | 2013-01-18 | 2014-07-23 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method and operation method thereof |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769028B (en) * | 2011-05-03 | 2015-01-28 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN104835842A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Ldmos device |
| US20160056285A1 (en) * | 2014-08-25 | 2016-02-25 | Mediatek Inc. | High-voltage metal-oxide-semiconductor transistor device with increased cutoff frequency |
| CN104835837B (en) * | 2015-06-05 | 2017-07-28 | 杭州士兰微电子股份有限公司 | High-voltage semi-conductor device and its manufacture method |
| CN106257646B (en) * | 2015-06-17 | 2019-06-14 | 北大方正集团有限公司 | It is embedded in the CMOS production method of PIP capacitor |
| CN110634949B (en) * | 2018-06-22 | 2023-03-28 | 立锜科技股份有限公司 | High voltage device and method for manufacturing the same |
| CN109830538B (en) * | 2019-01-22 | 2022-08-16 | 上海华虹宏力半导体制造有限公司 | LDMOS device and manufacturing method thereof |
| CN114050181B (en) * | 2022-01-07 | 2022-03-22 | 北京芯可鉴科技有限公司 | NLDMOS device, preparation method and chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030141559A1 (en) * | 2001-12-20 | 2003-07-31 | Stmicroelectronics S.R.I. | Metal oxide semiconductor field-effect transistor and associated methods |
| CN1487595A (en) * | 2002-09-30 | 2004-04-07 | 东南大学 | High-voltage N-type transversely double-diffusion metal oxide semiconductor transistor |
| US20040222488A1 (en) * | 2003-05-06 | 2004-11-11 | International Business Machines Corporation | High voltage n-ldmos transistors having shallow trench isolation region |
-
2008
- 2008-08-28 CN CN200810214469XA patent/CN101661955B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030141559A1 (en) * | 2001-12-20 | 2003-07-31 | Stmicroelectronics S.R.I. | Metal oxide semiconductor field-effect transistor and associated methods |
| CN1487595A (en) * | 2002-09-30 | 2004-04-07 | 东南大学 | High-voltage N-type transversely double-diffusion metal oxide semiconductor transistor |
| US20040222488A1 (en) * | 2003-05-06 | 2004-11-11 | International Business Machines Corporation | High voltage n-ldmos transistors having shallow trench isolation region |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平9-139438A 1997.05.27 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943665A (en) * | 2013-01-18 | 2014-07-23 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method and operation method thereof |
| CN103943665B (en) * | 2013-01-18 | 2016-08-24 | 旺宏电子股份有限公司 | Semiconductor device and manufacture method thereof and method of operating |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101661955A (en) | 2010-03-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101661955B (en) | Transverse diffusion metal oxide semiconductor device and manufacturing method thereof | |
| KR101145558B1 (en) | Asymmetric hetero?doped high?voltage mosfet?ah2mos | |
| US8158475B2 (en) | Gate electrodes of HVMOS devices having non-uniform doping concentrations | |
| KR100962233B1 (en) | High Voltage Junction Field Effect Transistor | |
| KR101530582B1 (en) | A semiconductor device and method for manufacturing the same | |
| US8362558B2 (en) | Low on-resistance lateral double-diffused MOS device | |
| KR20100064263A (en) | A semiconductor device and method for manufacturing the same | |
| US6773997B2 (en) | Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability | |
| JP2010135800A (en) | Semiconductor device and method for manufacturing the same | |
| KR20100064556A (en) | A semiconductor device and method of manufacturing the same | |
| US20170236930A1 (en) | Vertical double-diffused metal-oxide semiconductor field-effect transistor and manufacturing method therefor | |
| US6492679B1 (en) | Method for manufacturing a high voltage MOSFET device with reduced on-resistance | |
| CN115020486A (en) | LDMOS transistor structure and corresponding manufacturing method | |
| WO2006082618A1 (en) | Semiconductor device and method for manufacturing the same | |
| KR101099560B1 (en) | Method for manufacturing high voltage transistor | |
| KR101024638B1 (en) | Method for manufacturing semiconductor device | |
| KR100587605B1 (en) | High voltage transistor and method of fabricating the same | |
| CN216958042U (en) | LDMOS transistor structure | |
| JP2004146465A (en) | Silicon carbide semiconductor device and its manufacturing method | |
| KR100272174B1 (en) | Lateral double-diffused mos transistor device and method for manufacturing the same | |
| CN100461372C (en) | High-voltage metal oxide semiconductor element | |
| JP3802331B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR101262853B1 (en) | A semiconductor device and method of manufacturing the same | |
| KR100834287B1 (en) | Ldmos device and method for manufacturing the same | |
| JP2003115585A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |