CN102769028B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN102769028B CN102769028B CN201110115558.0A CN201110115558A CN102769028B CN 102769028 B CN102769028 B CN 102769028B CN 201110115558 A CN201110115558 A CN 201110115558A CN 102769028 B CN102769028 B CN 102769028B
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first doped well, a first doped electrode, a second doped electrode, a plurality of doping strips and a doped top area. The doping strips are positioned on the first doped well between the first doped electrode and the second doped electrode and are separated from each other. The doped top area is positioned above the doping strips and extends onto the first doped well among the doping strips. The first doped well and the doped top area are of a first electric conduction type. The doping strips are of a second electric conduction type which is opposite to the first electric conduction type. The structure and the method in each embodiment of the invention have the advantages that starting impedance of a device can be reduced, starting current can be increased, and efficacy can be improved.
Description
Technical field
The invention relates to semiconductor structure and manufacture method thereof, relate to high voltage semiconductor device and manufacture method thereof especially.
Background technology
Between nearly decades, semicon industry continues the size reducing semiconductor structure, and improves the unit cost of speed, usefulness, density and integrated circuit simultaneously.In the method for the withstand voltage degree of general lifting device, for example, utilize single mask to be formed on drift region surface profile is identical and depth bounds is different field plate region (namely Field Plate Regions forms the region of surface profile on drift region).But the lifting degree of this technology to the reduction of device impedance and firing current is still limited.
Summary of the invention
The invention relates to semiconductor structure and manufacture method thereof.Semiconductor structure has doping striped and pushes up district with doping between doped electrode.Doping striped is separated from each other.Doping top district is positioned on doping striped, and extends on the region between doping striped.Therefore can reduce the on-resistance of semiconductor structure, promote firing current and usefulness, and do not affect the withstand voltage degree of semiconductor structure.
A kind of semiconductor structure is provided.Semiconductor structure comprises one first dopant well, one first doped electrode, one second doped electrode, multiple doping striped and adulterate and push up district.On first dopant well of doping striped between the first doped electrode and the second doped electrode.Doping striped is separated from each other.Doping top district is positioned on doping striped, and extends on the first dopant well between doping striped.First dopant well pushes up district with doping and has one first conduction type.The doping content in doping top district is greater than the doping content of the first dopant well.Doping striped has one second conduction type in contrast to the first conduction type.
A kind of manufacture method of semiconductor structure is provided.Method comprises the following steps.Form multiple doping striped on one first dopant well.Doping striped is separated from each other.Form a doping top district on doping striped, and extend on the first dopant well between doping striped.Form one first doped electrode and one second doped electrode, lay respectively on the first dopant well on the opposite side in doping top district.First dopant well pushes up district with doping and has one first conduction type.Doping striped has one second conduction type in contrast to the first conduction type.
The structure of various embodiments of the present invention and method can reduce the on-resistance of device, promote firing current and usefulness, and do not affect the withstand voltage degree of device.
Preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the vertical view of the semiconductor structure according to an embodiment.
Fig. 2 illustrates the vertical view of the semiconductor structure according to an embodiment.
Fig. 3 illustrates the vertical view of the semiconductor structure according to an embodiment.
Fig. 4 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 5 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 6 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 7 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 8 illustrates the I-V curve of the semiconductor structure of an embodiment.
Fig. 9 illustrates the vertical view of the semiconductor structure according to an embodiment.
Figure 10 illustrates the vertical view of the semiconductor structure according to an embodiment.
Figure 11 illustrates the vertical view of the semiconductor structure according to an embodiment.
Figure 12 A to Figure 19 B illustrates the technique of the semiconductor structure according to an embodiment.
[primary clustering symbol description]
2,202: substrate
4,204: the first dopant wells
6,206: the second dopant wells
8,108,208: doping striped
10,110,210: doping top district
12,112,212: the first doped electrodes
14,114,214: the second doped electrodes
16,116,216: the three doped electrodes
18,218: the three dopant wells
20,120,220: the four doped electrodes
22,222: dielectric structure
24,224: grid structure
26,226: interlayer dielectric layer
28,228: conductive layer
Embodiment
Fig. 1 to Fig. 3 illustrates the vertical view of the semiconductor structure according to an embodiment.Fig. 4 and Fig. 5 illustrates the profile of the semiconductor structure according to an embodiment.Fig. 6 and Fig. 7 illustrates the profile of the semiconductor structure according to another embodiment.Fig. 8 illustrates the I-V curve of the semiconductor structure of an embodiment.Fig. 9 to Figure 11 illustrates the vertical view of the semiconductor structure according to another embodiment.
Please refer to Fig. 4, semiconductor structure comprises substrate 2.First dopant well 4 is positioned on substrate 2.Second dopant well 6 is positioned on the first dopant well 4.Doping striped 8 is positioned on the first dopant well 4.District 10, doping top is positioned on doping striped 8.First doped electrode 12 is positioned on the first dopant well 4.Second doped electrode 14 is positioned on the second dopant well 6.3rd doped electrode 16 is positioned on the second dopant well 6.3rd dopant well 18 is positioned on substrate 2.4th doped electrode 20 is positioned on the 3rd dopant well 18.Dielectric structure 22 is positioned on substrate 2.On second dopant well 6 of grid structure 24 between the second doped electrode 14 and dielectric structure 22, and extend on dielectric structure 22.Interlayer dielectric layer 26 is positioned on substrate 2.Conductive layer 28 is filled the opening of interlayer dielectric layer 26 and is electrically connected at the first doped electrode 12, second doped electrode 14, the 3rd doped electrode 16, the 4th doped electrode 20 and grid structure 24.
The difference of the semiconductor structure of Fig. 5 and the semiconductor structure of Fig. 4 is, the semiconductor structure of Fig. 5 omits doping striped 8.In one embodiment, the semiconductor structure shown in Fig. 4 draws out along the AA ' line segment of Fig. 3.Semiconductor structure shown in Fig. 5 draws out along the BB ' line segment of Fig. 3.Fig. 3 is that the semiconductor structure of Fig. 1 and Fig. 2 surrounds enlarged drawing partly with dotted line.Fig. 3 illustrates the doping striped 8 of semiconductor structure, doping top district 10, first doped electrode 12, second doped electrode 14, the 3rd doped electrode 16 and the 4th doped electrode 20.Fig. 1 omits the doping top district 10 in Fig. 3.Fig. 2 omits the doping striped 8 in Fig. 3.
Please refer to Fig. 4, in one embodiment, the first dopant well 4, district 10, first, doping top doped electrode 12 and the second doped electrode 14 have the first conduction type (a first conductivity type).Substrate 2, second dopant well 6, doping striped 8, the 3rd doped electrode 16, the 3rd dopant well 18 and the 4th doped electrode 20 have the second conduction type (a second conductivity type) in contrast to the first conduction type.For example, the first conduction type can be N-type, and the second conduction type can be P type.In other embodiments, the first conduction type can be P type, and the second conduction type can be N-type.In one embodiment, semiconductor structure is metal-oxide semiconductor (MOS) (MOS), such as NMOS or PMOS.First doped electrode 12 can be used as drain electrode.Second doped electrode 14 can be used as source electrode.In another embodiment, the first doped electrode 12 is have contrary conduction type with the second doped electrode 14.For example, the first doped electrode 12 has P conduction type, and the second doped electrode 14 has N conduction type.The semiconductor structure of this example can be insulated gate bipolar transistor (IGBT).Semiconductor structure as shown in Figures 6 and 7 can be diode.
Please refer to Fig. 3, doping striped 8 is separated from each other.In an embodiment, the width W of doping striped 8 is 0.2um to 20um.Space D between doping striped 8 is 0.2um to 20um.Please refer to Fig. 3 to Fig. 5, district 10, doping top is positioned on doping striped 8, and extends on the first dopant well 4 between doping striped 8.In an embodiment, use district 10, doping top can help vague and general efficiency and the degree of doping striped 8, therefore can reduce the on-resistance of device, promote firing current and usefulness, and do not affect the withstand voltage degree of device.The doping top district 10 that area is large also can increase (N-type) doping content of drain region, and reduces the resistance on surface, drain region.In embodiment, semiconductor structure can be applicable to high pressure, MOS, IGBT of superhigh pressure and diode.Please refer to Fig. 8, compared to general semiconductor structure, in embodiment, the on-resistance of semiconductor structure (superhigh pressure Laterally Diffused Metal Oxide Semiconductor (LDMOS)) drain electrode end can reduce about 15%, current boost about 17.5%.In addition, in embodiment, the puncture voltage of semiconductor structure maintains more than 700V.
Semiconductor structure also can have layout as shown in Figures 9 to 11.Figure 11 is that the semiconductor structure of Fig. 9 and Figure 10 surrounds enlarged drawing partly with dotted line.Figure 11 illustrates the doping striped 108 of semiconductor structure, doping top district 110, first doped electrode 112, second doped electrode 114, the 3rd doped electrode 116 and the 4th doped electrode 120.Fig. 9 omits the doping top district 110 in Figure 11.Figure 10 omits the doping striped 108 in Figure 11.
Figure 12 A to Figure 19 B illustrates the technique of the semiconductor structure according to an embodiment.The figure being labeled as A illustrates in semiconductor structure, and doping top district is positioned at the profile of the part on doping striped, the profile of the AA ' line segment of such as Fig. 3.The figure being labeled as B illustrates in semiconductor structure, and doping top district extends the profile of the part on the first dopant well between doping striped, the profile of the BB ' line segment of such as Fig. 3.
Please refer to Figure 12 A and Figure 12 B, a substrate 202 such as bulk silicon or silicon-on-insulator (SOI) is provided.First dopant well 204 is formed on substrate 202.Second dopant well 206 is formed on the first dopant well 204.3rd dopant well 218 is formed on substrate 202.In one embodiment, simultaneously the second dopant well 206 and the 3rd dopant well 218 utilize same mask to be formed.Please refer to Figure 12 A, doping striped 208 can be formed on the first dopant well 204.
Please refer to Figure 13 A and Figure 13 B, form district 210, doping top on doping striped 208 with on the first dopant well 204.In an embodiment, the mask pushing up district 210 in order to form doping is the mask be different from order to form doping striped 208.
Please refer to Figure 14 A and Figure 14 B, form dielectric structure 222 on substrate 202.Dielectric structure 222 is not limited to the field oxide as shown in Figure 14 A and Figure 14 B, also can comprise shallow trench isolation from.
Please refer to Figure 15 A and Figure 15 B, grid structure 224 can be formed on the first dopant well 204 and the second dopant well 206, and extend on dielectric structure 222.Grid structure 224 can comprise gate dielectric layer, gate electrode layer and clearance wall.Gate electrode layer is formed on gate dielectric layer.Clearance wall is formed in the opposing sidewalls of gate dielectric layer and gate electrode layer.In one embodiment, between formation gate dielectric layer, be on the surface of substrate 202, form sacrifical oxide (SAC oxide), then remove sacrifical oxide, form the second best in quality gate dielectric layer to get help.Gate electrode layer can comprise polysilicon and the metal silicide such as tungsten silicide be formed on polysilicon.Clearance wall can comprise silicon dioxide such as tetraethoxysilane (Tetraethoxy silane; TEOS).
Please refer to Figure 16 A and Figure 16 B, form the first doped electrode 212 on the first dopant well 204.Form the second doped electrode 214 on the second dopant well 206.In one embodiment, the first doped electrode 212 and the second doped electrode 214 are heavily doped.Please refer to Figure 17 A and Figure 17 B, form the 3rd doped electrode 216 on the second dopant well 206.Form the 4th doped electrode 220 on the 3rd dopant well 218.In one embodiment, the 3rd doped electrode 216 and the 4th doped electrode 220 are heavily doped.Please refer to Figure 18 A and Figure 18 B, form interlayer dielectric layer 226 on substrate 202.Please refer to Figure 19 A and Figure 19 B, fill the opening of interlayer dielectric layer 226 with conductive layer 228.Conductive layer 228 can comprise metal.
Although the present invention with preferred embodiment openly as above; so itself and be not used to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; should do change and the modification of local, therefore protection scope of the present invention is when being as the criterion depending on the claim person of defining.
Claims (10)
1. a semiconductor structure, is characterized in that, comprising:
One first dopant well;
One first doped electrode;
One second doped electrode;
Multiple doping striped, on this first dopant well between this first doped electrode and this second doped electrode, wherein these doping stripeds are separated from each other; And
One doping top district, be positioned on these doping stripeds, and extend on this first dopant well between these doping stripeds, wherein, this first dopant well and this doping top district have one first conduction type, and these doping stripeds have one second conduction type in contrast to this first conduction type.
2. semiconductor structure according to claim 1, is characterized in that, also comprises:
One dielectric structure, is positioned in this doping top district;
One second dopant well, between this first dopant well and this second doped electrode; And
One grid structure, on this second dopant well between this second doped electrode and this dielectric structure, and extends on this dielectric structure.
3. semiconductor structure according to claim 1, is characterized in that, these each width of doping stripeds are 0.2um to 20um.
4. semiconductor structure according to claim 1, is characterized in that, the spacing between these doping stripeds is 0.2um to 20um.
5. semiconductor structure according to claim 1, is characterized in that, this first doped electrode has contrary conduction type with this second doped electrode.
6. semiconductor structure according to claim 1, is characterized in that, this first doped electrode and this second doped electrode have this first conduction type.
7. a manufacture method for semiconductor structure, is characterized in that, comprising:
Form multiple doping striped on one first dopant well, wherein these doping stripeds are separated from each other;
Form a doping top district on these doping stripeds, and extend on this first dopant well between these doping stripeds; And
Form one first doped electrode and one second doped electrode, lay respectively on this first dopant well on the opposite side in this doping top district, wherein,
This first dopant well and this doping top district have one first conduction type, and these doping stripeds have one second conduction type in contrast to this first conduction type.
8. the manufacture method of semiconductor structure according to claim 7, is characterized in that, these each width of doping stripeds are 0.2um to 20um, and the spacing between these doping stripeds are 0.2um to 20um.
9. the manufacture method of semiconductor structure according to claim 7, is characterized in that, this first doped electrode has contrary conduction type with this second doped electrode.
10. the manufacture method of semiconductor structure according to claim 7, is characterized in that, this first doped electrode and this second doped electrode have this first conduction type.
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| CN201110115558.0A CN102769028B (en) | 2011-05-03 | 2011-05-03 | Semiconductor structure and manufacturing method thereof |
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| CN102769028B true CN102769028B (en) | 2015-01-28 |
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| US8785988B1 (en) * | 2013-01-11 | 2014-07-22 | Macronix International Co., Ltd. | N-channel metal-oxide field effect transistor with embedded high voltage junction gate field-effect transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0618622A1 (en) * | 1993-02-01 | 1994-10-05 | Power Integrations, Inc. | High voltage transistor |
| EP1298721A2 (en) * | 2001-09-28 | 2003-04-02 | Dalsa Semiconductor Inc. | Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices |
| CN101162697A (en) * | 2006-10-13 | 2008-04-16 | 台湾积体电路制造股份有限公司 | Lateral power mosfet with high breakdown voltage and low on-resistance |
| CN101661955A (en) * | 2008-08-28 | 2010-03-03 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3121723B2 (en) * | 1994-06-27 | 2001-01-09 | 松下電子工業株式会社 | Semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0618622A1 (en) * | 1993-02-01 | 1994-10-05 | Power Integrations, Inc. | High voltage transistor |
| EP1298721A2 (en) * | 2001-09-28 | 2003-04-02 | Dalsa Semiconductor Inc. | Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices |
| CN101162697A (en) * | 2006-10-13 | 2008-04-16 | 台湾积体电路制造股份有限公司 | Lateral power mosfet with high breakdown voltage and low on-resistance |
| CN101661955A (en) * | 2008-08-28 | 2010-03-03 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor device and manufacturing method thereof |
Non-Patent Citations (1)
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| JP特开平8-17935A 1996.01.19 * |
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