CN114512532A - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

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Publication number
CN114512532A
CN114512532A CN202011281570.4A CN202011281570A CN114512532A CN 114512532 A CN114512532 A CN 114512532A CN 202011281570 A CN202011281570 A CN 202011281570A CN 114512532 A CN114512532 A CN 114512532A
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layer
type semiconductor
semiconductor layer
conductive layer
semiconductor device
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Inventor
龚轶
刘伟
刘磊
袁愿林
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to CN202011281570.4A priority Critical patent/CN114512532A/en
Priority to PCT/CN2020/130598 priority patent/WO2022099763A1/en
Publication of CN114512532A publication Critical patent/CN114512532A/en
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

The invention discloses a semiconductor device, comprising: a first conductive layer in a lower portion of the gate trench, the first conductive layer being isolated from the second n-type semiconductor layer by a first insulating layer, a second conductive layer in an upper portion of the gate trench, the second conductive layer being isolated from the p-type semiconductor layer, the third n-type semiconductor layer and the first conductive layer by a second insulating layer; the third conducting layer is positioned in the source electrode groove, connected with the p-type semiconductor layer and the third n-type semiconductor layer and isolated from the second n-type semiconductor layer at the position of the side wall of the source electrode groove through a third insulating layer; and the p-type well region is positioned in the second n-type semiconductor layer and at the bottom of the source electrode groove, and the p-type well region is connected with the third conducting layer at the bottom of the source electrode groove. The invention can reduce the risk of breakdown of the grid and improve the withstand voltage of the semiconductor device.

Description

Semiconductor device with a plurality of transistors
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor device manufactured on a silicon carbide semiconductor layer.
Background
Silicon carbide has many different characteristics from the traditional silicon semiconductor material, the energy band gap of the silicon semiconductor material is 2.8 times of that of silicon, and the insulation breakdown field strength of the silicon semiconductor material is 5.3 times of that of silicon, so that in the field of high-voltage power devices, the silicon carbide device can use an epitaxial layer which is thinner than the silicon material to reach the same voltage withstanding level of the traditional silicon device, and meanwhile, the silicon carbide device has lower on-resistance. At present, the main problem of using silicon carbide to prepare a trench power device is that a large electric field is applied to a gate dielectric layer in a gate trench when the device is operated, so that a gate is easily broken down, and the withstand voltage of the device is affected.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor device, so as to reduce the risk of breakdown of a gate and improve the withstand voltage of the semiconductor device.
To achieve the above object of the present invention, the present invention provides a semiconductor device comprising:
a semiconductor layer including a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer, and a third n-type semiconductor layer which are sequentially stacked;
the grid electrode grooves and the source electrode grooves are positioned in the semiconductor layer and are alternately arranged at intervals, and the bottoms of the grid electrode grooves and the bottoms of the source electrode grooves are positioned in the second n-type semiconductor layer;
a first conductive layer within a lower portion of the gate trench, the first conductive layer being separated from the second n-type semiconductor layer by a first insulating layer, a second conductive layer within an upper portion of the gate trench, the second conductive layer being separated from the p-type semiconductor layer, the third n-type semiconductor layer, and the first conductive layer by a second insulating layer;
a third conductive layer located within the source trench, the third conductive layer being connected to the p-type semiconductor layer and the third n-type semiconductor layer, the third conductive layer being isolated from the second n-type semiconductor layer at the sidewall position of the source trench by a third insulating layer;
and the p-type well region is positioned in the second n-type semiconductor layer and at the bottom of the source electrode groove, and the p-type well region is connected with the third conducting layer at the bottom of the source electrode groove.
Optionally, the depth of the gate trench is the same as the depth of the source trench.
Optionally, the width of the source trench is greater than the width of the gate trench.
Optionally, the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer, and the third n-type semiconductor layer are all silicon carbide semiconductor layers.
Optionally, the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
Optionally, the material of the first insulating layer is silicon oxide.
Optionally, the third insulating layer is made of silicon oxide.
Optionally, the material of the second insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride, and hafnium oxide.
Optionally, the material of the first conductive layer is conductive polysilicon.
Optionally, the second conductive layer is made of at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten.
Optionally, the material of the third conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten.
Optionally, the first conductive layer extends up into an upper portion of the gate trench.
According to the semiconductor device, firstly, the electric field near the bottom of the source groove can be increased by the p-type well region below the source groove, the highest electric field is limited at the pn junction at the bottom of the source groove, the grid electrode in the upper part of the grid groove is protected from being broken down easily, and the withstand voltage of the device is improved; secondly, the first insulating layer with larger thickness is adopted in the lower part of the grid groove, so that the grid in the upper part of the grid groove can be further protected from being easily broken down; and thirdly, the first conducting layer in the lower part of the grid groove can increase the electric field at the bottom of the grid groove and improve the withstand voltage of the device.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiment of the present invention, a brief introduction will be made to the drawings required for describing the embodiment.
Fig. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor device provided by the present invention.
Detailed Description
The technical solution of the present invention will be fully described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the use of terms such as "having," "including," and "comprising" in connection with the present invention does not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic drawings listed in the accompanying drawings enlarge the thickness of the layers and regions of the present invention, and the listed sizes of the figures do not represent actual sizes.
Fig. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor device provided by the present invention, and as shown in fig. 1, the semiconductor device of the present invention includes a semiconductor layer 20, where the semiconductor layer 20 includes a first n-type semiconductor layer 21, a second n-type semiconductor layer 22, a p-type semiconductor layer 23, and a third n-type semiconductor layer 24, which are sequentially stacked, and optionally, the first n-type semiconductor layer 21 serves as an n-type drain region of the semiconductor device, and the first n-type semiconductor layer 21, the second n-type semiconductor layer 22, the p-type semiconductor layer 23, and the third n-type semiconductor layer 24 are all silicon carbide semiconductor layers.
And gate trenches 41 and source trenches 42 alternately spaced apart and located in the semiconductor layer 20, a bottom of the gate trenches 41 and a bottom of the source trenches 42 being located in the second n-type semiconductor layer 22. The number of gate trenches 41 and source trenches 42 is determined by the specifications of the designed semiconductor device, and only one gate trench 41 and two source trenches 42 are exemplarily shown in the embodiment of the present invention. The depth of the gate trench 41 and the depth of the source trench 42 may be the same, and thus, the gate trench 41 and the source trench 42 may be simultaneously formed in the same etching process.
The p-type semiconductor layer 23 between the gate trench 41 and the source trench 42 serves as a p-type body region of the semiconductor device, and the third n-type semiconductor layer 24 between the gate trench 41 and the source trench 42 serves as an n-type source region of the semiconductor device.
A first conductive layer 25 located within a lower portion of the gate trench 41, the first conductive layer 25 being separated from the second n-type semiconductor layer 22 by a first insulating layer 26, the material of the first insulating layer 26 typically being silicon oxide, the material of the first conductive layer 25 typically being conductive polysilicon, such as p-type doped polysilicon; a second conductive layer 27 located within an upper portion of the gate trench 41, the second conductive layer 27 being separated from the p-type semiconductor layer 23, the third n-type semiconductor layer 24 and the first conductive layer 25 by a second insulating layer 28, the second conductive layer 27 and the second insulating layer 28 forming a gate structure of the device. The material of the second insulating layer 28 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, and hafnium oxide, or may be another insulating medium with a high dielectric constant, and the material of the second conductive layer 27 may be at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten.
The width of the source trench 42 may be greater than the width of the gate trench 41, so that the first insulating layer 26 and the first conductive layer 25 in the gate trench 41 may be more easily formed to simplify the manufacturing process of the semiconductor device of the present invention.
The first conductive layer 25 in the lower portion of the gate trench 41 may be externally connected to a source voltage for increasing an electric field at the bottom of the gate trench 41 and improving a withstand voltage of the semiconductor device. Meanwhile, the thickness of the first insulating layer 26 may be greater than that of the second insulating layer 28, which may protect the gate electrode in the upper portion of the gate trench 41 from being easily broken down.
Optionally, the first conductive layer located in the lower portion of the gate trench may extend upward into the upper portion of the gate trench, and in this case, in the upper portion of the gate trench, the second conductive layer may be located on both sides of the first conductive layer, may surround the upper portion of the first conductive layer, or surround the upper portion of the first conductive layer and cover the upper surface of the first conductive layer, which is not specifically shown in the embodiments of the present invention.
And a third conductive layer 29 located within the source trench 42, the third conductive layer 29 being connected to the p-type semiconductor layer 23 and the third n-type semiconductor layer 24, the third conductive layer 29 being isolated from the second n-type semiconductor layer 22 at the position of the sidewall of the source trench 42 by a third insulating layer 30. Illustratively, the material of the third insulating layer 30 may be silicon oxide, and the material of the third conductive layer 29 may be at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten. The material of the third insulating layer 30 may be the same as that of the first insulating layer 26, so that the third insulating layer 30 and the first insulating layer 26 can be formed in the same manufacturing process step, thereby simplifying the manufacturing process of the semiconductor device.
And a p-type well region 31 located in the second n-type semiconductor layer 22 at a bottom position of the source trench 42, the p-type well region 31 being connected to the third conductive layer 29 at the bottom position of the source trench 42. The p-type well region 31 and the second n-type semiconductor layer 22 form a pn junction structure, an electric field near the bottom of the source trench is increased, the highest electric field in the semiconductor device is limited at the pn junction below the source trench 42, the gate in the upper part of the gate trench 41 is protected from being broken down easily, and the withstand voltage of the device is improved.
The above embodiments and examples are specific supports for the technical ideas of the present invention, and the protection scope of the present invention should not be limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical solutions according to the technical ideas proposed by the present invention still belong to the protection scope of the technical solutions of the present invention.

Claims (10)

1. A semiconductor device, comprising:
a semiconductor layer including a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer, and a third n-type semiconductor layer which are sequentially stacked;
the grid electrode grooves and the source electrode grooves are positioned in the semiconductor layer and are alternately arranged at intervals, and the bottoms of the grid electrode grooves and the bottoms of the source electrode grooves are both positioned in the second n-type semiconductor layer;
a first conductive layer within a lower portion of the gate trench, the first conductive layer being separated from the second n-type semiconductor layer by a first insulating layer, a second conductive layer within an upper portion of the gate trench, the second conductive layer being separated from the p-type semiconductor layer, the third n-type semiconductor layer, and the first conductive layer by a second insulating layer;
a third conductive layer located within the source trench, the third conductive layer being connected to the p-type semiconductor layer and the third n-type semiconductor layer, the third conductive layer being isolated from the second n-type semiconductor layer at the sidewall position of the source trench by a third insulating layer;
and the p-type well region is positioned in the second n-type semiconductor layer and at the bottom of the source electrode groove, and the p-type well region is connected with the third conducting layer at the bottom of the source electrode groove.
2. The semiconductor device of claim 1, in which a depth of the gate trench is the same as a depth of the source trench.
3. The semiconductor device of claim 1, wherein a width of the source trench is greater than a width of the gate trench.
4. The semiconductor device according to claim 1, wherein the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer, and the third n-type semiconductor layer are all silicon carbide semiconductor layers.
5. The semiconductor device according to claim 1, wherein a thickness of the first insulating layer is larger than a thickness of the second insulating layer.
6. The semiconductor device according to claim 1, wherein the material of each of the first insulating layer and the third insulating layer is silicon oxide.
7. The semiconductor device according to claim 1, wherein a material of the second insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride, and hafnium oxide.
8. The semiconductor device according to claim 1, wherein a material of the first conductive layer is conductive polysilicon.
9. The semiconductor device according to claim 1, wherein a material of the second conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten;
the material of the third conducting layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
10. The semiconductor device of claim 1, wherein the first conductive layer extends up into an upper portion of the gate trench.
CN202011281570.4A 2020-11-16 2020-11-16 Semiconductor device with a plurality of transistors Pending CN114512532A (en)

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