WO2022099763A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2022099763A1
WO2022099763A1 PCT/CN2020/130598 CN2020130598W WO2022099763A1 WO 2022099763 A1 WO2022099763 A1 WO 2022099763A1 CN 2020130598 W CN2020130598 W CN 2020130598W WO 2022099763 A1 WO2022099763 A1 WO 2022099763A1
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Prior art keywords
layer
type semiconductor
semiconductor layer
conductive layer
trench
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PCT/CN2020/130598
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French (fr)
Chinese (zh)
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龚轶
刘伟
刘磊
袁愿林
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苏州东微半导体有限公司
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Publication of WO2022099763A1 publication Critical patent/WO2022099763A1/en

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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Definitions

  • the present application belongs to the technical field of semiconductor devices, for example, relates to a semiconductor device fabricated on a silicon carbide semiconductor layer.
  • Silicon carbide has many characteristics different from traditional silicon semiconductor materials. Its energy band gap is 2.8 times that of silicon, and its dielectric breakdown field strength is 5.3 times that of silicon. Therefore, in the field of high-voltage power devices, silicon carbide devices can be used compared to silicon materials. Thinner epitaxial layers to reach the same withstand voltage level as conventional silicon devices, while having lower on-resistance. At present, the main problem of using silicon carbide to fabricate trench power devices is that a large electric field will be applied to the gate dielectric layer in the gate trench during the operation of the device, which makes the gate easily broken down and affects the device. pressure resistance.
  • the present application provides a semiconductor device, so as to reduce the risk of gate breakdown and improve the withstand voltage of the semiconductor device.
  • the present application provides a semiconductor device including:
  • the semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer and a third n-type semiconductor layer stacked in sequence;
  • gate trenches and source trenches that are located in the semiconductor layer and are alternately spaced, and the bottoms of the gate trenches and the source trenches are both located in the second n-type semiconductor layer;
  • a first conductive layer in the lower portion of the gate trench the first conductive layer being isolated from the second n-type semiconductor layer by a first insulating layer, and a first conductive layer in the upper portion of the gate trench
  • Two conductive layers, the second conductive layer is isolated from the p-type semiconductor layer, the third n-type semiconductor layer and the first conductive layer by a second insulating layer;
  • a third conductive layer located in the source trench the third conductive layer is connected to the p-type semiconductor layer and the third n-type semiconductor layer, and the third conductive layer is connected to the third insulating layer through a third insulating layer.
  • the second n-type semiconductor layer is isolated at the position of the sidewall of the source trench;
  • a p-type well region located in the second n-type semiconductor layer and located at the bottom of the source trench, the p-type well region and the third conductive layer are at the bottom of the source trench location is connected.
  • the depth of the gate trench is the same as the depth of the source trench.
  • the width of the source trench is greater than the width of the gate trench.
  • the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer and the third n-type semiconductor layer are all silicon carbide semiconductor layers.
  • the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
  • the material of the first insulating layer is silicon oxide.
  • the material of the third insulating layer is silicon oxide.
  • the material of the second insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride and hafnium oxide.
  • the material of the first conductive layer is conductive polysilicon.
  • the material of the second conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
  • the material of the third conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
  • the first conductive layer extends upward into the upper portion of the gate trench.
  • the p-type well region under the source trench can increase the electric field near the bottom of the source trench, limit the highest electric field at the pn junction at the bottom of the source trench, and protect the gate trench.
  • the gate in the upper part is not easily broken down and improves the withstand voltage of the device;
  • the first insulating layer with a larger thickness is used in the lower part of the gate trench, which can further protect the gate in the upper part of the gate trench from being damaged. It is easy to be broken down; again, the first conductive layer in the lower part of the gate trench can increase the electric field at the bottom of the gate trench and improve the withstand voltage of the device.
  • FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor device provided by the present application.
  • FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor device provided by the present application.
  • the semiconductor device of the present application includes a semiconductor layer 20, and the semiconductor layer 20 includes a first n-type semiconductor layer 21, a first n-type semiconductor layer 21, a first n-type semiconductor layer 21 and a Two n-type semiconductor layers 22, p-type semiconductor layers 23 and third n-type semiconductor layers 24.
  • the first n-type semiconductor layer 21 serves as the n-type drain region of the semiconductor device.
  • the two n-type semiconductor layers 22 , the p-type semiconductor layer 23 and the third n-type semiconductor layer 24 are all silicon carbide semiconductor layers.
  • the gate trenches 41 and the source trenches 42 are located in the semiconductor layer 20 and are alternately spaced, and the bottoms of the gate trenches 41 and the source trenches 42 are both located in the second n-type semiconductor layer 22 .
  • the numbers of the gate trenches 41 and the source trenches 42 are determined by the specifications of the designed semiconductor device, and only one gate trench 41 and two source trenches 42 are exemplarily shown in the embodiments of the present application.
  • the depth of the gate trench 41 and the depth of the source trench 42 may be the same, and thus, the gate trench 41 and the source trench 42 may be simultaneously formed in the same etching process.
  • the p-type semiconductor layer 23 between the gate trench 41 and the source trench 42 serves as the p-type body region of the semiconductor device
  • the third n-type semiconductor layer 24 between the gate trench 41 and the source trench 42 serves as the p-type body region of the semiconductor device.
  • n-type source region of a semiconductor device n-type source region of a semiconductor device.
  • the material of a conductive layer 25 is usually conductive polysilicon, such as p-type doped polysilicon;
  • the second conductive layer 27 located in the upper part of the gate trench 41, the second conductive layer 27 is connected to the p-type through the second insulating layer 28.
  • the n-type semiconductor layer 23, the third n-type semiconductor layer 24 and the first conductive layer 25 are isolated, and the second conductive layer 27 and the second insulating layer 28 form the gate structure of the device.
  • the material of the second insulating layer 28 can be at least one of silicon oxide, silicon nitride, silicon oxynitride and hafnium oxide, or other insulating medium with high dielectric constant, and the material of the second conductive layer 27 can be titanium , at least one of nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
  • the width of the source trench 42 may be greater than the width of the gate trench 41, so that the first insulating layer 26 and the first conductive layer 25 in the gate trench 41 can be more easily formed, so as to simplify the semiconductor device of the present application. manufacturing process.
  • the first conductive layer 25 located in the lower part of the gate trench 41 can be connected to a source voltage to increase the electric field at the bottom of the gate trench 41 and improve the withstand voltage of the semiconductor device. Meanwhile, the thickness of the first insulating layer 26 may be greater than that of the second insulating layer 28, which may protect the gate electrode in the upper portion of the gate trench 41 from being easily broken down.
  • the first conductive layer located in the lower part of the gate trench may extend upward to the upper part of the gate trench, and at this time, in the upper part of the gate trench, the second conductive layer may be located in the first conductive layer.
  • the two sides of the conductive layer may also surround and surround the upper portion of the first conductive layer, or surround the upper portion of the first conductive layer and cover the upper surface of the first conductive layer. This structure will not be specifically shown in the embodiments of the present application. .
  • the second n-type semiconductor layer 22 at the location of the sidewall of the trench 42 is isolated.
  • the material of the third insulating layer 30 may be silicon oxide
  • the material of the third conductive layer 29 may be at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
  • the material of the third insulating layer 30 may be the same as that of the first insulating layer 26, so that the third insulating layer 30 and the first insulating layer 26 can be formed in the same manufacturing process step, thereby simplifying the manufacturing process of the semiconductor device.
  • the p-type well region 31 located in the second n-type semiconductor layer 22 at the bottom position of the source trench 42 is connected to the third conductive layer 29 at the bottom position of the source trench 42 .
  • the p-type well region 31 and the second n-type semiconductor layer 22 form a pn junction structure, increase the electric field near the bottom of the source trench, limit the highest electric field in the semiconductor device to the pn junction under the source trench 42, and protect the The gate in the upper portion of the gate trench 41 is not easily broken down, and the withstand voltage of the device is improved.

Abstract

A semiconductor device, comprising: a first conductive layer (25) located in a lower portion of a gate trench (41), the first conductive layer being isolated from a second n-type semiconductor layer (22) by means of a first insulating layer (26); a second conductive layer (27) located in an upper portion of the gate trench, the second conductive layer being isolated from a p-type semiconductor layer (23), a third n-type semiconductor layer (24), and the first conductive layer by means of a second insulating layer (28); a third conductive layer (29) located in a source electrode trench (42), the third conductive layer being connected to the p-type semiconductor layer and the third n-type semiconductor, and being isolated from a sidewall position of the source electrode trench by means of a third insulating layer (30); and a p-type well region (31) located in the second n-type semiconductor layer and located at a position on the bottom of the source electrode trench, the p-type well region being connected to the third conductive layer at the position on the bottom of the source electrode trench.

Description

半导体器件Semiconductor device
本申请要求在2020年11月16日提交中国专利局、申请号为202011281570.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。This application claims the priority of a Chinese patent application with application number 202011281570.4 filed with the China Patent Office on November 16, 2020, the entire contents of which are incorporated herein by reference.
技术领域technical field
本申请属于半导体器件技术领域，例如涉及一种在碳化硅半导体层上制作的半导体器件。The present application belongs to the technical field of semiconductor devices, for example, relates to a semiconductor device fabricated on a silicon carbide semiconductor layer.
背景技术Background technique
碳化硅具有不同于传统硅半导体材料的诸多特点，其能带间隙为硅的2.8倍,绝缘击穿场强为硅的5.3倍,因此在高压功率器件领域，碳化硅器件可以使用相对于硅材料更薄的外延层来到达传统硅器件相同的耐压水平，同时拥有更低的导通电阻。目前，利用碳化硅制备沟槽功率器件的主要问题在于，在器件运行时会有很大的电场施加在栅极沟槽内的栅介质层上，这使得栅极容易被击穿，影响了器件的耐压。Silicon carbide has many characteristics different from traditional silicon semiconductor materials. Its energy band gap is 2.8 times that of silicon, and its dielectric breakdown field strength is 5.3 times that of silicon. Therefore, in the field of high-voltage power devices, silicon carbide devices can be used compared to silicon materials. Thinner epitaxial layers to reach the same withstand voltage level as conventional silicon devices, while having lower on-resistance. At present, the main problem of using silicon carbide to fabricate trench power devices is that a large electric field will be applied to the gate dielectric layer in the gate trench during the operation of the device, which makes the gate easily broken down and affects the device. pressure resistance.
发明内容SUMMARY OF THE INVENTION
本申请提供一种半导体器件，以降低栅极被击穿的风险，提高半导体器件的耐压。The present application provides a semiconductor device, so as to reduce the risk of gate breakdown and improve the withstand voltage of the semiconductor device.
本申请提供了一种半导体器件，包括：The present application provides a semiconductor device including:
半导体层，所述半导体层包括依次层叠的第一n型半导体层、第二n型半导体层、p型半导体层和第三n型半导体层；a semiconductor layer, the semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer and a third n-type semiconductor layer stacked in sequence;
位于所述半导体层内且交替间隔设置的栅极沟槽和源极沟槽，所述栅极沟槽的底部和所述源极沟槽的底部均位于所述第二n型半导体层内；gate trenches and source trenches that are located in the semiconductor layer and are alternately spaced, and the bottoms of the gate trenches and the source trenches are both located in the second n-type semiconductor layer;
位于所述栅极沟槽的下部内的第一导电层，所述第一导电层通过第一绝缘 层与所述第二n型半导体层隔离，位于所述栅极沟槽的上部内的第二导电层，所述第二导电层通过第二绝缘层与所述p型半导体层、所述第三n型半导体层和所述第一导电层隔离；A first conductive layer in the lower portion of the gate trench, the first conductive layer being isolated from the second n-type semiconductor layer by a first insulating layer, and a first conductive layer in the upper portion of the gate trench Two conductive layers, the second conductive layer is isolated from the p-type semiconductor layer, the third n-type semiconductor layer and the first conductive layer by a second insulating layer;
位于所述源极沟槽内的第三导电层，所述第三导电层与所述p型半导体层和所述第三n型半导体层连接，所述第三导电层通过第三绝缘层与所述源极沟槽的侧壁位置处的所述第二n型半导体层隔离；A third conductive layer located in the source trench, the third conductive layer is connected to the p-type semiconductor layer and the third n-type semiconductor layer, and the third conductive layer is connected to the third insulating layer through a third insulating layer. the second n-type semiconductor layer is isolated at the position of the sidewall of the source trench;
位于所述第二n型半导体层内且位于所述源极沟槽的底部位置处的p型阱区，所述p型阱区与所述第三导电层在所述源极沟槽的底部位置相连接。a p-type well region located in the second n-type semiconductor layer and located at the bottom of the source trench, the p-type well region and the third conductive layer are at the bottom of the source trench location is connected.
可选的，所述栅极沟槽的深度与所述源极沟槽的深度相同。Optionally, the depth of the gate trench is the same as the depth of the source trench.
可选的，所述源极沟槽的宽度大于所述栅极沟槽的宽度。Optionally, the width of the source trench is greater than the width of the gate trench.
可选的，所述第一n型半导体层、所述第二n型半导体层、所述p型半导体层和所述第三n型半导体层均为碳化硅半导体层。Optionally, the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer and the third n-type semiconductor layer are all silicon carbide semiconductor layers.
可选的，所述第一绝缘层的厚度大于所述第二绝缘层的厚度。Optionally, the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
可选的，所述第一绝缘层的材料为氧化硅。Optionally, the material of the first insulating layer is silicon oxide.
可选的，所述第三绝缘层的材料为氧化硅。Optionally, the material of the third insulating layer is silicon oxide.
可选的，所述第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅和氧化铪中的至少一种。Optionally, the material of the second insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride and hafnium oxide.
可选的，所述第一导电层的材料为导电性多晶硅。Optionally, the material of the first conductive layer is conductive polysilicon.
可选的，所述第二导电层的材料为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。Optionally, the material of the second conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
可选的，所述第三导电层的材料为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。Optionally, the material of the third conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
可选的，所述第一导电层向上延伸至所述栅极沟槽的上部内。Optionally, the first conductive layer extends upward into the upper portion of the gate trench.
本申请的半导体器件，首先，源极沟槽下方的p型阱区可以增加源极沟槽底部附近的电场，把最高电场限定在源极沟槽底部的pn结处，保护栅极沟槽的上部内的栅极不容易被击穿并提高器件的耐压；其次，栅极沟槽的下部内采用更 大厚度的第一绝缘层，可以进一步保护栅极沟槽的上部内的栅极不容易被击穿；再次，栅极沟槽的下部内的第一导电层可以增加栅极沟槽底部的电场，提高器件的耐压。In the semiconductor device of the present application, first, the p-type well region under the source trench can increase the electric field near the bottom of the source trench, limit the highest electric field at the pn junction at the bottom of the source trench, and protect the gate trench. The gate in the upper part is not easily broken down and improves the withstand voltage of the device; secondly, the first insulating layer with a larger thickness is used in the lower part of the gate trench, which can further protect the gate in the upper part of the gate trench from being damaged. It is easy to be broken down; again, the first conductive layer in the lower part of the gate trench can increase the electric field at the bottom of the gate trench and improve the withstand voltage of the device.
附图说明Description of drawings
图1是本申请提供的半导体器件的一个实施例的剖面结构示意图。FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor device provided by the present application.
具体实施方式Detailed ways
以下将结合本申请实施例中的附图，完整地描述本申请的技术方案。应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。The technical solutions of the present application will be completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that terms such as "having", "comprising" and "including" used herein do not assign the presence of one or more other elements or combinations thereof. Meanwhile, in order to clearly illustrate the specific embodiments of the present application, the schematic diagrams listed in the accompanying drawings of the specification have enlarged the thicknesses of the layers and regions described in the present application, and the sizes of the listed figures do not represent actual sizes.
图1是本申请提供的半导体器件的一个实施例的剖面结构示意图，如图1所示，本申请的半导体器件包括半导体层20，半导体层20包括依次层叠的第一n型半导体层21、第二n型半导体层22、p型半导体层23和第三n型半导体层24，可选的，第一n型半导体层21作为半导体器件的n型漏区，第一n型半导体层21、第二n型半导体层22、p型半导体层23和第三n型半导体层24均为碳化硅半导体层。FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor device provided by the present application. As shown in FIG. 1 , the semiconductor device of the present application includes a semiconductor layer 20, and the semiconductor layer 20 includes a first n-type semiconductor layer 21, a first n-type semiconductor layer 21, a first n-type semiconductor layer 21 and a Two n-type semiconductor layers 22, p-type semiconductor layers 23 and third n-type semiconductor layers 24. Optionally, the first n-type semiconductor layer 21 serves as the n-type drain region of the semiconductor device. The two n-type semiconductor layers 22 , the p-type semiconductor layer 23 and the third n-type semiconductor layer 24 are all silicon carbide semiconductor layers.
位于半导体层20内且交替间隔设置的栅极沟槽41和源极沟槽42，栅极沟槽41的底部和源极沟槽42的底部均位于第二n型半导体层22内。栅极沟槽41和源极沟槽42的数量由所设计的半导体器件的规格确定，本申请实施例中仅示例性的示出了一个栅极沟槽41和两个源极沟槽42。栅极沟槽41的深度与源极沟槽42的深度可以相同，由此，栅极沟槽41和源极沟槽42可以在同一步刻蚀工艺中同时形成。The gate trenches 41 and the source trenches 42 are located in the semiconductor layer 20 and are alternately spaced, and the bottoms of the gate trenches 41 and the source trenches 42 are both located in the second n-type semiconductor layer 22 . The numbers of the gate trenches 41 and the source trenches 42 are determined by the specifications of the designed semiconductor device, and only one gate trench 41 and two source trenches 42 are exemplarily shown in the embodiments of the present application. The depth of the gate trench 41 and the depth of the source trench 42 may be the same, and thus, the gate trench 41 and the source trench 42 may be simultaneously formed in the same etching process.
栅极沟槽41和源极沟槽42之间的p型半导体层23作为半导体器件的p型 体区，栅极沟槽41和源极沟槽42之间的第三n型半导体层24作为半导体器件的n型源区。The p-type semiconductor layer 23 between the gate trench 41 and the source trench 42 serves as the p-type body region of the semiconductor device, and the third n-type semiconductor layer 24 between the gate trench 41 and the source trench 42 serves as the p-type body region of the semiconductor device. n-type source region of a semiconductor device.
位于栅极沟槽41的下部内的第一导电层25，第一导电层25通过第一绝缘层26与第二n型半导体层22隔离，第一绝缘层26的材料通常为氧化硅，第一导电层25的材料通常为导电性多晶硅，比如为p型掺杂的多晶硅；位于栅极沟槽41的上部内的第二导电层27，第二导电层27通过第二绝缘层28与p型半导体层23、第三n型半导体层24和第一导电层25隔离，第二导电层27与第二绝缘层28形成器件的栅极结构。第二绝缘层28的材料可以为氧化硅、氮化硅、氮氧化硅和氧化铪中的至少一种，也可以为其它高介电常数的绝缘介质，第二导电层27的材料可以为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。The first conductive layer 25 located in the lower part of the gate trench 41, the first conductive layer 25 is isolated from the second n-type semiconductor layer 22 by the first insulating layer 26, the material of the first insulating layer 26 is usually silicon oxide, The material of a conductive layer 25 is usually conductive polysilicon, such as p-type doped polysilicon; the second conductive layer 27 located in the upper part of the gate trench 41, the second conductive layer 27 is connected to the p-type through the second insulating layer 28. The n-type semiconductor layer 23, the third n-type semiconductor layer 24 and the first conductive layer 25 are isolated, and the second conductive layer 27 and the second insulating layer 28 form the gate structure of the device. The material of the second insulating layer 28 can be at least one of silicon oxide, silicon nitride, silicon oxynitride and hafnium oxide, or other insulating medium with high dielectric constant, and the material of the second conductive layer 27 can be titanium , at least one of nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
源极沟槽42的宽度可以大于栅极沟槽41的宽度，这样可以更加容易的形成栅极沟槽41内的第一绝缘层26和第一导电层25，以简化本申请的半导体器件的制造工艺。The width of the source trench 42 may be greater than the width of the gate trench 41, so that the first insulating layer 26 and the first conductive layer 25 in the gate trench 41 can be more easily formed, so as to simplify the semiconductor device of the present application. manufacturing process.
位于栅极沟槽41的下部内的第一导电层25，可以外接源极电压，用以增加栅极沟槽41底部的电场，提高半导体器件的耐压。同时，第一绝缘层26的厚度可以大于第二绝缘层28的厚度，这可以保护栅极沟槽41的上部内的栅极不容易被击穿。The first conductive layer 25 located in the lower part of the gate trench 41 can be connected to a source voltage to increase the electric field at the bottom of the gate trench 41 and improve the withstand voltage of the semiconductor device. Meanwhile, the thickness of the first insulating layer 26 may be greater than that of the second insulating layer 28, which may protect the gate electrode in the upper portion of the gate trench 41 from being easily broken down.
可选的，位于栅极沟槽的下部内的第一导电层可以向上延伸至栅极沟槽的上部内，此时，在栅极沟槽的上部内，第二导电层可以是位于第一导电层的两侧、也可以是环绕包围第一导电层的上部、或者是环绕包围第一导电层的上部并覆盖第一导电层的上表面，该结构在本申请实施例中不再具体展示。Optionally, the first conductive layer located in the lower part of the gate trench may extend upward to the upper part of the gate trench, and at this time, in the upper part of the gate trench, the second conductive layer may be located in the first conductive layer. The two sides of the conductive layer may also surround and surround the upper portion of the first conductive layer, or surround the upper portion of the first conductive layer and cover the upper surface of the first conductive layer. This structure will not be specifically shown in the embodiments of the present application. .
位于源极沟槽42内的第三导电层29，第三导电层29与p型半导体层23和第三n型半导体层24连接，第三导电层29通过第三绝缘层30与源极沟槽42的侧壁位置处的第二n型半导体层22隔离。示例性的，第三绝缘层30的材料可以为氧化硅，第三导电层29的材料可以为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。第三绝缘层30的材料可以与第一绝缘层26的材料相同， 以使得第三绝缘层30和第一绝缘层26能够在同一制造工艺步骤中形成，进而简化半导体器件的制备工艺。The third conductive layer 29 located in the source trench 42, the third conductive layer 29 is connected to the p-type semiconductor layer 23 and the third n-type semiconductor layer 24, and the third conductive layer 29 is connected to the source trench through the third insulating layer 30 The second n-type semiconductor layer 22 at the location of the sidewall of the trench 42 is isolated. Exemplarily, the material of the third insulating layer 30 may be silicon oxide, and the material of the third conductive layer 29 may be at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten. The material of the third insulating layer 30 may be the same as that of the first insulating layer 26, so that the third insulating layer 30 and the first insulating layer 26 can be formed in the same manufacturing process step, thereby simplifying the manufacturing process of the semiconductor device.
位于第二n型半导体层22内且位于源极沟槽42的底部位置处的p型阱区31，p型阱区31与第三导电层29在源极沟槽42的底部位置相连接。p型阱区31与第二n型半导体层22形成pn结结构，增加源极沟槽底部附近的电场，将半导体器件的内的最高电场限定在源极沟槽42下方的pn结处，保护栅极沟槽41的上部内的栅极不容易被击穿，并提高器件的耐压。The p-type well region 31 located in the second n-type semiconductor layer 22 at the bottom position of the source trench 42 is connected to the third conductive layer 29 at the bottom position of the source trench 42 . The p-type well region 31 and the second n-type semiconductor layer 22 form a pn junction structure, increase the electric field near the bottom of the source trench, limit the highest electric field in the semiconductor device to the pn junction under the source trench 42, and protect the The gate in the upper portion of the gate trench 41 is not easily broken down, and the withstand voltage of the device is improved.

Claims (10)

  1. 半导体器件，包括：Semiconductor devices, including:
    半导体层，所述半导体层包括依次层叠的第一n型半导体层、第二n型半导体层、p型半导体层和第三n型半导体层；a semiconductor layer, the semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer and a third n-type semiconductor layer stacked in sequence;
    位于所述半导体层内且交替间隔设置的栅极沟槽和源极沟槽，所述栅极沟槽的底部和所述源极沟槽的底部均位于所述第二n型半导体层内；gate trenches and source trenches that are located in the semiconductor layer and are alternately spaced, and the bottoms of the gate trenches and the source trenches are both located in the second n-type semiconductor layer;
    位于所述栅极沟槽的下部内的第一导电层，所述第一导电层通过第一绝缘层与所述第二n型半导体层隔离，位于所述栅极沟槽的上部内的第二导电层，所述第二导电层通过第二绝缘层与所述p型半导体层、所述第三n型半导体层和所述第一导电层隔离；A first conductive layer in the lower portion of the gate trench, the first conductive layer being isolated from the second n-type semiconductor layer by a first insulating layer, and a first conductive layer in the upper portion of the gate trench Two conductive layers, the second conductive layer is isolated from the p-type semiconductor layer, the third n-type semiconductor layer and the first conductive layer by a second insulating layer;
    位于所述源极沟槽内的第三导电层，所述第三导电层与所述p型半导体层和所述第三n型半导体层连接，所述第三导电层通过第三绝缘层与所述源极沟槽的侧壁位置处的所述第二n型半导体层隔离；A third conductive layer located in the source trench, the third conductive layer is connected to the p-type semiconductor layer and the third n-type semiconductor layer, and the third conductive layer is connected to the third insulating layer through a third insulating layer. the second n-type semiconductor layer is isolated at the position of the sidewall of the source trench;
    位于所述第二n型半导体层内且位于所述源极沟槽的底部位置处的p型阱区，所述p型阱区与所述第三导电层在所述源极沟槽的底部位置相连接。a p-type well region located in the second n-type semiconductor layer and located at the bottom of the source trench, the p-type well region and the third conductive layer are at the bottom of the source trench location is connected.
  2. 如权利要求1所述的半导体器件，其中，所述栅极沟槽的深度与所述源极沟槽的深度相同。The semiconductor device of claim 1, wherein the depth of the gate trench is the same as the depth of the source trench.
  3. 如权利要求1所述的半导体器件，其中，所述源极沟槽的宽度大于所述栅极沟槽的宽度。The semiconductor device of claim 1, wherein a width of the source trench is greater than a width of the gate trench.
  4. 如权利要求1所述的半导体器件，其中，所述第一n型半导体层、所述第二n型半导体层、所述p型半导体层和所述第三n型半导体层均为碳化硅半导体层。The semiconductor device of claim 1, wherein the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer, and the third n-type semiconductor layer are all silicon carbide semiconductors layer.
  5. 如权利要求1所述的半导体器件，其中，所述第一绝缘层的厚度大于所述第二绝缘层的厚度。The semiconductor device of claim 1, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
  6. 如权利要求1所述的半导体器件，其中，所述第一绝缘层和所述第三绝缘层的材料均为氧化硅。The semiconductor device of claim 1, wherein materials of the first insulating layer and the third insulating layer are both silicon oxide.
  7. 如权利要求1所述的半导体器件，其中，所述第二绝缘层的材料为氧化 硅、氮化硅、氮氧化硅和氧化铪中的至少一种。The semiconductor device of claim 1, wherein a material of the second insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride and hafnium oxide.
  8. 如权利要求1所述的半导体器件，其中，所述第一导电层的材料为导电性多晶硅。The semiconductor device of claim 1, wherein the material of the first conductive layer is conductive polysilicon.
  9. 如权利要求1所述的半导体器件，其中，所述第二导电层的材料为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种；The semiconductor device according to claim 1, wherein the material of the second conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten;
    所述第三导电层的材料为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。The material of the third conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
  10. 如权利要求1所述的半导体器件，其中，所述第一导电层向上延伸至所述栅极沟槽的上部内。The semiconductor device of claim 1, wherein the first conductive layer extends upward into an upper portion of the gate trench.
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CN116598205A (en) * 2023-07-18 2023-08-15 凌锐半导体(上海)有限公司 Groove type MOSFET device and manufacturing method thereof
CN116598205B (en) * 2023-07-18 2023-10-03 凌锐半导体(上海)有限公司 Groove type MOSFET device and manufacturing method thereof

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