JP2013069783A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high withstand voltage of a termination region and a small area of the termination region.SOLUTION: The semiconductor device includes a first semiconductor layer 2 of a first conductivity type, a guard-ring layer 5 of a second conductivity type, a first FP insulating film 8, a second FP insulating film 8a, a first FP electrode 9, a second FP electrode 9a, a first interlayer insulating film 12, a gate insulating film 11, a gate electrode 13, a first electrode 16, and a second electrode 17. A second trench 7 extends from a first surface of the first semiconductor layer to the inside of the first semiconductor layer, surrounds a plurality of first trenches 6, and terminates an end of the guard-ring layer. The first FP electrode is provided in the first trench via the first FP insulating film. The second FP electrode is electrically connected to the first FP electrode and is provided so as to extend, via the second FP insulating film, from on the guard-ring layer toward the opposite side of the first trenches through on the side wall of the second trench on the first trenches side, on the bottom of the second trench.

Description

  Embodiments described herein relate generally to a power semiconductor device.

  A power semiconductor device is used as a switching element of a power supply unit (eg, a DC-DC converter) of a notebook personal computer or the like. These power semiconductor devices are required to have high breakdown voltage, low power consumption, and high-speed response. Further, these power semiconductor devices have an element region in which a semiconductor element is provided so that a current flows in the vertical direction, and a termination region that surrounds the element region on the outside. In order to increase the avalanche resistance of the power semiconductor device, the termination region is formed to have a higher breakdown voltage than the element region. In order to improve the breakdown voltage in the termination region, a p-type guard ring layer is formed at the termination of the p-type base layer. Thereby, the electric field concentration at the end of the p-type base layer is relaxed, and a high breakdown voltage is obtained. However, in order to obtain a high breakdown voltage, it is necessary to increase the area of the termination region in order to expand the depletion layer from the guard ring layer. For this reason, the profitability of the semiconductor chip is impaired. A power semiconductor device having a high withstand voltage and a reduced termination region is desired.

JP 2009-4668 A

  Provided is a semiconductor device in which a termination region has a high breakdown voltage and a small termination region.

  The semiconductor device according to the embodiment of the present invention includes a first conductivity type first semiconductor layer, a plurality of first trenches, a second conductivity type second semiconductor layer, and a first conductivity type third semiconductor layer. A semiconductor layer, a second conductivity type guard ring layer, a second trench, a first FP insulating film, a second FP insulating film, a first FP electrode, a second FP electrode, A first interlayer insulating film, a gate insulating film, a gate electrode, a second interlayer insulating film, a first electrode, and a second electrode are provided.

  The plurality of first trenches are formed in the first semiconductor layer from the first surface of the first semiconductor layer, and extend in a first direction parallel to the first surface. They are arranged in a second direction orthogonal to the direction of one. The second semiconductor layer of the second conductivity type is selectively provided on the first surface of the first semiconductor layer adjacent to one of the plurality of first trenches. The third semiconductor layer of the first conductivity type is selectively provided on the surface of the second semiconductor layer, is adjacent to the first trench, and is higher in concentration than the first conductivity type impurity of the first semiconductor layer. It has a concentration of one conductivity type impurity. The second conductivity type guard ring layer is adjacent to both ends of the second semiconductor layer in the first direction and has a second conductivity type impurity concentration lower than the second conductivity type impurity concentration of the second semiconductor layer. Have.

  The second trench extends from the first surface of the first semiconductor layer into the first semiconductor layer, surrounds the plurality of first trenches, and is wider than the width of the first trench in the second direction. It has a width and terminates the end of the guard ring layer opposite to the second semiconductor layer.

  The first FP insulating film is provided on the inner surface in a portion on the bottom side of the first trench from a portion in contact with the second semiconductor layer of the first trench. The second FP insulating film is provided so as to cover the guard ring layer and the entire inner surface of the second trench, and is connected to the first FP insulating film.

  The first FP electrode is provided in the first trench via the first FP insulating film. The second FP electrode is electrically connected to the first FP electrode, and passes through the second FP insulating film and from the guard ring layer to the first trench side sidewall of the second trench. The second trench is provided so as to extend on the side opposite to the first trench on the bottom of the second trench.

  The first interlayer insulating film covers a portion of the first FP electrode exposed from the first FP insulating film and a portion of the second FP electrode opposite to the second FP insulating film. Provided. The gate insulating film is provided on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer exposed on the sidewall of the first trench. The gate electrode is provided in the first trench through the gate insulating film and the first interlayer insulating film.

  The second interlayer insulating film is provided on the gate electrode, and is provided on the first FP electrode and the second FP electrode via the first interlayer insulating film. The first electrode is electrically connected to a second surface opposite to the first surface of the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer, the third semiconductor layer, and the second FP electrode.

1 is a schematic top view of a power semiconductor device according to a first embodiment. The main part schematic sectional drawing in the AA of FIG. 1 of the semiconductor device for electric power which concerns on 1st Embodiment, and the partially expanded view of (b) and (a). FIG. 2A is a schematic cross-sectional view of the main part of the power semiconductor device according to the first embodiment taken along the line BB in FIG. 2A, and FIG. 2B is the main part of the power semiconductor device taken along the line CC in FIG. FIG. The partially expanded view in the principal part schematic cross section corresponding to FIG. 2A of the power semiconductor device which concerns on 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description in the embodiments are schematic for ease of description, and the shape, size, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effect of the present invention can be obtained. Although the first conductivity type is described as n-type and the second conductivity type is described as p-type, the opposite conductivity types may be used. As a semiconductor, silicon will be described as an example, but it can also be applied to a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). As the insulating film, silicon oxide is described as an example, but other insulators such as silicon nitride (SiN), silicon oxynitride (SiNO), and alumina (Al ₂ O ₃ ) can also be used. When n-type conductivity is expressed by n ⁺ , n, and n ⁻ , the n-type impurity concentration is assumed to be lower in this order. Similarly, in the p-type, the p-type impurity concentration is low in the order of p ⁺ , p, and p ⁻ .

(First embodiment)
The power semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 1 is a schematic top view of a power semiconductor device 100 according to the first embodiment. 2A is a schematic cross-sectional view of the main part of the power semiconductor device 100 according to the first embodiment, taken along line AA in FIG. 1, and FIG. 2B is an enlarged view of the gate trench portion in FIG. . 3A is a schematic cross-sectional view of the main part of the power semiconductor device 100 according to the first embodiment, taken along line BB in FIG. 2A, and FIG. 3B is a cross-sectional view taken along line C- in FIG. It is a principal part schematic sectional drawing in the C line.

As shown in FIGS. 1 to 3, the power semiconductor device according to the present embodiment includes an n ⁺ -type drain layer 1, an n ⁻ -type drift layer 2 (first conductivity type first semiconductor layer), and a plurality of power semiconductor devices. A gate trench 6 (first trench), a p-type base layer 3 (second semiconductor layer of the second conductivity type), an n ^{+ type} source layer (third semiconductor layer of the first conductivity type), p ^{+ -type} contact layer 15, p ⁻ -type guard ring layer 5, termination trench 7 (second trench), p ⁻ -type semiconductor layer 5 a, p-type first channel stopper layer 3 a, n ⁺ Type second channel stopper layer 4 a, p ^{+ type} third channel stopper layer 15 a, first FP insulating film 8, second FP insulating film 8 a, first FP electrode 9, The second FP electrode 9a, the channel stopper electrode 10, the first interlayer insulating film 12, and the gate insulating film 1 A gate electrode 13, a gate wiring layer 18, a second interlayer insulating film 14, a drain electrode 16 (first electrode), a source electrode 17 (second electrode), a gate metal 19, and a channel. A stopper metal 20.

The n ^{− type} drift layer 2 is provided on the n ^{+ type} drain layer 1. For the n ⁺ -type drain layer 1, for example, an n ⁺ -type silicon substrate is used. The n ^{− type} drift layer 2 is formed on the n ^{+ type} silicon substrate by epitaxial growth of silicon. The n ^{+ -type} silicon substrate becomes an n ⁺ -type drain layer 1 by being polished to a desired thickness in a later step. The stacked structure of the n ⁺ -type drain layer 1 and the n ⁻ -type drift layer 2 can also be prepared by epitaxially growing an n ⁺ -type drain layer on an n ⁻ -type silicon substrate. Alternatively, it can also be prepared by ion-implanting n-type impurities on the surface of the n ⁻ -type silicon substrate and thermal nucleic acid.

The plurality of gate trenches 6 are formed in the n ⁻ -type drift layer from the first surface opposite to the n ⁺ -type drain layer 1 of the n ⁻ -type drift layer 2, and are parallel to the first surface. (A) It extends | stretches in the Y direction (1st direction) perpendicular | vertical to the paper surface in (a), and is arranged in the X direction (2nd direction) in the figure orthogonal to a Y direction on the 1st surface. The p-type base layer 3 is adjacent to one gate trench 6 of the plurality of gate trenches 6 and is selectively provided on the first surface of the n ⁻ -type drift layer 2. In other words, the p-type base layer 3 is provided between the adjacent gate trenches 6 of the plurality of gate trenches 6 and is adjacent to the adjacent gate trenches. The p-type base layer 3 is, for example, a p-type diffusion layer formed by ion implantation of p-type impurities into the first surface of the n ⁻ -type drift layer 2 and subsequent heat treatment.

The n ^{+ -type} source layer 4 is selectively provided on the surface of the p-type base layer 3, is adjacent to the gate trench 6, and has an n-type impurity concentration higher than the n-type impurity concentration of the n ⁻ -type drift layer 2. . The n ^{+ -type} source layer is, for example, an n-type diffusion layer formed by ion implantation of n-type impurities on the surface of the p-type base layer 3 and subsequent heat treatment.

As shown in FIG. 3A, the p-type guard ring layer 5 is provided on the first surface of the n ⁻ -type drift layer 2 adjacent to both outer ends of the p-type semiconductor layer 3 in the Y direction. The p-type impurity concentration is lower than the p-type impurity concentration of the p-type base layer 3. Further, as shown in FIG. 3B, the p-type guard ring layer 5 is adjacent to both outer ends of the gate trench 6 in the Y direction, and adjacent to these between the gate trench 6 and a termination trench 7 described later. Provided. Further, as shown in FIG. 2A, the p-type guard ring layer 5 is formed between the outermost gate trench 6 and the terminal trench 7 described later in the X direction. Adjacent to each other.

p ⁺ -type contact layer 15, through the n ⁺ -type source layer 4 from adjacent n ⁺ -type surface of the source layer 4 and the n ⁺ -type source layer 4, is provided to reach the p-type base layer 3. That is, the P ^{+ -type} contact layer 15 penetrates the n ^{+ -type} source layer 4 to reach the p-type base layer and is electrically connected to the p-type base layer. The p ^{+ -type} contact layer 15 is also a p-type diffusion layer formed by ion implantation of p-type impurities on the surface of the n ^{+ -type} source layer 4 and subsequent heat treatment, for example. The p ^{+ -type} contact layer 15 has a higher p-type impurity concentration than the p-type base layer 3.

Termination trench 7, n ^- from the first surface forms the drift layer n ^- stretched shape drift layer, a plurality of gate trenches 6 by two sides and two sides along the Y direction along the X-direction surround. These four sides of the termination trench 7 have a width wider than the width in the X direction of the gate trench.

  Two sides along the X direction of the termination trench 7 terminate the end of the guard ring layer 5 opposite to the p-type base layer 3 in the Y direction. Furthermore, in the Y direction, the guard ring layer 5 is sandwiched between the side along the X direction of the termination trench and the gate trench 6.

  The two sides along the Y direction of the termination trench 7 terminate the end of the guard ring layer 5 opposite to the gate trench 6 in the X direction. That is, in the X direction, the guard ring layer 5 is sandwiched between the side along the Y direction of the termination trench and the outermost gate trench 6 of the gate trench 6.

The gate trench 6 and the termination trench 7 can be integrally formed in the same process. In this case, n ^- n from the first surface forms the drift layer 2 ^- depth extending in the shape drift layer 2 is the same in the gate trench 6 and the termination trench 7. That is, the bottoms of the gate trench 6 and the termination trench 7 are located at the same depth from the first surface of the n ⁻ -type drift layer 2.

  In addition, the distance between the gate trench 6 adjacent to the termination trench and the termination trench 7 among the plurality of gate trenches 6 in the X direction is formed to be the same as or narrower than the distance between the adjacent gate trenches 6. .

The p-type first channel stopper layer 3 a is provided adjacent to the outer peripheral edge of the first surface of the n ⁻ -type drift layer 2. The p-type first channel stopper layer 3 a is a p-type diffusion layer having the same p-type impurity concentration as the p-type base layer 3 and formed integrally with the p-type base layer 3 in the same process. .

The n ^{+ -type} second channel stopper layer 4a is selectively provided on the surface of the p-type first channel stopper layer 3a, and is separated from the end of the p-type first channel stopper layer on the gate trench 6 side. ing. second channel stopper layer 4a of n ⁺ form, the n ⁺ -type having a concentration of the source layer 4 and the same n-type impurity, the n ⁺ -type source layer 4 in the same process are integrally formed with n-type diffusion Is a layer.

The p ^{+ -type} third channel stopper layer 15 a is selectively provided on the surface of the p-type first channel stopper layer 3 a and is adjacent to the outer peripheral edge of the first surface of the n ⁻ -type drift layer 2. The n ^{+ -type} second channel stopper layer 4a and the gate trench 6 are adjacent to each other at the opposite end. In other words, the third channel stopper layer 15a of the p ⁺ form, from the surface of the second channel stopper layer 4a of the n ⁺ -type through the second channel stopper layer 4a of the n ⁺ type (or through it) p The first channel stopper layer 3a having a shape is reached and electrically connected to the first channel stopper layer 3a having a p-type. The p ^{+ -type} third channel stopper layer 15a has the same p-type impurity concentration as the p ^{+ -type} contact layer 15 and is formed integrally with the p ^{+ -type} contact layer in the same process. Is a layer.

The p ⁻ -type semiconductor layer 5 a is provided on the first surface of the n ⁻ -type drift layer 2 between the termination trench 7 and the p-type first channel stopper layer 3 a so as to be adjacent thereto. p ^- type semiconductor layer 5a is, p ^- having a concentration of form the guard ring layer 5 and the same p-type impurity, p in the same step ^- is in the form the guard ring layer 5 and the p-type semiconductor layer which is formed integrally with .

The first FP insulating film 8 is formed in a portion of the gate trench 6 in contact with the p-type base layer 3, that is, a portion where the p-type base layer 3 is exposed on the side wall of the gate trench 6, and a portion below the gate trench 6. Cover all 6 inside surfaces. In other words, the first FP insulating film 8 is provided under the gate trench 6 so as to cover the portion of the n ⁻ -type drift layer 2 exposed on the inner surface of the gate trench 6. The first FP insulating film 8 is silicon oxide, and is formed by thermal oxidation or a CVD (Chemical Vapor Deposition) method. Instead of silicon oxide, silicon nitride, silicon oxynitride, alumina, or the like can be used.

The second FP insulating film 8a is provided so as to cover the p-type guard ring layer 5, the entire inner surface of the termination trench 7, the p ⁻ -type semiconductor layer 5a, and the p-type first channel layer 3a. Are connected to the first FP insulating film 8. The second FP insulating film 8a is silicon oxide and is integrally formed in the same process as the first FP insulating film 8. The first FP insulating film 9 and the second FP insulating film 9a are formed thicker than a gate insulating film 11 described later in order to prevent dielectric breakdown at the tip of the gate trench 6 and the tip of the termination trench 7. The

The first FP electrode 9 is provided in the gate trench 6 along the Y direction via a first FP insulating film. The first FP electrode 9 is not only provided at the portion where the inner surface in the gate trench 6 is exposed by the n ⁻ -type drift layer 2, but the inner surface in the gate trench 6 is exposed by the p-type base layer 3. It is also provided in the part. The first FP electrode is made of, for example, conductive polysilicon.

The second FP electrode 9a passes over the side wall of the termination trench 7 on the gate trench 6 side from the p ^{− type} guard ring layer 5 via the second FP insulating film 8a and on the bottom of the termination trench 7. The p-type first channel layer 3 a (or the side opposite to the gate trench 6) is provided so as to extend. The second FP electrode 9a is electrically connected to the first FP electrode 8. The second FP electrode 9a is made of conductive polysilicon, and is formed integrally with the first FP electrode 9 in the same process.

The channel stopper electrode 10 is formed on the p-type first channel stopper layer 3a via the second FP insulating film, on the side wall of the termination trench 7 opposite to the gate trench 6 and on the sidewall of the termination trench 7. The bottom portion is provided so as to extend toward the gate trench 6. The channel stopper electrode 10 is separated from the second FP electrode on the bottom of the termination trench 7. The channel stopper electrode 10 is electrically connected to the p-type first channel stopper layer 3a. As will be described later, the channel stopper electrode 10 is electrically connected to the p-type first channel stopper layer 3a through the channel stopper metal 20 and the p ^{+ -type} third channel stopper layer. The channel stopper electrode 10 is also made of conductive polysilicon and is formed integrally with the first FP electrode 9 and the second FP electrode in the same process.

  The first interlayer insulating film 12 is opposed to the portion of the first FP electrode 9 exposed from the first FP insulating film 8, that is, the portion of the inner surface of the gate trench 6 where the p-type base layer 3 is exposed. A portion of the first FP electrode 9 is provided so as to cover the surface. The first interlayer insulating film 12 is connected to the first FP insulating film and insulates the first FP electrode 9 from the periphery together with the first FP insulating film. The first interlayer insulating film 12 is on the surface of the second FP electrode opposite to the second FP insulating film, and on the surface of the channel stopper electrode 10 opposite to the second FP insulating film. , So as to cover. The first interlayer insulating film is silicon oxide like the first FP insulating film.

The gate insulating film 11 is provided on the n ⁻ -type drift layer 2, the p-type base layer 3, and the n ^{+ -type} source layer 4 exposed on the side wall of the gate trench 6, and is connected to the first FP insulating film. . The gate insulating film 11 is silicon oxide, and is formed integrally with the first interlayer insulating film by, for example, thermal oxidation in the same process as the first interlayer insulating film 12. Silicon oxide can be formed by CVD in addition to thermal oxidation. Similar to the first FP insulating film 8 and the second FP insulating film 8a, an insulating film having a high dielectric constant such as silicon nitride, silicon oxynitride, or alumina can be used instead of silicon oxide.

The gate electrode 13 is provided in the gate trench 6 via the gate insulating film 11 and the first interlayer insulating film. The gate electrode 13 is provided to face the n ⁻ -type drift layer 2, the p-type base layer 3, and the n ^{+ -type} source layer 4 exposed on the side wall of the gate trench 6 with the gate insulating film 11 interposed therebetween. Further, the gate electrode 13 is provided between the first FP electrode 9 and the p-type base layer 3 in the X direction, and the first FP electrode 9 and the first FP electrode 9 are interposed via the first interlayer insulating film 12. opposite. Further, the gate electrode 13 is provided on the first FP insulating film 8. The gate electrode 13 is made of, for example, conductive polysilicon.

  The gate wiring layer 18 is provided on the second FP electrode 9 a via the first interlayer insulating film 12, on the p-type guard ring layer 5, on the side wall of the termination trench 7 on the gate trench 6 side, and on the termination Extending in the X direction while covering the bottom of the trench 7. Further, the gate wiring layer 18 extends in the X direction on the end portion on the terminal trench side of the first FP electrode 9 provided in the plurality of gate trenches 6 via the first interlayer insulating film 12. To do. The gate wiring layer 18 is disposed on the p-type base layer 3 via the interlayer insulating film 11a. The interlayer insulating film 11a is integrally formed by the same process as the gate insulating film 11. The gate wiring layer 18 is electrically connected to the gate electrode 13 at the end of the gate trench 6 in the Y direction. The gate wiring layer 18 is made of conductive polysilicon and is formed integrally with the gate electrode 13 in the same process.

  The second interlayer insulating film 14 is provided on the gate electrode 13 and insulates the gate electrode 13 from the outside of the gate trench 6. The second interlayer insulating film 14 is provided on the first FP electrode 9 via the first interlayer insulating film 12. The second interlayer insulating film 14 is provided so as to cover the second FP electrode 9 a and the channel stopper electrode 10 with the first interlayer insulating film 12 interposed therebetween. Further, the second interlayer insulating film 14 is provided so as to cover the gate wiring layer 18. Similar to the first interlayer insulating film, the second interlayer insulating film is formed of silicon oxide. Silicon oxide can be formed by thermal oxidation or CVD.

The drain electrode 16 is electrically connected to the surface of the n ⁺ -type drain layer 1 opposite to the n ⁻ -type drift layer 2.

The source electrode 17 is electrically connected to the n ^{+ -type} source electrode 4 and the p ^{+ -type} contact layer 15 through the opening of the second interlayer insulating film 14. The source electrode 17 is electrically connected to the p-type base layer 3 via the p ^{+ -type} contact layer 15. The source electrode 17 is electrically connected to the second FP electrode through the opening of the second interlayer insulating film 14 in the termination trench 7. As a result, the first FP electrode 9 and the second FP electrode 9 a are kept at the same potential as the source electrode 17.

  The gate metal 19 is provided on the gate wiring layer 18 so as to extend in the X direction along the gate wiring layer 18 via the second interlayer insulating film 14. The gate metal 19 is electrically connected to the gate wiring layer 18 through an opening extending in the X direction of the second interlayer insulating film 14 in the termination trench 7. As a result, the gate electrode 13 in the gate trench 6 is drawn out to the gate pad via the gate wiring layer 18.

The channel stopper metal 20 is electrically connected to the channel stopper electrode 10 and the p ^{+ -type} third channel stopper layer 15 a outside the termination trench 7 through the opening of the second interlayer insulating film 14. . Therefore, the channel stopper electrode 10 is electrically connected to the p-type first channel stopper layer via the channel stopper metal 20 and the p ^{+ -type} third channel stopper layer 15a. The p-type first channel stopper layer 3a and the p ^{+ -type} third channel stopper layer 15a have the same potential as the drain electrode through the side end portion of the chip.

  The drain electrode 16, the source electrode 17, the gate metal 19, and the channel stopper metal 20 may be any commonly used metal, such as copper or aluminum.

  Next, the operation of the power semiconductor device 100 according to this embodiment will be described. The power semiconductor device 100 according to the present embodiment is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). When a positive voltage exceeding a threshold value with respect to the source electrode 17 is applied to the gate electrode 13 while a positive voltage is applied to the drain electrode 16 with respect to the source electrode 17, the gate of the p-type base layer 3 is applied. A channel layer is formed in a portion facing the electrode 13. As a result, a current flows from the drain electrode 16 toward the source electrode 17, and the power semiconductor device 100 according to the present embodiment is turned on.

When a voltage lower than the threshold value is applied to the gate electrode 13, the channel layer formed in the p-type base layer 3 disappears, and the current flowing from the drain electrode 16 to the source electrode 17 is cut off. The power semiconductor device 100 is turned off. When power semiconductor device 100 is turned off, a depletion layer extends from the junction between p-type base layer 3 and n ⁻ -type drift layer 2 toward n ⁻ -type drift layer 2.

In general, in the conventional MOSFET, since the junction between the p-type base layer 3 and the n ⁻ -type drift layer 2 has a curvature at the terminal portion of the p-type base layer 3, electric field concentration occurs at this junction. For this reason, breakdown occurs before the depletion layer extends sufficiently at the terminal portion of the p-type base layer 3, and the breakdown voltage becomes lower than other portions. Therefore, a p ^{− type} guard ring layer 5 having a p type impurity concentration lower than that of the p type base layer 3 is provided adjacent to the terminal portion of the p type base layer 3. As a result, the portion where the electric field concentration occurs moves from the terminal portion of the p-type base layer 3 to the terminal portion of the p-type guard ring layer 5. Further, since the concentration of the p-type impurity in the p-type guard ring layer 5 is lower than that in the p-type base layer 3, the electric field concentration at the terminal portion of the p-type guard ring layer 5 is alleviated.

However, the higher the breakdown voltage, the more the region where the depletion layer sufficiently extends at the terminal end is required. That is, a termination region in which a depletion layer extends from the p ^{− type} guard ring layer 5 along the surface of the n ^{− type} drift layer 2 is required. This becomes an ineffective region where no current flows during the operation of the MOSFET. Therefore, as the breakdown voltage is improved, the productivity or profitability of the MOSFET chip is impaired.

In the power semiconductor device 100 according to the present embodiment, the p ⁻ -type guard ring layer 5 is terminated by the termination trench 7 at the end opposite to the p-type base layer 3. The second FP electrode 9a passes over the side wall of the termination trench 7 on the gate trench 6 side from the p ^{− type} guard ring layer 5 via the second FP insulating film 8a and on the bottom of the termination trench 7. The p-type first channel layer 3a (or the side opposite to the gate trench 6) is provided so as to extend.

Since the second FP electrode 9a is at the same potential as the source electrode, a depletion layer is formed in the n ^{− type} drift layer 2 from the p ^{− type} guard ring layer 5 to the bottom of the termination trench 7 by the field plate effect. Will grow. Compared with the conventional termination structure in which the p ⁻ -type guard ring layer 5 is not terminated by the termination trench 7, the termination structure according to the present embodiment has no pn junction having a curvature. Electric field concentration hardly occurs. For this reason, compared with the conventional termination structure, an equivalent breakdown voltage can be obtained even if the termination region extending the depletion layer is small. That is, it is possible to narrow the width of the termination trench 7 in the X direction and the Y direction. Therefore, the power semiconductor device 100 according to the present embodiment can reduce the area of the termination region while maintaining a high breakdown voltage, thereby improving productivity.

In the power semiconductor device 100 according to the present embodiment, the channel stopper electrode 10 is connected to the gate trench 6 of the termination trench 7 from the p-type first channel stopper layer 3a via the second FP insulating film. It is provided so as to extend toward the gate trench 6 on the bottom of the termination trench 7 through the side wall on the opposite side. The channel stopper electrode 10 is electrically connected to the p-type first channel stopper layer 3a through the channel stopper metal 20 and the p ^{+ -type} third channel stopper layer 15a. Therefore, the end of the channel stopper electrode 10 on the termination trench 7 has the same potential as the drain electrode 16 as described above.

Thus, the depletion layer extending from the p ⁻ -type guard ring layer 5 along the bottom of the termination trench 7 into the n ⁻ -type drift layer 2 is more p-type than the end of the channel stopper electrode 10 on the termination trench 7. It does not spread to the first channel stopper layer side. That is, even if the power semiconductor device 100 reaches the withstand voltage (breakdown) in the termination region, the depletion layer extending from the p ⁻ -type guard ring layer 5 does not reach the end of the chip. High reliability.

  The first FP electrode provided below the gate trench 6 is disposed between the gate electrode 13 and the drain electrode 16 and has the same potential as the source electrode. For this reason, the first FP electrode functions as a field plate electrode, and the gate-drain capacitance is reduced. Therefore, the switching response of the power semiconductor device 100 is high.

  The first FP insulating film is formed thicker than the gate insulating film 11. This is to prevent dielectric breakdown at the bottom of the gate trench. The second FP insulating film is also formed thick for the same reason.

  A gate metal 19 is provided on the gate wiring layer 18 along the X direction. This is because the gate resistance caused by the gate wiring layer 18 is reduced by using a metal material.

  The gate wiring layer 18 is provided on the second FP electrode 9a via the first interlayer insulating film 12. As a result, the gate wiring layer 18 and the second FP electrode 9 a have a laminated structure in the termination trench 7. By doing so, similarly to the first FP electrode 9, the gate-drain capacitance caused by the gate wiring layer 18 can be reduced. Further, the flatness of the surface of the power semiconductor device 100 is improved. Furthermore, the area of the termination region can be reduced by stacking the gate wiring layer 18 and the second FP electrode 9a.

Adjacent intervals between the gate trenches 6 are sufficiently narrow so that depletion layers extending in the n ⁻ -type drift 2 are easily connected from the adjacent gate trenches 6. Thereby, the breakdown voltage is improved in the element region in which the gate trench 6 is formed. Similarly, the interval between the gate trench 6 adjacent to the termination trench 7 and the termination trench 6 among the plurality of gate trenches 6 is equal to or smaller than the interval between the adjacent gate trenches 6. Provided. By doing so, the breakdown voltage between the termination trench 7 and the adjacent gate trench 6 (that is, the breakdown voltage of the termination region) does not become lower than the breakdown voltage between the adjacent gate trench 6 (that is, the breakdown voltage of the element region). You can

(Second Embodiment)
A power semiconductor device according to a second embodiment will be described with reference to FIG. FIG. 4 is an enlarged view of a gate trench portion corresponding to FIG. 2B of the power semiconductor device 200 according to the present embodiment. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in the first embodiment, and description thereof is omitted. Differences from the first embodiment will be mainly described. The power semiconductor device 200 according to the present embodiment is the same as the power semiconductor device 100 according to the first embodiment except for the structure of the gate trench portion. For this reason, the figure corresponding to FIG. 1, FIG. 2 (a), and FIG. 3 of 1st Embodiment in this embodiment is abbreviate | omitted.

The power semiconductor device 200 according to the present embodiment is a MOSFET as in the first embodiment, and differs in the following points. As shown in FIG. 4, in the power semiconductor device according to the present embodiment, the amount of the first FP electrode 9 protruding to the portion where the side wall in the gate trench 6 is exposed by the p-type base layer 3 is small. . That is, in the power semiconductor device 200 according to the present embodiment, the portion where the first FP electrode 9 is opposed to the p-type base layer 3 in the gate trench 6 is compared with the power semiconductor device 100 of the first embodiment. almost none. Further, the gate electrode 13 is not sandwiched between the first FP electrode 9 and the p-type base layer 3 in the gate trench 6. The gate electrode 13 is provided in the gate trench 6 directly above the first FP electrode via the first interlayer insulating film 12 in the stacking direction (direction perpendicular to the first surface of the n ⁻ -type drift layer). It is done. The second interlayer insulating film 14 is provided on the first FP electrode 9 via the first interlayer insulating film 12 and the gate electrode 13.

  Also in the power semiconductor device 200 according to the present embodiment, the effects obtained in the power semiconductor device 100 according to the first embodiment can be similarly obtained. Further, the power semiconductor device 200 according to the present embodiment has a larger cross-sectional area of the gate electrode 13 extending in the Y direction than the power semiconductor device 100 according to the first embodiment. For this reason, since the power semiconductor device 200 according to the present embodiment has a lower gate resistance and a smaller delay of the gate signal than the power semiconductor device 100 according to the first embodiment, the switching response is high.

The embodiment of the present invention has been described above using the MOSFET as an example. An IGBT (Insulated Gate Bipolar Transistor) has the same structure as a structure in which a p ^{+ type} collector layer is further provided between the n ^{+ type} drain layer 1 and the drain electrode 16 in the MOSFET. Therefore, each of the above embodiments can be applied to an IGBT.

  Further, in the element region in which the gate trench 6 is formed, a pn diode region or an SBD (Schottky Barrier Diode) region can be formed. Accordingly, each of the above embodiments can be applied to a pn junction diode or SBD.

In the embodiments described above, MOSFET the n ^- between the shape drift layer 2 and the drain electrode 16 has been described in the case of providing the n ⁺ -type drain layer, n ^- form drift layer 2 and the drain electrode 16 and bonding directly Of course, it is also possible to have a structure as described above.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 n ^{+ type} drain layer 2 n ^{− type} drift layer (first semiconductor layer)
3 p-type base layer (second semiconductor layer)
3a p-type first channel stopper layer 4 n ^{+ -type} source layer (third semiconductor layer)
4a n ^{+ type} second channel stopper layer 5 p ^{− type} guard ring layer 5a p ^{− type} semiconductor layer 6 Gate trench (first trench)
7 Termination trench (second trench)
8, 8a First and second FP insulating films 9, 9a First and second FP electrodes 10 Channel stopper electrode 11 Gate insulating film 12 First interlayer insulating film 13 Gate electrode 14 Second interlayer insulating film 15 p ⁺ -Type contact layer 15a p ^{+ -type} third channel stopper layer 16 Drain electrode (first electrode)
17 Source electrode (second electrode)
18 Gate wiring layer 19 Gate metal 20 Channel stopper metal 100, 200 MOSFET

Claims (15)

A first semiconductor layer of a first conductivity type;
Formed in the first semiconductor layer from the first surface of the first semiconductor layer, extending in a first direction parallel to the first surface, and in the first direction on the first surface A plurality of first trenches arranged in a second direction orthogonal to
A second semiconductor layer of a second conductivity type adjacent to the first trench of the plurality of first trenches and selectively provided on the first surface of the first semiconductor layer; ,
A first conductivity type impurity selectively provided on a surface of the second semiconductor layer and adjacent to the first trench and having a first conductivity type impurity concentration higher than a concentration of the first conductivity type impurity of the first semiconductor layer. A third semiconductor layer of one conductivity type;
A second conductivity type guard adjacent to both ends of the second semiconductor layer in the first direction and having a second conductivity type impurity concentration lower than the concentration of the second conductivity type impurity of the second semiconductor layer. A ring layer,
A width that extends from the first surface of the first semiconductor layer into the first semiconductor layer, surrounds the plurality of first trenches, and is wider than a width of the first trench in the second direction A second trench that terminates an end of the guard ring layer opposite to the second semiconductor layer;
A first channel stopper layer of a second conductivity type provided adjacent to an outer peripheral edge of the first surface of the first semiconductor layer;
A first FP insulating film provided on an inner surface in a portion on the bottom side of the first trench from a portion in contact with the second semiconductor layer of the first trench;
A second FP insulating film provided to cover the guard ring layer, the entire inner surface of the second trench, and the first channel stopper layer, and connected to the first FP insulating film; When,
A first FP electrode provided in the first trench via the first FP insulating film;
Electrically connected to the first FP electrode, through the second FP insulating film, from the guard ring layer, through the side wall of the second trench on the first trench side, and A second FP electrode provided on the bottom of the second trench so as to extend toward the first channel stopper layer;
The second trench is opposite to the first trench from above the first channel stopper layer, electrically connected to the first channel stopper layer and via the second FP insulating film. A channel stopper electrode extending on the bottom of the second trench toward the first trench through the side wall of the second trench and spaced from the second FP electrode;
A portion of the first FP electrode exposed from the first FP insulating film, a surface of the second FP electrode opposite to the second FP insulating film, and the first of the channel stopper electrode A first interlayer insulating film provided to cover the surface opposite to the FP insulating film of 2;
A gate insulating film provided on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer exposed on a sidewall of the first trench;
A gate electrode provided in the first trench via the gate insulating film and the first interlayer insulating film;
A second interlayer insulating layer provided on the gate electrode and provided on the first FP electrode, the second FP electrode, and the channel stopper electrode via the first interlayer insulating film. A membrane,
A first electrode electrically connected to a second surface opposite to the first surface of the first semiconductor layer;
A second electrode electrically connected to the second semiconductor layer, the third semiconductor layer, and the second FP electrode;
A gate wiring layer provided on the second FP electrode along the first direction and via the first interlayer insulating film and electrically connected to the gate electrode;
With
The gate wiring layer is formed in the second trench;
The first FP insulating film and the second FP insulating film are formed thicker than the gate insulating film,
The first FP insulating film and the second FP insulating film are made of the same insulator formed integrally,
The first FP electrode, the second FP electrode, and the channel stopper electrode are made of the same conductive material formed integrally,
The gate electrode and the gate wiring layer are made of the same conductive material formed integrally,
The first trench and the second trench are integrally formed and pass through the second semiconductor layer from the first surface of the first semiconductor layer and are identical in the first semiconductor layer. Formed in depth,
In the second direction, an interval between the second trench among the plurality of first trenches and the second trench is an interval between the adjacent first trenches. The same or narrow,
The gate electrode is sandwiched between the first FP electrode and the second semiconductor layer in the second direction;
The second semiconductor layer has a second conductivity type impurity concentration higher than the concentration of the second conductivity type impurity of the second semiconductor layer, penetrates the third semiconductor layer from the surface of the third semiconductor layer, and passes through the third semiconductor layer. A second conductivity type contact layer leading to two semiconductor layers;
A second channel stopper layer of the first conductivity type formed on the surface of the first channel stopper layer integrally with the third semiconductor layer;
A third channel stopper layer of the second conductivity type formed on the surface of the first channel stopper layer integrally with the contact layer;
Further comprising
The third channel stopper layer is adjacent to the outer peripheral end of the first semiconductor layer, and is adjacent to the second channel stopper layer at an end opposite to the first trench. Semiconductor device. A first semiconductor layer of a first conductivity type;
Formed in the first semiconductor layer from the first surface of the first semiconductor layer, extending in a first direction parallel to the first surface, and in the first direction on the first surface A plurality of first trenches arranged in a second direction orthogonal to
A second semiconductor layer of a second conductivity type adjacent to the first trench of the plurality of first trenches and selectively provided on the first surface of the first semiconductor layer; ,
A first conductivity type impurity selectively provided on a surface of the second semiconductor layer and adjacent to the first trench and having a first conductivity type impurity concentration higher than a concentration of the first conductivity type impurity of the first semiconductor layer. A third semiconductor layer of one conductivity type;
A second conductivity type guard adjacent to both ends of the second semiconductor layer in the first direction and having a second conductivity type impurity concentration lower than the concentration of the second conductivity type impurity of the second semiconductor layer. A ring layer,
A width that extends from the first surface of the first semiconductor layer into the first semiconductor layer, surrounds the plurality of first trenches, and is wider than a width of the first trench in the second direction A second trench that terminates an end of the guard ring layer opposite to the second semiconductor layer;
A first FP insulating film provided on an inner surface in a portion on the bottom side of the first trench from a portion in contact with the second semiconductor layer of the first trench;
A second FP insulating film provided on the guard ring layer and over the entire inner surface of the second trench and connected to the first FP insulating film;
A first FP electrode provided in the first trench via the first FP insulating film;
Electrically connected to the first FP electrode, through the second FP insulating film, from the guard ring layer, through the side wall of the second trench on the first trench side, and A second FP electrode provided on the bottom of the second trench so as to extend toward the side opposite to the first trench;
A first FP electrode provided so as to cover a portion of the first FP electrode exposed from the first FP insulating film and a surface of the second FP electrode opposite to the second FP insulating film; 1 interlayer insulating film;
A gate insulating film provided on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer exposed on a sidewall of the first trench;
A gate electrode provided in the first trench via the gate insulating film and the first interlayer insulating film;
A second interlayer insulating film provided on the gate electrode and provided on the first FP electrode and on the second FP electrode via the first interlayer insulating film;
A first electrode electrically connected to a second surface opposite to the first surface of the first semiconductor layer;
A second electrode electrically connected to the second semiconductor layer, the third semiconductor layer, and the second FP electrode;
A power semiconductor device comprising: A first channel stopper layer of a second conductivity type provided adjacent to an outer peripheral edge of the first surface of the first semiconductor layer;
The second trench is opposite to the first trench from above the first channel stopper layer, electrically connected to the first channel stopper layer and via the second FP insulating film. A channel stopper electrode extending on the bottom of the second trench toward the first trench through the side wall of the second trench and spaced from the second FP electrode;
Further comprising
The first interlayer insulating film is provided so as to cover a surface of the channel stopper electrode opposite to the second FP insulating film,
The second interlayer insulating film is provided on the channel stopper electrode via the first interlayer insulating film,
The power semiconductor device according to claim 2.   4. The power semiconductor device according to claim 3, wherein the first FP electrode, the second FP electrode, and the channel stopper electrode are made of the same conductive material that is integrally formed.   The gate wiring layer further provided on the second FP electrode along the first direction and via the first interlayer insulating film and electrically connected to the gate electrode. The semiconductor device for electric power as described in any one of -4.   6. The power semiconductor device according to claim 5, wherein the gate electrode and the gate wiring layer are made of the same conductive material formed integrally.   The power semiconductor device according to claim 5, wherein the gate wiring layer is formed in the second trench.   The power semiconductor device according to claim 2, wherein the first FP insulating film and the second FP insulating film are thicker than the gate insulating film.   The power semiconductor device according to any one of claims 2 to 8, wherein the first FP insulating film and the second FP insulating film are made of the same insulator formed integrally.   The power semiconductor device according to claim 2, wherein the first interlayer insulating film and the gate insulating film are made of the same insulator formed integrally.   The first trench and the second trench are integrally formed and pass through the second semiconductor layer from the first surface of the first semiconductor layer and are identical in the first semiconductor layer. The power semiconductor device according to claim 2, wherein the power semiconductor device is formed with a depth.   In the second direction, an interval between the second trench among the plurality of first trenches and the second trench is an interval between the adjacent first trenches. The power semiconductor device according to any one of claims 2 to 11, which is the same or narrow.   The power semiconductor device according to claim 2, wherein the gate electrode is sandwiched between the first FP electrode and the second semiconductor layer in the second direction. .   The power semiconductor device according to any one of claims 2 to 12, wherein the gate electrode is provided immediately above the first FP electrode via the first interlayer insulating film in the stacking direction. The second semiconductor layer has a second conductivity type impurity concentration higher than the concentration of the second conductivity type impurity of the second semiconductor layer, penetrates the third semiconductor layer from the surface of the third semiconductor layer, and passes through the third semiconductor layer. A second conductivity type contact layer leading to two semiconductor layers;
A second channel stopper layer of the first conductivity type formed on the surface of the first channel stopper layer integrally with the third semiconductor layer;
A third channel stopper layer of the second conductivity type formed on the surface of the first channel stopper layer integrally with the contact layer;
Further comprising
The third channel stopper layer is adjacent to the outer peripheral end of the first semiconductor layer, and is adjacent to the second channel stopper layer at an end opposite to the first trench. The power semiconductor device according to any one of 2 to 12, 14, and 15.

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