CN216958042U

CN216958042U - LDMOS transistor structure

Info

Publication number: CN216958042U
Application number: CN202221318969.XU
Authority: CN
Inventors: 许凯; 张亦舒
Original assignee: ZJU Hangzhou Global Scientific and Technological Innovation Center
Current assignee: ZJU Hangzhou Global Scientific and Technological Innovation Center
Priority date: 2022-05-30
Filing date: 2022-05-30
Publication date: 2022-07-12
Anticipated expiration: 2032-05-30

Abstract

The utility model relates to the technical field of LDMOS (laterally diffused metal oxide semiconductor), and discloses an LDMOS transistor structure, which comprises: the device comprises a device body, a first grid electrode and a second grid electrode, wherein the device body comprises a substrate layer and an N-type drift region positioned above the substrate layer, and at least two second grid electrodes which are arranged at intervals according to a preset distance are arranged above the N-type drift region; the at least two second gates are arranged at unequal intervals, so that the breakdown voltage can be increased and the on-resistance can be reduced. According to the technical scheme, the breakdown voltage and on-resistance contradiction is broken through, the reliability of the power semiconductor chip and the power intelligent equipment is improved, and the safe and stable operation of a power grid is ensured.

Description

LDMOS transistor structure

Technical Field

The utility model relates to the technical field of LDMOS (laterally diffused metal oxide semiconductor), in particular to an LDMOS transistor structure.

Background

Compared with a power circuit formed by discrete devices, a power integrated circuit has the advantages of high integration level, high stability, low manufacturing cost and the like, and in recent years, the power integrated circuit has been a necessary choice for the power circuit due to the rapid development. The power integrated chip mainly adopts a special process based on BCD (BiCMOS/CMOS/DMOS), and the most critical lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device is used as a power switch to play a key role in the power integrated circuit. The LDMOS device has a large proportion, the power consumption is far larger than that of other analog and digital devices in a chip, and most of the loss of the whole power integrated circuit is occupied. The breakdown voltage and the performance of the on-resistance of the power supply integrated chip are directly related to important indexes such as conversion efficiency, switching frequency, stable operation time and the like of the power supply integrated chip. Meanwhile, the quality of the performance of the LDMOS device is also an important standard for judging the technical level of the BCD process. However, for DMOS type power devices, high breakdown voltage and low on-resistance are contradictory in design and process manufacturing.

The concrete points are as follows: generally, the performance of the LDMOS device is mainly limited by the on-resistance thereof, and the on-resistance of the device should be reduced as much as possible under the condition that the device satisfies a certain withstand voltage, but reducing the on-resistance of the device should reduce the length of the drift region and improve the doping concentration of the drift region, which, however, affects the breakdown voltage of the device; therefore, high breakdown voltage and low on-resistance are contradictory in design and process manufacturing.

Disclosure of Invention

The utility model aims to solve the problem that the design and the process manufacturing of the existing LDMOS device are mutually contradictory in terms of high breakdown voltage and low on-resistance, and provides an LDMOS transistor structure.

In order to achieve the above object, the present invention provides an LDMOS transistor structure comprising: the device comprises a device body, a first grid electrode and a second grid electrode, wherein the device body comprises a substrate layer, a P well region and an N type drift region, the P well region and the N type drift region are positioned on the surface of the substrate layer, the first grid electrode is arranged on the surface of the P well region, the drain electrode is arranged on the surface of the N type drift region, and the second grid electrode is arranged between the first grid electrode and the drain electrode and at least two second grid electrodes are arranged on the surface of the N type drift region at intervals; the at least two second gates are arranged at unequal intervals, so that when the device body is in an off state, voltages are applied to the at least two second gates to increase the breakdown voltage of the junction area of the P-well region and the N-type drift region, and when the device body is in an on state, voltages are applied to the at least two second gates to reduce the on-resistance of the device body.

As an implementation manner, the first gate includes a first gate oxide layer and a first gate electrode, the second gate includes a second gate oxide layer and a second gate electrode, the first gate oxide layer is disposed on the surface of the P-well region, the first gate electrode is disposed on the surface of the first gate oxide layer, the second gate oxide layer is disposed on the surface of the N-type drift region, and the second gate electrode is disposed on the surface of the second gate oxide layer; the thickness of the second grid electrode oxidation layer is larger than that of the first grid electrode oxidation layer.

As an implementation manner, the surface of the P-well region is further provided with a source, the source is located on a side of the first gate away from the second gate, the source includes a source N + region, a source P + region, and a source electrode, the source N + region and the source P + region are located on the surface of the P-well region, the source electrode is located on the surfaces of the source N + region and the source P + region, the drain includes a drain N + region and a drain electrode, the drain N + region is located on the surface of the N-type drift region, and the drain electrode is located on the surface of the drain N + region.

As an embodiment, the substrate layer further includes a buried N layer.

In an implementation manner, a silicon dioxide layer is further arranged between the substrate layer and the P-well region and between the substrate layer and the N-type drift region.

As an implementation manner, when there are i second gates, the 1 st to the ith second gates are arranged from left to right, the spacing distance between the first gate and the 1 st second gate is Δ 1, …, the spacing distance between the i-1 st second gate and the ith second gate is Δ i, and the spacing distance between the ith second gate and the drain is Δ i +1, wherein the distance values of Δ 1, …, Δ i, and Δ i +1 are sequentially increased from left to right, so that the boundary region of the P-well region and the N-type drift region is not broken down when the device body is in an off state and a voltage is applied to the plurality of second gates.

The utility model has the beneficial effects that: on the basis of the traditional LDMOS transistor structure, a series of second grid electrodes arranged at intervals according to a preset distance are added, on one hand, when the device body is in an off state, voltage is applied to the second grid electrodes, the depletion of an N-type drift region is increased, and therefore the whole device can bear higher voltage and increase breakdown voltage; on the other hand, when the device body is in an on state, a voltage is applied to the second grid electrode, more electrons can be attracted on the surface of the drift region, and a high-concentration electron accumulation layer is formed, so that the conductivity of the drift region is modulated, and the on-resistance is reduced; moreover, every time a grid is arranged, the grid is equivalent to one more peak of an electric field, and the peaks of the electric fields at two sides can be reduced, so that the breakdown voltage is increased, the breakdown voltage is equal to the integral of the electric field in the transverse direction, the electric fields at two sides are reduced, the integral electric field can be increased again, the breakdown voltage is increased, and the effect is better; the breakthrough of the contradiction between the breakdown voltage and the on-resistance is realized, the reliability of the power semiconductor chip and the power intelligent equipment is improved, and the safe and stable operation of a power grid is ensured.

Drawings

FIG. 1 is a diagram of a conventional LDMOS transistor structure;

FIG. 2 is a schematic diagram illustrating a second gate oxide layer having a thickness equal to a thickness of a first gate oxide layer in an LDMOS transistor structure according to an embodiment of the utility model;

FIG. 3 is a schematic structural diagram of an LDMOS transistor structure according to an embodiment of the present invention, in which the thickness of the second gate oxide layer is greater than that of the first gate oxide layer;

FIG. 4 is a schematic structural diagram of an LDMOS transistor structure with an N buried layer according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an LDMOS transistor structure with an added silicon dioxide layer according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an LDMOS transistor structure in the manufacturing process according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment provides a technical scheme: an LDMOS transistor structure comprising: the device comprises a device body, a first grid electrode and a second grid electrode, wherein the device body comprises a substrate layer, a P well region and an N type drift region, the P well region and the N type drift region are positioned on the surface of the substrate layer, the first grid electrode is arranged on the surface of the P well region, the drain electrode is arranged on the surface of the N type drift region, and the second grid electrode is arranged between the first grid electrode and the drain electrode and at least two second grid electrodes are arranged on the surface of the N type drift region at intervals; the at least two second gates are arranged at unequal intervals, so that when the device body is in an off state, voltages are applied to the at least two second gates to increase the breakdown voltage of the junction area of the P-well region and the N-type drift region, and when the device body is in an on state, voltages are applied to the at least two second gates to reduce the on-resistance of the device body.

The first grid electrode comprises a first grid oxide layer and a first grid electrode, the second grid electrode comprises a second grid oxide layer and a second grid electrode, the first grid oxide layer is arranged on the surface of the P well region, the first grid electrode is arranged on the surface of the first grid oxide layer, the second grid oxide layer is arranged on the surface of the N-type drift region, and the second grid electrode is arranged on the surface of the second grid oxide layer; in this embodiment, the thickness of the second gate oxide layer of the finally formed second gate may not be limited; in one embodiment, as shown in fig. 2, the thickness of the second gate oxide layer is equal to the thickness of the first gate oxide layer, so that when the device body is in the on state, the voltage applied to the second gate may be equal to the voltage applied to the first gate, wherein the second gate oxide layer and the first gate oxide layer may be formed simultaneously.

Further, a source electrode is further arranged on the surface of the P-well region, the source electrode is located on one side, away from the second gate electrode, of the first gate electrode, the source electrode comprises a source electrode N + region, a source electrode P + region and a source electrode, the source electrode N + region and the source electrode P + region are located in the P-well region, the source electrode is located on the surfaces of the source electrode N + region and the source electrode P + region, the drain electrode comprises a drain electrode N + region and a drain electrode, the drain electrode N + region is located in the N-type drift region, and the drain electrode is located on the surface of the drain electrode N + region.

Specifically, as shown in fig. 1, the device body includes a substrate layer 100, an N-type drift region 220 and a P-well region 210 located on a surface of the substrate layer 100, a source N + region 211 located on a surface of the P-well region 210, a source P + region 212, a source electrode 310 located on surfaces of the source N + region 211 and the source P + region 212, a first gate oxide layer 320 located on a surface of the P-well region 210, a first gate electrode 330 located on a surface of the first gate oxide layer 320, a drain N + region 221 located on a surface of the N-type drift region 220, and a drain electrode 340 located on a surface of the drain N + region 221, where the first gate oxide layer 320 and the first gate electrode 330 form a first gate.

In this embodiment, the breakdown voltage of the device body is mainly increased by increasing the breakdown voltage of the boundary region between the P-well region and the N-type drift region and the breakdown voltage of the boundary region between the N-type drift region and the drain region, because the electric field of these two regions is stronger and easier to break down than other regions in general, and the boundary region between the P-well region and the N-type drift region is a more mainly easier to break down part, and the electric field is stronger.

That is, in order to improve the breakdown voltage of the boundary region between the P-well region and the N-drift region and the boundary region between the N-drift region and the N-drift region, which is the most vulnerable place under normal conditions, in this embodiment, at least two second gates arranged at intervals of a predetermined distance as shown in fig. 2 are disposed above the N-drift region based on the conventional LDMOS transistor structure as shown in fig. 1, specifically, at least two second gates 350 arranged at intervals of a predetermined distance as shown in fig. 2 are disposed above the N-drift region 220, wherein, by disposing at least two second gates arranged at intervals of a predetermined distance, when the device body is in an off state, applying a voltage to at least two second gates can increase the depletion of the N-drift region so that the entire device can withstand a higher voltage, and the breakdown voltage is increased, and meanwhile, when the device body is in an on state, a high-concentration electron accumulation layer can be formed in the N-type drift region by applying voltages to at least two second gates, so that the conductivity of the N-type drift region is modulated, and the on resistance of the device body is reduced.

In this embodiment, the second gates arranged at unequal intervals are arranged to form an electric field peak corresponding to each second gate when a voltage is applied to the plurality of second gates, when the electric field peak increases, the electric field of the boundary region between the P-well region and the N-type drift region, and the electric field of the boundary region between the N-type drift region and the drain region can be reduced, and further, because the electric field of the boundary region between the P-well region and the N-type drift region is stronger, more second gates can be arranged near the P-well region than those near the drain side, and the formation of the peak of each second gate is equivalent to flattening the whole electric field distribution, thereby increasing the breakdown voltage of the whole device; that is to say, in order to ensure that the device is not broken down, more second gates may be disposed on the side of the N-type drift region close to the P-well region, so as to increase the breakdown voltage of the boundary region between the P-well region and the N-type drift region, and in addition, it is also necessary to ensure that the rightmost second gate is a certain distance away from the drain, because the electric field at the drain is weaker than the electric field at the boundary region between the P-well region and the N-type drift region, the electric field may be reduced without the need of the second gate close to the drain, otherwise, if the second gate close to the drain is too much or too close, the electric field may be increased, so that the two places of the second gate and the drain closest to the drain may be easily broken down.

The second gates arranged at intervals may specifically be arranged at non-equal intervals, where the non-equal interval arrangement includes that the interval distances of any adjacent second gates are not equal, or the interval distances of some adjacent second gates are equal, and the interval distances of some adjacent second gates are not equal, for example: when the number of the second gates is i, arranging from left to right from 1 st second gate to the ith second gate, wherein the spacing distance between the first gate and the 1 st second gate is Δ 1, …, the spacing distance between the i-1 st second gate and the ith second gate is Δ i, and the spacing distance between the ith second gate and the drain is Δ i +1, wherein the distance values of Δ 1, …, Δ i, and Δ i +1 sequentially increase from left to right, so that when the device body is in an off state and voltage is applied to the plurality of second gates, the boundary region between the P-well region and the N-type drift region, and the drain boundary region are not broken down.

For example, as shown in fig. 2 and fig. 3, when the number of the second gates is 5, the 1 st second gate 351, the 2 nd second gate 352, the 3 rd second gate, the 4 th second gate, and the 5 th second gate 355 may be arranged in a non-equidistant manner from left to right, and it can be seen that in this embodiment, the distance between the first gate and the 5 th second gate gradually increases from left to right, and this is set to ensure that only the boundary region between the P-well region and the N-type drift region, and the drain boundary region are not broken down.

In other embodiments, however, the non-equidistant spacing arrangement further comprises: the spacing distances of part of adjacent second grid electrodes are equal; specifically, the number and the spacing distance of the second gates may be determined according to different devices and application scenarios, for example, at least two second gates may not be arranged at equal intervals, but no matter how the distance value is set, the setting of the distance values Δ 1, Δ 2, …, Δ i +1 ensures that when a voltage is applied to the plurality of second gates when the device body is in an off state, the boundary region between the P-well region and the N-type drift region is not broken down, and the other regions, for example, the region between the ith second gate closest to the drain and the drain, are not broken down, which requires that more second gates be arranged on the side close to the first gate, and a sufficient distance is required between the ith second gate closest to the drain and the drain, that is, the distance value Δ i +1 is sufficiently large, or, it is also possible to ensure that there is sufficient distance between the i-1 th and i-th second gates close to the drain, between the i-th second gates and the drain, i.e. to ensure that the distance values Δ i and Δ i +1 are together large enough, etc. so that the device does not break down when the device body is in the off-state, by applying voltages to a plurality of the second gates, for example, it may be provided that the distance values Δ 1 and Δ 2 are equal, while the distance values Δ i and Δ i +1 are also equal but are both sufficiently larger than Δ 1 and Δ 2.

Further, in one embodiment, as shown in fig. 3, the thickness of the second gate oxide layer 360 is greater than the thickness of the first gate oxide layer 320, preventing the second gate oxide layer from being broken down when a voltage is applied in an off state or an on state; this also causes the voltage applied to the second gate to be greater than the voltage applied to the first gate when the device body is in the on state, thereby further reducing the on-resistance of the device body.

Specifically, when the device body is in an off state, in order to further prevent the second gate and the drain near the second gate from being broken down, and to ensure the safety of the drain, as shown in fig. 3, the thickness of the second gate oxide layer 360 may be greater than the thickness of the first gate oxide layer 320, because the voltage applied to the second gate may vary with the thickness of the second gate oxide layer, and if the thickness of the second gate oxide layer is greater, the applied voltage may be greater, that is, when the thickness of the second gate oxide layer is greater than that of the first gate oxide layer, the voltage applied to the second gate oxide layer is greater than that applied to the first gate oxide layer, which is to prevent the second gate from being broken down, so as to prevent the drain near the second gate from being broken down, and finally improve the breakdown voltage of the entire device. At this time, since the thickness of the second gate oxide layer 360 may be greater than the thickness of the first gate oxide layer 320, the voltage applied to the at least two second gates when the device body is in the on state also needs to be greater than the voltage applied to the first gate, and at this time, since the voltage applied to the at least two second gates is greater, the on-resistance of the device body may be further reduced.

It should be noted that, in this embodiment, how much voltage is specifically applied to the first gate and the second gate is different for different devices, and specifically, the voltage may be determined according to the thickness of the first gate oxide layer and the second gate oxide layer, the length of the N-type drift region, and the like, however, when the device body is in the on state, the applied voltage is greater than 0V, and when the thickness of the second gate oxide layer is equal to the thickness of the first gate oxide layer, the voltage applied to the at least two second gates and the voltage applied to the first gate may be equal; when the thickness of the second grid electrode oxide layer is larger than that of the first grid electrode oxide layer, the voltage applied to at least two second grid electrodes is larger than that applied to the first grid electrode; when the device body is in an off state, the voltage does not need to be applied to the first grid voltage, but the voltage applied to the at least two second grids needs to be less than 0V; for example, when a certain device is turned on, +5V is applied to the first grid electrode, and +10V is applied to the second grid electrode; when the grid is turned off, no voltage is applied to the first grid, and-5V is applied to the second grid.

Further, as shown in fig. 4, the substrate layer further includes an N buried layer 10, specifically, the N buried layer 10 is further disposed at a predetermined depth of the substrate layer, where the N buried layer 10 may form a reverse bias junction with the substrate layer, and a new electric field spike is introduced, so as to greatly improve the blocking performance of the device body at a longitudinal voltage.

Further, as shown in fig. 5, a silicon dioxide layer 20 is further disposed between the substrate layer and the P-well region and between the substrate layer and the N-type drift region, wherein the silicon dioxide layer 20 can achieve isolation between device bodies, has a small parasitic capacitance, and reduces a latch-up effect.

On the one hand, when the device body is in an off state, voltage is applied to the second grid electrode, and depletion of the N-type drift region is increased, so that the whole device can bear higher voltage and increase breakdown voltage; on the other hand, when the device body is in an open state, voltage is applied to the second grid electrode, more electrons can be attracted on the surface of the drift region, and a high-concentration electron accumulation layer is formed, so that the conductivity of the drift region is modulated, and the on-resistance is reduced; and, every time set up a second grid, it is equivalent to the peak of an electric field more, can reduce the peak of electric field of both sides of junction of P trap and N drift region, N drift region and drain junction, and in these two areas, because the peak of P well region and N type drift region junction is bigger, also the position of mainly puncturing, can set up more second grids on one side close to P well region, thus increase the breakdown voltage, and the breakdown voltage is equal to the integral of electric field on the horizontal, the electric field of both sides has reduced, the integral electric field can increase again, the breakdown voltage increases, the effect is better.

According to the technical scheme, the breakdown voltage and on-resistance contradiction is broken through, the reliability of the power semiconductor chip and the power intelligent equipment is improved, and the safe and stable operation of a power grid is guaranteed.

Based on the same concept, the embodiment of the utility model also provides a manufacturing method of the LDMOS transistor, which comprises the following steps of:

providing a substrate layer, and extending N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer; as shown in fig. 6 (a), a substrate layer 100 and an N-type epitaxial layer 200 are formed;

carrying out ion implantation on the N-type epitaxial layer to form a P well region and an N-type drift region; a P-well region 210 and an N-type drift region 220 formed as shown in fig. 6 (b);

forming a first grid electrode on the surface of the P-well region and at least two second grid electrodes which are arranged at intervals on the surface of the N-type drift region, wherein the at least two second grid electrodes which are arranged at intervals enable the breakdown voltage of the junction region of the P-well region and the N-type drift region to be increased when a subsequently formed device body is in an off state through applying voltage to the at least two second grid electrodes, and enable the on-resistance of the device body to be reduced when the subsequently formed device body is in an on state through applying voltage to the at least two second grid electrodes; a second gate oxide layer, a second gate electrode 350, a first gate oxide layer 320, and a first gate electrode 330 formed as shown in (c) of fig. 6;

performing ion implantation on the P well region to form a source N + region and a source P + region, performing ion implantation on the N-type drift region to form a drain N + region, forming source electrodes on the surfaces of the source N + region and the source P + region, and forming a drain electrode on the surface of the drain N + region, wherein at least two second grid electrodes which are arranged at intervals are positioned between the first grid electrode and the drain electrode; a source N + region 211 and a source P + region 212, a source electrode 310, a drain N + region 221, a drain electrode 340 formed as shown in (d) of fig. 6;

finally, after back-end process treatment, finishing process manufacturing to obtain a device body; the back-end process belongs to the prior art, and the detailed description is omitted in this embodiment.

The first grid electrode comprises a first grid oxide layer and a first grid electrode, the second grid electrode comprises a second grid oxide layer and a second grid electrode, the first grid oxide layer is located on the surface of the P well region, the first grid electrode is located on the surface of the first grid oxide layer, the second grid oxide layer is located on the surface of the N-type drift region, the second grid electrode is located on the surface of the second grid oxide layer, the source N + region and the source electrode form a source electrode, the drain N + region and the drain electrode form a drain electrode, and at least two second grid electrodes which are arranged at intervals are located between the first grid electrode and the drain electrode.

The step of forming a first gate on the surface of the P-well region and forming at least two second gates arranged at intervals on the surface of the N-type drift region specifically includes:

forming a first oxidation layer and at least two second oxidation layers arranged at intervals on the surface of the P well region, etching and removing the first oxidation layer, forming a first oxidation layer on the surface of the P well region to serve as a first grid oxidation layer, and forming a second oxidation layer on the surface of the second oxidation layer to obtain a second grid oxidation layer comprising two second oxidation layer surfaces; wherein the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer such that when the device body is in an off state, a voltage applied to the second gate is greater than a voltage applied to the first gate, thereby preventing the drain from being broken down;

and forming a first gate electrode on the surface of the first gate oxide layer and forming a second gate electrode on the surface of each second gate oxide layer to obtain a first gate comprising the first gate oxide layer and the first gate electrode and at least two second gates comprising the second gate oxide layer and the second gate electrode and arranged at intervals.

Further, a first oxide layer and at least two second oxide layers which are arranged at intervals are formed on the surface of the P well region at the same time; after the first oxide layer is removed by etching, a first oxide layer is formed on the surface of the P-well region to serve as a first gate oxide layer, and a second oxide layer is formed on the surface of the second oxide layer to obtain a second gate oxide layer including two second oxide layers.

In this embodiment, a substrate layer is provided, N-type doped silicon is epitaxially formed on a surface of the substrate layer, and the step of forming the N-type epitaxial layer specifically includes: providing a substrate layer, carrying out ion implantation at a preset depth of the substrate layer to form an N buried layer, and extending N type doped silicon on the surface of the substrate layer to form an N type epitaxial layer.

In this embodiment, a substrate layer is provided, N-type doped silicon is epitaxially formed on a surface of the substrate layer, and the step of forming the N-type epitaxial layer specifically includes: providing a substrate layer, depositing a silicon dioxide layer on the surface of the substrate layer, and extending N-type doped silicon on the surface of the silicon dioxide layer to form an N-type epitaxial layer.

The step of performing ion implantation on the N-type epitaxial layer to form a P well region and an N-type drift region specifically comprises the following steps: carrying out photoetching, ion implantation and diffusion treatment on the N-type epitaxial layer to form a P well region, wherein the region of the N-type epitaxial layer except the P well region is an N-type drift region; the processes such as photolithography, ion implantation, and diffusion belong to the prior art, and this embodiment will not be described in detail.

The step of forming a first gate on the surface of the P-well region and forming at least two second gates arranged at intervals on the surface of the N-type drift region specifically includes: forming a first grid on the surface of the P well region through thermal oxidation, deposition, photoetching and etching treatment, and forming at least two second grids arranged at intervals on the surface of the N-type drift region, wherein the thermal oxidation, deposition, photoetching and etching treatment are all the prior art, and detailed description is not provided in this embodiment.

Performing ion implantation on the P well region to form a source N + region and a source P + region, performing ion implantation on the N-type drift region to form a drain N + region, forming source electrodes on the surfaces of the source N + region and the source P + region, and forming a drain electrode on the surface of the drain N + region specifically comprises the following steps: forming a source electrode N + area and a source electrode P + area in the P well area through photoetching and ion implantation, forming a drain electrode N + area in the N-type drift area, depositing metal electrodes on the surfaces of the source electrode N + area and the source electrode P + area to form a source electrode, and depositing metal electrodes on the surface of the drain electrode N + area to form a drain electrode; the metal electrode may be NiPt, and photolithography and ion implantation are the prior art, and this embodiment will not be described in detail.

Providing a substrate layer, extending N-type doped silicon on the surface of the substrate layer in an epitaxial manner, and forming an N-type epitaxial layer specifically comprises the following steps: providing a substrate layer, carrying out ion implantation in the middle of the substrate layer to form an N buried layer penetrating through two sides of the substrate layer, and extending N type doped silicon on the surface of the substrate layer to form an N type epitaxial layer; or providing a substrate layer, depositing a silicon dioxide layer on the surface of the substrate layer, and extending N-type doped silicon on the surface of the silicon dioxide layer to form an N-type epitaxial layer.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.

Claims

1. An LDMOS transistor structure comprising: the device comprises a device body, a first grid electrode and a second grid electrode, wherein the device body comprises a substrate layer, a P well region and an N type drift region, the P well region and the N type drift region are positioned on the surface of the substrate layer, the first grid electrode is arranged on the surface of the P well region, the drain electrode is arranged on the surface of the N type drift region, and the second grid electrode is arranged between the first grid electrode and the drain electrode and at least two second grid electrodes are arranged on the surface of the N type drift region at intervals; the at least two second gates are arranged at intervals in a non-equal interval mode, so that when the device body is in an off state, voltage is applied to the at least two second gates to increase the breakdown voltage of a boundary region of the P-well region and the N-type drift region, and when the device body is in an on state, voltage is applied to the at least two second gates to reduce the on-resistance of the device body.

2. The LDMOS transistor structure of claim 1, wherein the first gate comprises a first gate oxide layer and a first gate electrode, the second gate comprises a second gate oxide layer and a second gate electrode, the first gate oxide layer is disposed on a surface of the P-well region, the first gate electrode is disposed on a surface of the first gate oxide layer, the second gate oxide layer is disposed on a surface of the N-type drift region, and the second gate electrode is disposed on a surface of the second gate oxide layer; the thickness of the second grid oxide layer is larger than that of the first grid oxide layer.

3. The LDMOS transistor structure of claim 1, wherein a source is further disposed on a surface of the P-well region, the source is located on a side of the first gate away from the second gate, the source comprises a source N + region, a source P + region and a source electrode, the source N + region and the source P + region are located on a surface of the P-well region, the source electrode is located on a surface of the source N + region and the source P + region, the drain comprises a drain N + region and a drain electrode, the drain N + region is located on a surface of the N-type drift region, and the drain electrode is located on a surface of the drain N + region.

4. The LDMOS transistor structure of claim 1, wherein the substrate layer further comprises a buried N layer.

5. The LDMOS transistor structure of claim 1, wherein a silicon dioxide layer is further disposed between the substrate layer and the P-well region and the N-type drift region.

6. The LDMOS transistor structure of claim 1, wherein when there are i second gates, the 1 st to the ith second gates are arranged from left to right, the separation distance between the first gate and the 1 st second gate is Δ 1, …, the separation distance between the i-1 st second gate and the ith second gate is Δ i, and the separation distance between the ith second gate and the drain is Δ i +1, wherein the distance values of Δ 1, …, Δ i +1 increase sequentially from left to right, such that the boundary region of the P-well region and the N-type drift region is not broken down when the device body is in an off state and a voltage is applied to the plurality of second gates.