CN104576732A - FinFET parasitic lateral double-diffused semiconductor device - Google Patents
FinFET parasitic lateral double-diffused semiconductor device Download PDFInfo
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- CN104576732A CN104576732A CN201310496879.9A CN201310496879A CN104576732A CN 104576732 A CN104576732 A CN 104576732A CN 201310496879 A CN201310496879 A CN 201310496879A CN 104576732 A CN104576732 A CN 104576732A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 230000003071 parasitic effect Effects 0.000 title claims abstract description 12
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- 238000009792 diffusion process Methods 0.000 claims abstract description 5
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- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
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- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses a FinFET parasitic lateral double-diffused semiconductor device which comprises a semiconductor substrate, fin structures positioned on the semiconductor substrate, first well regions and second well regions arranged in parallel in the fin structures, source regions positioned in the second well region, shallow trench isolation structures and a drain region all positioned in the first well region, and gate electrodes spanning across the fin structures, wherein the doping types of the first well region and the second well region are different; each shallow trench isolation structure is positioned between the source region and the drain region; each gate electrode partially covers the first well region, the second well region and the shallow trench isolation structure; each fin structure has two separated branch fin structures on one side of the drain region, so as to accelerate the diffusion of ions. The semiconductor device provided by the invention improves the breakdown voltage on the side surfaces of the source regions of an LDMOS device for producing FinFet.
Description
Technical field
The present invention relates to cross bimoment (Lateral Double Diffused MOSFET, LDMOS) technical field, particularly the LDMOS device structure of a kind of parasitic FinFET.
Background technology
Along with the development of semiconductor technology, cross bimoment (LDMOS) device is widely used in power integrated circuit because it has good short-channel properties.LDMOS device is applicable to being applied to RF(radio frequency very much) base station and power MOSFET (mos field effect transistor) conversion.In the application of RF technology, because LDMOS has high power performance, high-gain, the excellent linearity (linearity) and low manufacturing cost, LDMOS device is mainly used in base station circuitry.In the application of power MOSFET, such as, in DC-CD transducer, LDMOS device has outstanding conversion performance, and LDMOS device can reduce transition loss compared with other power converter.Therefore, LDMOS technology is that base station of new generation brings higher power PAR, more high-gain and the linearity, simultaneously for multimedia service brings higher data transmission rate.
Because LDMOS device is generally used for power circuit, such as, in RF technology and power MOSFET s device, power circuit needs to obtain high-voltage power and amplifies and larger power output, and therefore LDMOS device must can bear higher voltage.Along with the extensive use power integrated circuit of LDMOS, also more and more higher to the device performance requirements of LDMOS, require the puncture voltage of higher LDMOS device, also may require to increase threshold drift and good performance, in a word, more and more urgent to the demand of the LDMOS device with higher puncture voltage.Existing LDMOS device is difficult to meet the requirement with high breakdown voltage.
Along with the challenge constantly reduced from manufacture and design aspect of semiconductor device impels three dimensional design as the development of FinFET (FinFET), in the manufacture craft of FinFET, LDMOS device is transformed into fin structure device by planar device usually, LDMOS planar technique is after changing FinFET technique into, and the puncture voltage of LDMOS device will reduce.Therefore, the puncture voltage how improving LDMOS device in FinFET technique is urgent problem.
As the plan structure schematic diagram of LDMOS device that Fig. 1 is the FinFET made according to prior art.As shown in Figure 1, the LDMOS device of FinFET comprises source electrode 100, grid 101, drain electrode 102, and is positioned at the fin structure 103 below grid 101 and drain electrode 102, the isolated area (STI) 104 between grid 101 and drain electrode 102.As the cross-sectional view of LDMOS device that Fig. 2 A-2B is the FinFET made according to prior art.Accompanying drawing 2A-2B is for doing the cross-sectional view of the LDMOS device of the FinFET that cross section obtains along the X-direction in Fig. 1.For NLDMOS device, as shown in Figure 2 A, LDMOS device comprises substrate 200, source region is formed in substrate, P trap 201 in substrate, be positioned at the field oxide (STI) 202 of substrate 200 and P trap 201 top layer intersection, be positioned at the drift region (N trap) of Semiconductor substrate 200, drift region field oxide layer 203 is coated with above drift region, be positioned at the source region 204 of well region 201, be positioned at the drain region 205 of drift region, be positioned at the grid structure 206 above substrate 200, source region, drain region and grid can be distinguished composition and draw source electrode, drain electrode and grid.Fig. 2 B is the cross-sectional view of PLDMOS device, and only needing to do simple deformation compared with Fig. 2 A can realize.
Therefore, need the LDMOS semiconductor device of a kind of novel FinFET, so that the puncture voltage of the LDMOS device in FinFET technique can be improved.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to effectively solve the problem, the cross bimoment of a kind of parasitic FinFET, comprising: Semiconductor substrate; Be positioned at the fin structure in described Semiconductor substrate; Be positioned at the first well region and the second well region that described fin structure is set up in parallel, described first well region is different from the doping type of described second well region; Be positioned at the source region of described second well region; Be positioned at fleet plough groove isolation structure and the drain region of described first well region, described fleet plough groove isolation structure is between described source region and described drain region; Across the grid of described fin structure, described grid is the first well region described in cover part and described second well region also, and part covers described fleet plough groove isolation structure, wherein, described fin structure has the Liang Ge branch fin structure be separated from each other in side, described drain region, to accelerate the diffusion of ion.
Preferably, the center between the described fin in the center of described two fin structures in side, described drain region and channel region on the same line.
Preferably, described two fin structures being positioned at side, described drain region increase the dropping distance of side, described drain region voltage.
Preferably, described two fin structures being positioned at side, described drain region improve the puncture voltage of side, drain region.
Preferably, also comprise the fin structure that multiple and described fin structure be arranged in parallel, two adjacent fin structures share a described branch fin structure.
Preferably, the center line of described branch fin structure aligns with the mid line of described two adjacent fin structures.
In sum, semiconductor device prepared in accordance with the present invention, increases voltage drop distance (falling distance) of side, drain region, to improve the breakdown voltage value of the side, LDMOS device source region of FinFET.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the plan structure schematic diagram of LDMOS device of the FinFET made according to prior art;
Fig. 2 A-2B is the cross-sectional view of LDMOS device of the FinFET made according to prior art;
Fig. 3 is the plan structure schematic diagram of LDMOS device of the FinFET made according to an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention improves the technique making semiconductor device structure to solve the problems of the prior art.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Herein." on " the direction type term on D score " left side " " right side " be relative to the orientation of the LDMOS of FinFET in accompanying drawing define (such as, left and right directions refer to the LDMOS of FinFET channel direction, it is parallel to substrate surface, above-below direction perpendicular to substrate surface).Further, be to be understood that, these directional terminology are relative concepts, and they are for relative description and clarification, the change in its orientation can placed according to the LDMOS of FinFET and correspondingly changing.
In order to solve the problems of the prior art, the present invention proposes the LDMOS semiconductor device structure of a kind of novel FinFET.Elaborate below in conjunction with accompanying drawing 3 pairs of the specific embodiment of the present invention.With reference to Fig. 3, the schematic diagram of the correlation step of the embodiment according to one aspect of the invention is shown.
Be described in detail below in conjunction with accompanying drawing 3 pairs of the specific embodiment of the present invention.With reference to Fig. 3, the plan structure schematic diagram of the LDMOS device of the FinFET made according to an embodiment of the invention is shown.In this embodiment, cross bimoment is N-type device, is specifically described the LDMOS structure of this embodiment below in conjunction with Fig. 3.
Fig. 3 is the plan structure schematic diagram of the LDMOS device according to an embodiment of the invention making, LDMOS device comprises Semiconductor substrate 300, source electrode 301, grid 302, drain electrode 303, and the fin structure 304 be positioned at below grid 301 and drain electrode 303, the isolated area (STI) 305 between grid 301 and drain electrode 303.Semiconductor substrate 300 comprises source region and drain region, forms source electrode and drain electrode respectively on source region and drain region.According to the semiconductor device structure that the present invention makes, add two fin structure 304a and 304b separately in side, drain region, to improve the ion diffuse in device.Simultaneously, in the such as device architecture shown in 3 figure, center between two fins in the center of side, drain region fin and channel region is on the same line, concrete, and two fin 304c in the center of the fin structure 304a of side, drain region and channel region and 304d center are on the same line.Semiconductor substrate surface is formed the grid 302 that part covers source region; Wherein, the preferred polysilicon of material of described grid 302.
The execution mode of cross bimoment is for N-type device, the invention provides a kind of LDMOS semiconductor device structure improving the FinFET of puncture voltage, as shown in Figure 3, compare the schematic top plan view with the LDMOS shown in Fig. 1, layout (layout) mode that the invention provides a kind of LDMOS semiconductor device from FinFET obtains high breakdown voltage, exactly the fin structure in Semiconductor substrate in the LDMOS of traditional F inFET is become center between two fins in the center of side, drain region fin and channel region on the same line, this device architecture increases voltage drop distance (falling distance) of side, drain region, to improve the breakdown voltage value of the side, LDMOS device source region of FinFET.Wherein, the LDMOS device structure of FinFET also comprises the fin structure that multiple and described fin structure be arranged in parallel, two adjacent fin structures share a described branch fin structure, and the center line of described branch fin structure aligns with the mid line of described two adjacent fin structures.
In this embodiment, the cross bimoment with FinFET is N-type device, is specifically described below to the LDMOS structure of the FinFET of this embodiment.
The LDMOS of FinFET is formed in Semiconductor substrate, and Semiconductor substrate is silicon substrate.In Semiconductor substrate, doping forms drift region (well region) and well region.Drift region (well region) is different with the doping type of well region.
Described substrate is P type substrate in the present embodiment, and its concrete doping content is not restrictive by the present invention.Concrete can being formed by epitaxial growth of Semiconductor substrate also can be wafer substrate.
The trap injection technology of employing standard forms P trap in the semiconductor substrate.P trap can be formed by high energy implantation process, also can by low-yield injection, collocation high-temperature thermal annealing process forms P trap.Source region and the body draw-out area of LDMOS device can be formed in trap.Drift region is similar with P trap generation type, can be formed by high energy implantation process, also can by low-yield injection, and collocation high-temperature thermal annealing process is formed.
Form P trap on a semiconductor substrate as tagma.In preferred embodiment, the doping content scope in tagma can be 10
15atom/cm
3~ 10
18atom/cm
3, such as doping content is set to 10
17atom/cm
3.For N raceway groove LDMOS, drift region is N-type doping.Also form drift region in the semiconductor substrate simultaneously, drift region is positioned at Semiconductor substrate, and between source electrode and drain electrode, drift region is generally light doping section, and the existence of drift region can provide the puncture voltage of LDMOS device, reduce the parasitic capacitance between source, drain electrode simultaneously, for N groove LDMOS, drift region is N-type doping, and its doping content is generally lower than the doping content of drain electrode, in a preferred embodiment, drift doping concentration scope can be 10
15atom/cm
3~ 10
18atom/cm
3.Namely the drift region field oxide layer of follow-up formation is the place formed above drift region, and described place is fleet plough groove isolation structure (STI).
In an embodiment of the present invention, be formed with silicon nitride layer and silicon oxide layer on a semiconductor substrate, there is the photoresist layer of drift region for mask, dry etching is adopted to etch away silicon nitride layer above drift region and silicon oxide layer successively, and silicon layer, to form groove structure, remove the photoresist layer with drift region pattern, adopt oxide layer deposit and the mode that polishes to form fleet plough groove isolation structure (STI), described fleet plough groove isolation structure is between described source region and described drain region.
Shallow trench isolation technology is adopted to form isolated area oxide layer on a semiconductor substrate.Well region and drift region is formed in Semiconductor substrate.
Described trap forms semiconductor material layer, and described in patterning, semiconductor material layer obtains fin structure.Then, formed across and surround the grid of described fin structure, described grid is drift region (N trap) and described P well region described in cover part simultaneously, and part covers described fleet plough groove isolation structure, wherein, there is the Liang Ge branch fin structure be separated from each other, to accelerate the ion diffuse in semiconductor device in side, described drain region.
In an embodiment of the present invention, inject and form well region and drift region in semiconductor lining body, well region and drift region can be injected by high-energy and be formed, also can by low-yield injection, and collocation high-temperature thermal annealing is formed.Well region, as tagma, injects P+ type impurity organizator draw-out area in tagma, and injects N+ type impurity formation source region.In drift region, inject N+ type impurity form drain region.Source region can be identical with the doping content in drain region, therefore, and the two formation of can synchronously adulterating.In a preferred embodiment, the N-type doping content scope in source region and drain region can be 10
18atom/cm
3~ 10
21atom/cm
3, such as doping content is set to 10
20atom/cm
3.
Last interlayer dielectric layer (not shown) on a semiconductor substrate, and on interlayer dielectric layer, form corresponding through hole, in described respective through hole, introduce metal can be connected grid, source electrode, drain electrode with Bulk with corresponding grid G, source S, drain D with body draw-out area.
The manufacture method of cross bimoment, also for N-type device, comprises the following steps
Step a: the trap injection technology adopting standard in P type substrate, forms P trap;
Step b: inject N-type impurity and form drift region on P type lining body;
Step c: the shallow ditch groove separation process or the thermal oxide growth technique that adopt standard, the active area of definition device, and form field oxide in place;
Steps d: form fin structure in P type substrate;
Step e: utilize the polysilicon deposition of standard and etching technics to form grid on fin structure;
Step f: inject P+ type impurity organizator in well region and draw district, injects N+ impurity formation source, drain electrode in well region and drift region;
Deposition forms dielectric layer, etching contact hole, in the contact hole depositing metal layers, etches the step such as plain conductor and passivation is all that technological means well-known to those having ordinary skill in the art is not just described in detail at this.
Above illustrated embodiment is only for NMOS, also can be applied in PMOS, and invention technician only needs to do simple deformation and can realize.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (6)
1. a transverse double-diffusion semiconductor device of parasitic FinFET, comprising:
Semiconductor substrate;
Be positioned at the fin structure in described Semiconductor substrate;
Be positioned at the first well region and the second well region that described fin structure is set up in parallel, described first well region is different from the doping type of described second well region;
Be positioned at the source region of described second well region;
Be positioned at fleet plough groove isolation structure and the drain region of described first well region, described fleet plough groove isolation structure is between described source region and described drain region;
Across the grid of described fin structure, described grid is the first well region described in cover part and described second well region also, and part covers described fleet plough groove isolation structure,
Wherein, described fin structure has the Liang Ge branch fin structure be separated from each other in side, described drain region, to accelerate the diffusion of ion.
2. the cross bimoment of parasitic FinFET as claimed in claim 1, it is characterized in that, the center between the described fin in the center of described two fin structures in side, described drain region and channel region on the same line.
3. the cross bimoment of parasitic FinFET as claimed in claim 1, is characterized in that, described two fin structures being positioned at side, described drain region increase the dropping distance of side, described drain region voltage.
4. the cross bimoment of parasitic FinFET as claimed in claim 1, is characterized in that, described two fin structures being positioned at side, described drain region improve the puncture voltage of side, drain region.
5. the cross bimoment of parasitic FinFET as claimed in claim 1, it is characterized in that, also comprise the fin structure that multiple and described fin structure be arranged in parallel, two adjacent fin structures share a described branch fin structure.
6. the cross bimoment of parasitic FinFET as claimed in claim 5, is characterized in that, the center line of described branch fin structure aligns with the mid line of described two adjacent fin structures.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428353A (en) * | 2015-12-17 | 2016-03-23 | 江南大学 | High-voltage ESD protective device provided with fin type LDMOS structure |
| EP3226297A1 (en) * | 2016-03-29 | 2017-10-04 | Semiconductor Manufacturing International Corporation (Shanghai) | High voltage esd device for finfet technology |
| EP3252814A1 (en) * | 2016-06-01 | 2017-12-06 | Semiconductor Manufacturing International Corporation (Shanghai) | Esd protection device and method |
| CN114078704A (en) * | 2020-08-18 | 2022-02-22 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and forming method thereof |
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| US20130062692A1 (en) * | 2011-09-14 | 2013-03-14 | Broadcom Corporation | Half-FinFET Semiconductor Device and Related Method |
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| CN114078704A (en) * | 2020-08-18 | 2022-02-22 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and forming method thereof |
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