KR20110078531A - High voltage semiconductor device and manufacturing method of high voltage semiconductor device - Google Patents

High voltage semiconductor device and manufacturing method of high voltage semiconductor device Download PDF

Info

Publication number
KR20110078531A
KR20110078531A KR1020090135361A KR20090135361A KR20110078531A KR 20110078531 A KR20110078531 A KR 20110078531A KR 1020090135361 A KR1020090135361 A KR 1020090135361A KR 20090135361 A KR20090135361 A KR 20090135361A KR 20110078531 A KR20110078531 A KR 20110078531A
Authority
KR
South Korea
Prior art keywords
region
ion implantation
forming
high voltage
device isolation
Prior art date
Application number
KR1020090135361A
Other languages
Korean (ko)
Inventor
고광영
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020090135361A priority Critical patent/KR20110078531A/en
Publication of KR20110078531A publication Critical patent/KR20110078531A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

In an embodiment, a high voltage semiconductor device may include: a plurality of device isolation regions defining an active region of the semiconductor substrate; A well region formed on a portion of an upper side of the semiconductor substrate; A body region formed on an upper portion of the well region; A diffusion region formed on an upper portion of the well region to be spaced apart from the body region by a predetermined distance; A high voltage device isolation region formed over a portion of the diffusion region and formed in a LOCOS field plate structure having a predetermined thickness; A gate insulating film formed from a portion of the body region to a portion of the high voltage device isolation region; And a gate formed on the gate insulating layer.

According to the embodiment, by forming the high voltage device isolation region in the LOCOS field plate structure instead of the SIT, the thickness can be easily adjusted, and the stepped structure can be formed in the linear structure. Thus, the current path can be appropriately formed, and the operation resistance can be prevented from increasing.

Description

High voltage semiconductor device and manufacturing method of high voltage semiconductor device

The embodiment relates to a high voltage semiconductor device and a method for manufacturing the high voltage semiconductor device.

In general, a shallow trench isolation (STI) structure is used to reduce the electric field of the gate edge portion of a high voltage semiconductor device, for example, an LDMOS (laterally diffused metal oxide semiconductor) to obtain a high voltage withstand voltage.

That is, the STI structure is formed between the drain region and the gate edge portion to increase the breakdown voltage by lengthening the current path.

However, since the thickness of the STI is formed thick and the STI forms a stepped structure, the current path is formed longer than necessary, and the operating resistance (On resistance) is increased.

In addition, when the N-drift region including the drain region is processed before the STI process, since the substrate is etched in the form of a trench, the surface concentration of the N-type diffusion region is reduced, which is also important to increase the operating resistance. It becomes a factor.

In the embodiment, in forming the high voltage device isolation region of the high voltage semiconductor device, by improving the stepped structure of the STI, the thickness and current path of the device isolation region can be easily adjusted, and the operation resistance is increased. The present invention provides a high voltage semiconductor device and a method for manufacturing the high voltage semiconductor device, which can minimize the decrease in the surface ion concentration of the diffusion region.

In an embodiment, a high voltage semiconductor device may include: a plurality of device isolation regions defining an active region of the semiconductor substrate; A well region formed on a portion of an upper side of the semiconductor substrate; A body region formed on an upper portion of the well region; A diffusion region formed on an upper portion of the well region to be spaced apart from the body region by a predetermined distance; A high voltage device isolation region formed over a portion of the diffusion region and formed in a LOCOS field plate structure having a predetermined thickness; A gate insulating film formed from a portion of the body region to a portion of the high voltage device isolation region; And a gate formed on the gate insulating layer.

A method of manufacturing a high voltage semiconductor device according to an embodiment may include forming a plurality of device isolation regions defining an active region of the semiconductor substrate; Forming a well region on an upper portion of the semiconductor substrate; Forming a body region on an upper portion of the well region; Forming a diffusion region on an upper portion of the well region to be spaced apart from the body region by a predetermined distance; Forming a high voltage device isolation region having a predetermined thickness on a portion of an upper portion of the diffusion region in a LOCOS (LOCal Oxidation of Silicon) field plate structure; Forming a gate insulating film from a portion of the body region to a portion of the high voltage device isolation region; And forming a gate on the gate insulating layer.

According to the embodiment, the following effects are obtained.

First, by forming the high voltage device isolation region in the LOCOS field plate structure instead of the SIT, the thickness can be easily adjusted and the stepped structure can be formed in the linear structure. Thus, the current path can be appropriately formed, and the operation resistance can be prevented from increasing.

Second, since the high voltage device isolation region is formed in a LOCOS field plate structure, the surface concentration of the diffusion region due to the trench etching may be prevented from being reduced. Therefore, an increase in operating resistance can be prevented.

A high voltage semiconductor device and a method of manufacturing the high voltage semiconductor device according to the embodiment will be described in detail with reference to the accompanying drawings.

Hereinafter, in describing the embodiments, detailed descriptions of related well-known functions or configurations are deemed to unnecessarily obscure the subject matter of the present invention, and thus only the essential components directly related to the technical spirit of the present invention will be referred to. .

In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure may be "on" or "under" the substrate, each layer (film), region, pad or pattern. "On" and "under" include both "directly" or "indirectly" formed through another layer, as described in do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

1 is a side cross-sectional view schematically illustrating a shape of a high voltage semiconductor device after the pad oxide layer 130 is formed according to an embodiment.

Referring to FIG. 1, a plurality of device isolation regions 120 defining active regions of the semiconductor substrate 100 are formed.

Thereafter, a well region 110 is formed between the upper portion of the semiconductor substrate 100 and the device isolation region 120.

The well region 110 is a high voltage well and is formed by doping with a high concentration of ions. For example, when the semiconductor substrate 100 is a first conductivity type sub substrate, the well region 110 may be of a first conductivity type or It may be a second conductivity type well region.

When the well region 110 is formed, a body region 112 is formed on a portion of the upper portion of the well region 110, and the body region 112 is spaced apart from the body region 112 by a predetermined interval to diffuse to a portion of the upper portion of the well region 110. Area 114 is formed.

The body region 112 may be formed to contact the device isolation region 120 on one side, and the diffusion region 114 may be formed to contact the device isolation region 120 on the other side.

In addition, the body region may be formed by implanting first conductivity type ions, and the diffusion region 114 may be formed by implantation of second conductivity type ions.

Next, a pad oxide layer 130 is formed on the semiconductor substrate 100.

2 is a side cross-sectional view schematically showing the shape of a high voltage semiconductor device after the pad nitride layer 140 is formed according to the embodiment.

As illustrated in FIG. 2, when the pad oxide layer 130 is formed, a pad nitride layer 140 is formed thereon.

3 is a side cross-sectional view schematically illustrating the shape of a high voltage semiconductor device after the pad oxide layer 130 and the pad nitride layer 140 are patterned to define a high voltage device isolation region according to an exemplary embodiment.

Referring to FIG. 3, a photoresist pattern (not shown) for opening a portion of the diffusion region 114 to form a high voltage device isolation region (see FIG. 4; The process proceeds to pattern the pad oxide layer 130 and the pad nitride layer 140.

Thus, a portion of the diffusion region 114 in which the high voltage device isolation region is to be formed is exposed.

The photoresist pattern is then removed.

4 is a side cross-sectional view schematically illustrating a shape of a high voltage semiconductor device after the high voltage device isolation region 150 is formed according to the embodiment.

Referring to FIG. 4, an oxidation process is performed using the patterned pad oxide layer 130 and the pad nitride layer 140 as a mask.

Accordingly, a high voltage device isolation region 150 having a predetermined thickness is formed on a portion of the exposed diffusion region 114, and the high voltage device isolation region 150 is a field plate using a LOCOS (LOCal Oxidation of Silicon) process. field plate) structure.

5 is a side cross-sectional view schematically illustrating the shape of a high voltage semiconductor device after the gate 160 is formed according to an embodiment.

Referring to FIG. 5, the pad nitride layer 140 is removed and the pad oxide layer 130 is patterned to form a gate insulating layer 130a.

Subsequently, a gate 160 is formed on the gate insulating layer 130a, and spacers 170 are formed on both sidewalls of the gate 160.

In this case, the gate insulating layer 130a is formed from a portion of the body region 112 to a portion of the high voltage device isolation region 150 via a channel region of the semiconductor substrate 100.

FIG. 6 is a side cross-sectional view schematically illustrating a shape of a high voltage semiconductor device after the ion implantation regions 181, 182, 183, and 184 are formed according to the embodiment.

Referring to FIG. 6, a first ion implantation region may be formed by performing a first photoprocess and a first ion implantation process from a portion of the gate 160 of the body region 112 to a device isolation region 120 on the one side. 181 is formed.

Subsequently, a second ion implantation region 181 is formed from the bottom of the spacer 170 of the body region 112 to the device isolation region 120 on the one side by performing a second photo process and a second ion implantation process. .

A third ion implantation region 183 is formed next to the second ion implantation region 181 of the body region 112 by performing a third photoprocess and a third ion implantation process.

A fourth ion implantation region 184 is formed next to the high voltage device isolation region 150 of the diffusion region 114 by performing a fourth photo process and a fourth ion implantation process.

The first ion implantation region 181 may function as an LDD region, and the second ion implantation region 182 and the third ion implantation region 183 may function as a source region having a dual structure.

In addition, the fourth ion implantation region 184 may function as a drain region.

Meanwhile, the second ion implantation region 182 and the fourth ion implantation region 184 may be formed by implanting second conductivity type ions, and the third ion implantation region 183 may be a first conductivity type ion. Can be injected and formed.

7 is a side cross-sectional view schematically illustrating a shape of a high voltage semiconductor device after the interlayer insulating layer 190 is formed according to an embodiment.

Referring to FIG. 7, an interlayer insulating layer 190 is formed on the semiconductor substrate 100, and a via process, a metal material embedding process, a metal layer stacking process, a metal layer patterning process, and the like are performed on the interlayer insulating layer 190. Vias 192 and electrodes 194 are formed in the trenches.

One of the vias 192 may be simultaneously connected to the second ion implantation region 182 and the third ion implantation region 183, and the other of the vias 192 may be the fourth ion implantation region ( 184).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications other than those described above are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a side cross-sectional view schematically showing the shape of a high voltage semiconductor device after the pad oxide layer according to the embodiment is formed.

2 is a side cross-sectional view schematically showing the shape of a high voltage semiconductor device after the pad nitride layer is formed according to the embodiment.

3 is a side cross-sectional view schematically illustrating the shape of a high voltage semiconductor device after the pad oxide layer and the pad nitride layer are patterned to define a high voltage device isolation region according to an embodiment;

4 is a side cross-sectional view schematically showing the shape of a high voltage semiconductor device after the high voltage device isolation region is formed according to the embodiment;

5 is a side cross-sectional view schematically showing the shape of a high voltage semiconductor device after the gate is formed according to the embodiment.

6 is a side cross-sectional view schematically showing the shape of a high voltage semiconductor device after ion implantation regions are formed in accordance with an embodiment.

7 is a side cross-sectional view schematically showing the shape of a high voltage semiconductor device after the interlayer insulating layer is formed according to the embodiment.

Claims (14)

Forming a plurality of device isolation regions defining an active region of the semiconductor substrate; Forming a well region on an upper portion of the semiconductor substrate; Forming a body region on an upper portion of the well region; Forming a diffusion region on an upper portion of the well region to be spaced apart from the body region by a predetermined distance; Forming a high voltage device isolation region having a predetermined thickness on a portion of an upper portion of the diffusion region in a LOCOS (LOCal Oxidation of Silicon) field plate structure; Forming a gate insulating film from a portion of the body region to a portion of the high voltage device isolation region; And Forming a gate over the gate insulating film. The method of claim 1, wherein forming the high voltage device isolation region comprises: Forming a pad oxide layer on the semiconductor substrate; Forming a pad nitride layer on the pad oxide layer; Forming a photoresist pattern opening a portion of the diffusion region and patterning the pad oxide layer and the pad nitride layer; Removing the photoresist pattern; And forming the high voltage device isolation region by performing an oxidation process using the patterned pad oxide film and the pad nitride film as a mask. The method of claim 2, If the high voltage device isolation region is formed, removing the pad nitride layer; The forming of the gate insulating film may include forming the gate insulating film by patterning the pad oxide layer. The method of claim 1, Forming spacers on both sidewalls of the gate; Forming a first ion implantation region from a portion of the gate of the body region to an isolation region of the one side; Forming a second ion implantation region from below the spacer of the body region to the device isolation region of the one side; Forming a third ion implantation region next to the second ion implantation region of the body region; And And forming a fourth ion implantation region next to the high voltage device isolation region of the diffusion region. 5. The method of claim 4, Forming an interlayer insulating layer on the semiconductor substrate; Forming vias in the interlayer insulating layer, the vias connected to at least one of the first to fourth ion implantation regions and the gate; And And forming an electrode connected to the via on the interlayer insulating layer. The method of claim 5, wherein any one of a plurality of said vias is And a second ion implantation region and a third ion implantation region at the same time. 5. The method of claim 4, The semiconductor substrate is a first conductivity type sub substrate, The well region is a doped region of the first conductivity type or second conductivity type ions, The body region is a doped region of the first conductivity type ions, The diffusion region is a doped region of the second conductivity type ions, The second ion implantation region and the fourth ion implantation region are doped regions of the second conductivity type ions, And said third ion implantation region is a doped region of a first conductivity type ion. The method of claim 1, The body region is formed to contact the device isolation region on one side, The diffusion region is formed to be in contact with the device isolation region of the other side. A plurality of device isolation regions defining active regions of the semiconductor substrate; A well region formed on a portion of an upper side of the semiconductor substrate; A body region formed on an upper portion of the well region; A diffusion region formed on an upper portion of the well region to be spaced apart from the body region by a predetermined distance; A high voltage device isolation region formed over a portion of the diffusion region and formed in a LOCOS field plate structure having a predetermined thickness; A gate insulating film formed from a portion of the body region to a portion of the high voltage device isolation region; And A high voltage semiconductor device comprising a gate formed on the gate insulating film. 10. The method of claim 9, Spacers formed on both sidewalls of the gate; A first ion implantation region formed from a portion of the gate of the body region to an isolation region of the one side; A second ion implantation region formed from below the spacer of the body region to an isolation region of the one side; A third ion implantation region formed next to the second ion implantation region of the body region; And And a fourth ion implantation region formed next to the high voltage device isolation region of the diffusion region. The method of claim 10, An interlayer insulating layer formed on the semiconductor substrate; A via connected to at least one of the first to fourth ion implantation regions and the gate and formed in the interlayer insulating layer; And And an electrode connected to the via and formed on the interlayer insulating layer. 12. The via of claim 11 wherein any one of a plurality of said vias is And the second ion implantation region and the third ion implantation region at the same time. The method of claim 10, The semiconductor substrate is a first conductivity type sub substrate, The well region is a doped region of the first conductivity type or second conductivity type ions, The body region is a doped region of the first conductivity type ions, The diffusion region is a doped region of the second conductivity type ions, The second ion implantation region and the fourth ion implantation region are doped regions of the second conductivity type ions, And the third ion implantation region is a doped region of a first conductivity type ion. 10. The method of claim 9, The body region is formed to contact the device isolation region on one side, The diffusion region is formed to contact the device isolation region of the other side.
KR1020090135361A 2009-12-31 2009-12-31 High voltage semiconductor device and manufacturing method of high voltage semiconductor device KR20110078531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090135361A KR20110078531A (en) 2009-12-31 2009-12-31 High voltage semiconductor device and manufacturing method of high voltage semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090135361A KR20110078531A (en) 2009-12-31 2009-12-31 High voltage semiconductor device and manufacturing method of high voltage semiconductor device

Publications (1)

Publication Number Publication Date
KR20110078531A true KR20110078531A (en) 2011-07-07

Family

ID=44917988

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090135361A KR20110078531A (en) 2009-12-31 2009-12-31 High voltage semiconductor device and manufacturing method of high voltage semiconductor device

Country Status (1)

Country Link
KR (1) KR20110078531A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520493B1 (en) 2015-11-23 2016-12-13 SK Hynix Inc. High voltage integrated circuits having improved on-resistance value and improved breakdown voltage
KR20190008463A (en) * 2017-07-13 2019-01-24 매그나칩 반도체 유한회사 Semiconductor Device and Method for Fabricating the Same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520493B1 (en) 2015-11-23 2016-12-13 SK Hynix Inc. High voltage integrated circuits having improved on-resistance value and improved breakdown voltage
KR20190008463A (en) * 2017-07-13 2019-01-24 매그나칩 반도체 유한회사 Semiconductor Device and Method for Fabricating the Same

Similar Documents

Publication Publication Date Title
KR100974697B1 (en) Lateral double diffused metal oxide semiconductor device and manufacturing method of lateral double diffused metal oxide semiconductor device
KR101009399B1 (en) Lateral DMOS transistor and method of fabricating thereof
KR101572476B1 (en) semiconductor and method of manufacturing the same
KR101530582B1 (en) A semiconductor device and method for manufacturing the same
JP4440188B2 (en) Manufacturing method of semiconductor device
KR20190087786A (en) Semiconductor device and method of manufacturing the same
TW201943081A (en) Semiconductor device and method of manufacturing the same
US10910493B2 (en) Semiconductor device and method of manufacturing the same
KR100684428B1 (en) High voltage transistor having low on-resistance and method for thereof
KR100790261B1 (en) The fabricating method of dmos device
JP6651957B2 (en) Semiconductor device and manufacturing method thereof
TWI608546B (en) Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
JP5378925B2 (en) Semiconductor device and manufacturing method thereof
TW200952176A (en) Semiconductor devices and methods for fabricating the same
KR20110078531A (en) High voltage semiconductor device and manufacturing method of high voltage semiconductor device
US10868115B2 (en) High voltage device and manufacturing method thereof
CN110838513B (en) High voltage device and method for manufacturing the same
CN108962988B (en) High voltage metal oxide semiconductor element and manufacturing method thereof
TWI619200B (en) Metal oxide semiconductor device with dual-well and manufacturing method thereof
JP2006229182A (en) Semiconductor device and its fabrication process
JP3802331B2 (en) Semiconductor device and manufacturing method thereof
US20220223464A1 (en) High voltage device and manufacturing method thereof
JP2007059722A (en) Semiconductor device and its manufacturing method
JP5784269B2 (en) Semiconductor device and manufacturing method thereof
CN110838512B (en) High voltage device and method for manufacturing the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application