CN110838513B - High voltage device and method for manufacturing the same - Google Patents

High voltage device and method for manufacturing the same Download PDF

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CN110838513B
CN110838513B CN201810939369.7A CN201810939369A CN110838513B CN 110838513 B CN110838513 B CN 110838513B CN 201810939369 A CN201810939369 A CN 201810939369A CN 110838513 B CN110838513 B CN 110838513B
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well region
region
drift
conductivity type
deep well
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CN110838513A (en
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黄宗义
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Richtek Technology Corp
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Richtek Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention provides a high-voltage element and a manufacturing method thereof. The high voltage element includes: the semiconductor device comprises a semiconductor layer, an insulating structure, a first deep well region, a second deep well region, a drift well region, a first well region, a second well region, a body electrode, a high-voltage well region, a grid electrode, a source electrode and a drain electrode. The high-voltage well region is formed in the second deep well region, does not contact the first deep well region, the first well region and the second well region, and at least part of the high-voltage well region is located right below all the drift regions to inhibit parasitic transistor latch.

Description

High voltage device and method for manufacturing the same
Technical Field
The present invention relates to a high voltage device and a method for manufacturing the same, and more particularly, to a high voltage device capable of suppressing latch-up of a parasitic transistor and a method for manufacturing the same.
Background
Fig. 1A and 1B respectively show a top view and a cross-sectional view of a conventional high voltage device 100. The high voltage device means that the voltage applied to the drain is higher than 5V during normal operation. In general, the high voltage device 100 has a drift region 12a (indicated by the dashed line in fig. 1B) between the drain 19 and the gate 17, which separates the drain 19 from the gate 17, and the length of the drift region 12a in the channel direction (indicated by the dashed arrow in fig. 1A and 1B) is adjusted according to the operating voltage applied to the high voltage device 100 during normal operation. As shown in fig. 1A and 1B, the high voltage device 100 includes: well region 12, insulating structure 13, drift oxide region 14, body region 16, body electrode 16', gate 17, source 18, and drain 19. The well 12 has an N-type conductivity and is formed on the substrate 11, and the insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define an operation region 13a as a main active region of the high voltage device 100 during operation. The extent of the operation region 13a is as indicated by a thick black dashed box in fig. 1A. The gate 17 covers a portion of the drift oxide region 14.
When the high voltage device 100 operates as a low-side device, the high voltage device 100 may generate a latch-up current due to the conduction of the parasitic transistor, so that the high voltage device 100 may not operate normally.
In view of the above, the present invention provides a high voltage device capable of suppressing the conduction of a parasitic transistor and increasing a Safe Operating Area (SOA) when the high voltage device is operated, and a method for manufacturing the same.
Disclosure of Invention
From one aspect, the present invention provides a high voltage device comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other in a vertical direction, wherein the substrate has a first conductivity type; an insulating structure formed on the upper surface and connected to the upper surface for defining an operation region; a first deep well region of the first conductivity type formed in the semiconductor layer; a second deep well region of a second conductivity type formed in the semiconductor layer below the first deep well region and covering all of the first deep well region below and in contact with the first deep well region; a drift well region of the second conductivity type formed in the semiconductor layer over the first deep well region and covering a portion of the first deep well region over and in contact with the first deep well region, the drift well region being located below and connected to the upper surface in the vertical direction; a first well region of the first conductivity type formed on the second deep well region outside the operation region and contacting the first deep well region for electrically connecting with the first deep well region, wherein the first well region is located under the upper surface and connected to the upper surface in the vertical direction; a second well region of the second conductivity type formed outside the operation region and on the second deep well region outside the first well region, and contacting the second deep well region for electrically connecting with the second deep well region, and the second well region is located under the upper surface and connected to the upper surface in the vertical direction; a body region of the first conductivity type formed in the drift well region in the operating region and located below and connected to the upper surface in the vertical direction; a body electrode of the second conductivity type for serving as an electrical contact to the body region, the body electrode being formed below the top surface and connected to the body region of the top surface in the vertical direction; a high-voltage well region of the second conductivity type formed in the second deep well region, wherein the high-voltage well region does not contact the first deep well region, the first well region and the second well region, and at least a portion of the high-voltage well region is located under all the drift well regions; a gate formed in the operating region on the upper surface, wherein in the vertical direction, a portion of the drift well region is located below the gate and is connected to the gate, wherein the gate comprises: a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the drift well region; a conductive layer, which is used as an electrical contact of the grid electrode, is formed on all the dielectric layers and is connected with the dielectric layers; and a spacer layer formed on both sides of the conductive layer to serve as electrical insulation layers on both sides of the gate; and a source and a drain of the second conductivity type formed below the upper surface and connected to the operating region of the upper surface in the vertical direction, the source and the drain being located in the body region under the outside of the gate and in the drift well region away from the body region side, respectively; in a channel direction, an inversion region is located between the source electrode and the drift well, connected to the body region of the upper surface and used as an inversion current channel of the high-voltage element in a conducting operation; in the channel direction, a drift region is located between the drain and the body region, connected to the drift well region on the upper surface, and used as a drift current channel of the high-voltage device in a conducting operation.
From another aspect, the present invention provides a method for manufacturing a high voltage device, comprising: forming a semiconductor layer on a substrate, wherein the semiconductor layer has an upper surface and a lower surface opposite to each other in a vertical direction, and the substrate has a first conductivity type; forming an insulating structure on the upper surface and connected to the upper surface to define an operation region; forming a first deep well region of a first conductivity type formed in the semiconductor layer; forming a second deep well region of a second conductivity type formed in the semiconductor layer under the first deep well region and covering and contacting the first deep well region; forming a drift well region of the second conductivity type over the first deep well region in the semiconductor layer, covering a portion of the drift well region over and in contact with the first deep well region, the drift well region being located below and connected to the upper surface in the vertical direction; forming a first well region of the first conductivity type on the second deep well region outside the operation region, contacting the first deep well region, electrically connecting to the first deep well region, and being located under and connected to the upper surface in the vertical direction; forming a second well region of the second conductivity type over the second deep well region outside the operating region and outside the first well region, in contact with the second deep well region for electrically connecting to the second deep well region, the second well region being under the upper surface and connected to the upper surface in the vertical direction; forming a body region of the first conductivity type in the drift well region in the operation region, the body region being located below and connected to the upper surface in the vertical direction; forming a body electrode of the second conductivity type for serving as an electrical contact of the body region, the body electrode being formed below the top surface and connected to the body region of the top surface in the vertical direction; forming a high-voltage well region of the second conductivity type in the second deep well region without contacting the first deep well region, the first well region and the second well region, wherein at least a portion of the high-voltage well region is located under all of the drift regions; forming a gate in the operating region on the upper surface, wherein in the vertical direction, a portion of the drift well region is located below the gate and connected to the gate, wherein the gate comprises: a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the drift well region in the vertical direction; a conductive layer, which is used as an electrical contact of the grid electrode, is formed on all the dielectric layers and is connected with the dielectric layers; and a spacer layer formed on both sides of the conductive layer to serve as electrical insulation layers on both sides of the gate; and forming a source and a drain of the second conductivity type in the vertical direction, the source and the drain being formed below the upper surface and connected to the operating region of the upper surface, and the source and the drain being located in the body region below the outside of the gate and in the drift well region away from the body region side, respectively; in a channel direction, an inversion region is located between the source electrode and the drift well, connected to the body region of the upper surface and used as an inversion current channel of the high-voltage element in a conducting operation; in the channel direction, the drift region is located between the drain and the body region, connected to the drift well region on the upper surface, and used as a drift current channel of the high-voltage device in a conducting operation.
In a preferred embodiment, the high voltage device further includes a drift oxide region formed on and connected to the upper surface and located on and connected to the drift region in the operation region, wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a Shallow Trench Isolation (STI) structure or a Chemical Vapor Deposition (CVD) oxide region.
In a preferred embodiment, the concentration of a second conductive type impurity of the hvw region is higher than that of the second deep well region.
In a preferred embodiment, the first deep well region, the second deep well region and the substrate constitute a parasitic transistor, and the high-voltage well region is configured to suppress a latch-up current generated by the parasitic transistor.
In a preferred embodiment, the high voltage device further comprises: a first conductivity type contact of the first conductivity type for serving as an electrical contact of the first well region, the first conductivity type contact being formed under the upper surface and connected to the first well region of the upper surface in the vertical direction; and a second conductivity type contact of the second conductivity type formed below the upper surface and connected to the second well region on the upper surface in the vertical direction, the second conductivity type contact serving as an electrical contact of the second well region.
The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.
Drawings
Fig. 1A and 1B respectively show a top view and a cross-sectional view of a prior art high voltage device 100.
Fig. 2 shows a first embodiment of the invention.
Fig. 3 shows a second embodiment of the invention.
Fig. 4 shows a third embodiment of the invention.
Fig. 5 shows a fourth embodiment of the invention.
Fig. 6A-6G show a fifth embodiment of the present invention.
Description of the symbols in the drawings
100 200, 300, 400, 500 high voltage components
11 21, 31, 41, 51 substrate
11',21',31',41',51' semiconductor layer
11a,21a,31a,41a,51a upper surface
11b,21b,31b,41b,51b lower surface
12 22, 32, 42, 52 drift well region
12a,22a,32a,42a,52a drift region
13 23, 33, 43, 53 insulation structure
13a,23a,33a,43a,53a operating zone
14 24, 34, 44 drift oxide region
25 35, 45, 55 first deep well region
25',35',45',55' first well region
25",35",45",55" contacts of a first conductivity type
16 26, 36, 46, 56 body region
16',26',36',46',56' body pole
17 27, 37, 47, 57 grid
18 28, 38, 48, 58 source
19 29, 39, 49, 59 drain electrode
261. The photoresist layer
211 311, 411, 511 second deep well region
211',311',411',511' second well region
211',311',411',511' contacts of a second conductivity type
212 312, 412, 512 hvw well regions
271 371, 471, 571 dielectric layer
272 372, 472, 572 conductive layer
273 373, 473, 573 spacer layer
Detailed Description
The foregoing and other technical contents, features and effects of the invention will be more clearly understood from the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in the present invention are schematic and are intended to show the process steps and the up-down order of the layers, and the shapes, thicknesses and widths are not drawn to scale.
Referring to FIG. 2, a first embodiment of the present invention is shown. Fig. 2 shows a schematic cross-sectional view of a high voltage element 200. As shown in fig. 2, the high voltage device 200 includes: semiconductor layer 21', first deep well region 25, second deep well region 211, drift well region 22, insulating structure 23, drift oxide region 24, hvw region 212, body region 26, body pole 26', gate 27, source 28, drain 29, first well region 25', first conductivity type contact 25", second well region 211', and second conductivity type contact 211".
The semiconductor layer 21 'is formed on the substrate 21, and the semiconductor layer 21' has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 2, the same applies below). The substrate 21 is, for example, but not limited to, a semiconductor silicon substrate of a first conductivity type. The semiconductor layer 21 'is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 21'. The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described herein.
Referring to fig. 2, an insulating structure 23 is formed on the upper surface 21a and connected to the upper surface 21a to define an operation region 23a. The insulating structure 23 is not limited to a local oxidation of silicon (LOCOS) structure as shown in fig. 2, and may be a Shallow Trench Isolation (STI) structure. The operation region 23a is a voltage-current main operation region of the high-voltage device 200 during the on operation. A drift oxide region 24 is formed on the upper surface 21a and connected to the upper surface 21a, and is located on a drift region 22a (as indicated by the dashed line in fig. 2) in the operating region 23a and connected to the drift region 22a.
The first deep well region 25 has a first conductivity type and is formed in the semiconductor layer 21'. The first deep well region 25 can be formed by implanting, for example, but not limited to, first conductivity type impurities in the form of accelerated ions into the semiconductor layer 21' in an ion implantation process step to form the first deep well region 25. The second deep well region 211 has a second conductivity type, is formed in the semiconductor layer 21' under the first deep well region 25, and covers under the first deep well region 25 and contacts the first deep well region 25. The second deep well region 211 can be formed by implanting impurities of the second conductivity type into the substrate 21 or/and the semiconductor layer 21' in the form of accelerated ions in an ion implantation process step, for example, but not limited to. For example, when the semiconductor layer 21' is an epitaxial layer, the second conductive type impurities are implanted into the substrate 21 in the form of accelerated ions before the epitaxial layer is formed, and then an epitaxial process step is performed to form the epitaxial layer as the semiconductor layer 21', and after the thermal process, a portion of the second conductive type impurities will be diffused into the semiconductor layer 21', so as to form the second deep well region 211.
The drift well region 22 has a second conductivity type, is formed over the first deep well region 25 in the semiconductor layer 21', and covers over the first deep well region 25 and contacts the first deep well region 25, and in the vertical direction, the drift well region 22 is located under the upper surface 21a and connected to the upper surface 21a. The first well region 25' has the first conductivity type, is formed on the second deep well region 211 outside the operation region 23a, contacts the first deep well region 25 for electrically connecting with the first deep well region 25, and is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The second well region 211' has a second conductivity type, is formed on the second deep well region 211 outside the operation region 23a and outside the first well region 25', and contacts the second deep well region 211 to be electrically connected to the second deep well region 211, and the second well region 211' is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction.
The first conductive type contact 25 ″ has a first conductive type and serves as an electrical contact of the first well region 25', and the first conductive type contact 25 ″ is formed under the upper surface 21a and connected to the first well region 25' of the upper surface 21a in a vertical direction. The second conductive type contact 211 ″ has a second conductive type and serves as an electrical contact of the second well region 211', and the second conductive type contact 211 ″ is formed under the upper surface 21a and connected to the second well region 211' of the upper surface 21a in a vertical direction.
The body region 26 having the first conductivity type is formed in the drift well region 22 of the operation region 23a, and the body region 26 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The body electrode 26 'has a second conductivity type for serving as an electrical contact for the body region 26. In the vertical direction, the body electrode 26' is formed below the upper surface 21a and connected to the body region 26 of the upper surface 21a. The hvw region 212 of the second conductivity type is formed in the second deep well region 211, and the hvw region 212 does not contact the first deep well region 25, the first well region 25 'and the second well region 211', and at least a portion of the hvw region 212 is located directly under all the drift regions 22a. In the present embodiment, the hvw region 212 and the second deep well region 211 are defined in the same ion implantation region in the same channel direction and the same width direction (not shown) by the same photolithography process step, so that the hvw region 212 and the second deep well region 211 are completely overlapped from the top view (not shown).
A gate electrode 27 is formed in the operating region 23a on the upper surface 21a of the semiconductor layer 21', and a part of the drift well region 22 is located below the gate electrode 27 and connected to the gate electrode 27 in the vertical direction. Wherein, the gate 27 at least comprises: a dielectric layer 271, a conductive layer 272, and a spacer layer 273. The dielectric layer 271 is formed on the upper surface 21a and connected to the upper surface 21a, and the dielectric layer 271 is connected to the drift well region 22 in the vertical direction. The conductive layer 272 is used as an electrical contact for the gate 27, is formed over all of the dielectric layer 271 and is connected to the dielectric layer 271. Spacer layers 273 are formed on both sides of conductive layer 272 to serve as electrical insulation layers on both sides of gate 27.
With reference to fig. 2, the source 28 and the drain 29 have the second conductivity type, in the vertical direction, the source 28 and the drain 29 are formed under the upper surface 21a and connected to the operating region 23a of the upper surface 21a, and the source 28 and the drain 29 are respectively located in the body region 26 under the gate 27 outside the channel direction and in the drift well region 22 at the side far from the body region 26. In the channel direction, the inversion region 26a is located between the source 28 and the drift well region 22, and is connected to the body region 26 of the upper surface 21a for serving as an inversion current channel of the high voltage device 200 during the on operation. In the channel direction, the drift region 22a is located between the drain 29 and the body region 26, and is connected to the drift well region 22 of the upper surface 21a for serving as a drift current channel of the high voltage device 200 in the on operation.
It should be noted that the inversion current channel refers to a region where an inversion layer (inversion layer) is formed below the gate 27 to allow the on current to pass through between the source 28 and the drift current channel due to the voltage applied to the gate 27 during the on operation of the high voltage device 200, which is well known to those skilled in the art and is not described herein, and so on.
It should be noted that the drift current path refers to a region through which the on current passes in a drift manner during the on operation of the high voltage device 200, which is well known to those skilled in the art and will not be described herein.
Note that the upper surface 21a does not mean a completely flat plane, but means a surface of the semiconductor layer 21'. In the present embodiment, for example, the portion of the upper surface 21a where the drift oxide region 24 contacts the upper surface 21a has a depressed portion.
It should be noted that the gate 27 includes a dielectric layer 271 connected to the upper surface, a conductive layer 272 with conductivity, and a spacer layer 273 with electrical insulation property, which are well known to those skilled in the art and will not be described herein.
The above-mentioned "first conductivity type" and "second conductivity type" refer to that impurities of different conductivity types are doped in the semiconductor composition region (such as, but not limited to, the well region, the body region, the source and drain regions, etc.) in the high voltage device, so that the semiconductor composition region becomes the first or second conductivity type (such as, but not limited to, the first conductivity type is N-type, and the second conductivity type is P-type, or vice versa).
It should be noted that the high voltage device is referred to as a high voltage device, which is applied to the drain at normal operation and has a voltage higher than a specific voltage, for example, 5V, and the lateral distance (drift length) between the hvw region 25 and the drain 29 is adjusted according to the operation voltage applied at normal operation, so that the high voltage device can operate at the specific voltage. This is well known to those skilled in the art and will not be described in detail herein.
It is noted that one of the technical features of the present invention over the prior art is that: according to the present invention, taking the embodiment shown in fig. 2 as an example, when the high voltage device 200 is operated, the second conductive type impurity concentration of the hvw region 212 is higher than that of the second deep well region 211, thereby suppressing the current gain of a parasitic transistor, further reducing the substrate current of the parasitic transistor, preventing the parasitic transistor from turning on, and also suppressing the parasitic transistor from generating a latch-up current with another parasitic transistor adjacent to the high voltage device 200. Increasing the range of applications for the high voltage component 200. The parasitic transistor refers to a parasitic transistor formed by the first deep well region 25, the second deep well region 211, and the substrate 21.
Referring to FIG. 3, a second embodiment of the present invention is shown. Fig. 3 shows a schematic cross-sectional view of a high voltage element 300. As shown in fig. 3, the high voltage device 300 includes: semiconductor layer 31', first deep well region 35, second deep well region 311, drift well region 32, insulating structure 33, drift oxide region 34, hvw region 312, body region 36, body electrode 36', gate 37, source 38, drain 39, first well region 35', first conductivity type contact 35", second well region 311', and second conductivity type contact 311".
The semiconductor layer 31 'is formed on the substrate 31, and the semiconductor layer 31' has an upper surface 31a and a lower surface 31b opposite to each other in a vertical direction (as indicated by the solid arrow in fig. 3, the same applies below). The substrate 31 is, for example, but not limited to, a semiconductor silicon substrate of the first conductivity type. The semiconductor layer 31 'is formed on the substrate 31, or a portion of the substrate 31 is used as the semiconductor layer 31', for example, by an epitaxial process. The manner of forming the semiconductor layer 31' is well known to those skilled in the art and will not be described herein.
Referring to fig. 3, an insulating structure 33 is formed on the upper surface 31a and connected to the upper surface 31a to define an operation region 33a. The insulating structure 33 is not limited to a local oxidation of silicon (LOCOS) structure as shown in fig. 3, and may be a Shallow Trench Isolation (STI) structure. The operation region 33a is a voltage-current main action region of the high-voltage device 300 during the on operation. A drift oxide region 34 is formed on the upper surface 31a and connected to the upper surface 31a, and is located on a drift region 32a (as indicated by the dashed line in fig. 3) in the operation region 33a and connected to the drift region 32a.
The first deep well region 35 has a first conductivity type and is formed in the semiconductor layer 31'. The first deep well region 35 can be formed by implanting, for example, but not limited to, first conductive type impurities in the form of accelerated ions into the semiconductor layer 31' in an ion implantation process step to form the first deep well region 311. The second deep well region 311 has the second conductivity type, is formed in the semiconductor layer 31' under the first deep well region 35, and covers under the first deep well region 35 and contacts the first deep well region 35. The second deep well 311 can be formed by, for example, but not limited to, implanting a second conductive type impurity into the substrate 31 and/or the semiconductor layer 31' in the form of accelerated ions in an ion implantation process step to form the second deep well 311. For example, when the semiconductor layer 31' is an epitaxial layer, the second conductive type impurity is implanted into the substrate 31 in the form of accelerated ions before the epitaxial layer is formed, and then an epitaxial process is performed to form the epitaxial layer as the semiconductor layer 31', and after the thermal process, a portion of the second conductive type impurity will diffuse into the semiconductor layer 31', so as to form the second deep well region 311.
The drift well region 32 has the second conductivity type, is formed above the first deep well region 35 in the semiconductor layer 31', covers the first deep well region 35 and contacts the first deep well region 35, and in the vertical direction, the drift well region 32 is located below the upper surface 31a and connected to the upper surface 31a. The first well region 35' has the first conductivity type, is formed on the second deep well region 311 outside the operation region 33a, contacts the first deep well region 35 for electrically connecting with the first deep well region 35, and is located below the upper surface 31a and connected to the upper surface 31a in the vertical direction. The second well 311' of the second conductivity type is formed on the second deep well 311 outside the operation region 33a and outside the first well 35', and contacts the second deep well 311 to electrically connect to the second deep well 311, and the second well 311' is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction.
The first conductive type contact 35 ″ has a first conductive type for serving as an electrical contact of the first well region 35', and the first conductive type contact 35 ″ is formed under the upper surface 31a and connected to the first well region 35' of the upper surface 31a in a vertical direction. The second conductive type contact 311 ″ has a second conductive type for serving as an electrical contact of the second well region 311', and the second conductive type contact 311 ″ is formed under the upper surface 31a and connected to the second well region 311' of the upper surface 31a in a vertical direction.
The body region 36 has the first conductivity type, is formed in the drift well region 32 of the operation region 33a, and in the vertical direction, the body region 36 is located under the upper surface 31a and connected to the upper surface 31a. The body electrode 36 'has a second conductivity type for serving as an electrical contact to the body region 36. In the vertical direction, the body electrode 36' is formed under the upper surface 31a and connected to the body region 36 of the upper surface 31a. The hvw region 312 of the second conductivity type is formed in the second deep well region 311, and the hvw region 312 does not contact the first deep well region 35, the first well region 35 'and the second well region 311', and at least a portion of the hvw region 312 is located right under all the drift regions 32a. In the present embodiment, the hvw region 312 is between the body region 36 and the first well region 35' on the side away from the gate 37.
A gate electrode 37 is formed in the operating region 33a on the upper surface 31a of the semiconductor layer 31', and a part of the drift well region 32 is located below the gate electrode 37 and connected to the gate electrode 37 in the vertical direction. The gate 37 at least includes: a dielectric layer 371, a conductive layer 372, and a spacer layer 373. The dielectric layer 371 is formed on the upper surface 31a and connected to the upper surface 31a, and the dielectric layer 371 is connected to the drift well region 32 in the vertical direction. The conductive layer 372 serves as an electrical contact for the gate 37 and is formed over and connected to all of the dielectric layers 371. Spacers 373 are formed on both sides of conductive layer 372 to serve as electrical insulation layers on both sides of gate 37.
With reference to fig. 3, the source 38 and the drain 39 have the second conductivity type, in the vertical direction, the source 38 and the drain 39 are formed under the upper surface 31a and connected to the operating region 33a of the upper surface 31a, and the source 38 and the drain 39 are respectively located in the body region 36 under the gate 37 outside the channel direction and in the drift well region 32 at the side far from the body region 36. In the channel direction, the inversion region 36a is located between the source 38 and the drift well region 32, and is connected to the body region 36 of the upper surface 31a for serving as an inversion current channel of the high voltage device 300 during the on operation. In the channel direction, the drift region 32a is located between the drain 39 and the body region 36, and is connected to the drift well region 32 of the upper surface 31a for serving as a drift current channel of the high voltage device 300 in the on operation.
The present embodiment is different from the first embodiment in that, in the first embodiment, the drift oxide region 24 is a LOCOS structure, and in the present embodiment, the drift oxide region 34 is a Chemical Vapor Deposition (CVD) oxide region. The CVD oxide region is formed by a CVD process deposition step, which is well known to those skilled in the art and will not be described herein.
Referring to FIG. 4, a third embodiment of the present invention is shown. Fig. 4 shows a cross-sectional view of a high voltage element 400. As shown in fig. 4, the high voltage device 400 includes: semiconductor layer 41', first deep well region 45, second deep well region 411, drift well region 42, insulating structure 43, drift oxide region 44, hvw region 412, body region 46, body pole 46', gate 47, source 48, drain 49, first well region 411', first conductivity type contact 411", second well region 412', and second conductivity type contact 412".
The semiconductor layer 41 'is formed on the substrate 41, and the semiconductor layer 41' has an upper surface 41a and a lower surface 41b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 4, the same applies below). The substrate 41 is, for example, but not limited to, a semiconductor silicon substrate of a first conductivity type. The semiconductor layer 41 'is formed on the substrate 41, for example, by an epitaxial process, or a portion of the substrate 41 is used as the semiconductor layer 41'. The manner of forming the semiconductor layer 41' is well known to those skilled in the art and will not be described herein.
Referring to fig. 4, an insulating structure 43 is formed on the upper surface 41a and connected to the upper surface 41a to define an operation region 43a. The insulating structure 43 is not limited to a local oxidation of silicon (LOCOS) structure as shown in fig. 4, and may be a Shallow Trench Isolation (STI) structure. The operation region 43a is a voltage-current main action region of the high voltage device 400 during the on operation. A drift oxide region 44 is formed on the upper surface 41a and connected to the upper surface 41a, and is located on the drift region 42a (as indicated by the dashed line box in fig. 4) in the operating region 43a and connected to the drift region 42a.
The first deep well region 45 has a first conductivity type and is formed in the semiconductor layer 41'. The first deep well region 45 may be formed by implanting, for example, but not limited to, first conductivity type impurities in the semiconductor layer 41' in the form of accelerated ions in an ion implantation process step to form the first deep well region 45. The second deep well region 411 of the second conductivity type is formed in the semiconductor layer 41' under the first deep well region 45, and covers under the first deep well region 45 and contacts the first deep well region 45. The second deep well region 411 may be formed by implanting, for example, but not limited to, second conductive type impurities into the substrate 41 or/and the semiconductor layer 41' in the form of accelerated ions in an ion implantation process step to form the second deep well region 411. For example, when the semiconductor layer 41' is an epitaxial layer, the second conductive type impurity is implanted into the substrate 41 in the form of accelerated ions before the epitaxial layer is formed, and then an epitaxial process is performed to form the epitaxial layer as the semiconductor layer 41', and after the thermal process, a portion of the second conductive type impurity will diffuse into the semiconductor layer 41', so as to form the second deep well region 411.
The drift well region 42 has a second conductivity type, is formed above the first deep well region 45 in the semiconductor layer 41', covers the first deep well region 45 and contacts the first deep well region 45, and in the vertical direction, the drift well region 42 is located below the upper surface 41a and connected to the upper surface 41a. The first well region 45 'has the first conductivity type, is formed on the second deep well region 411 outside the operation region 43a, contacts the first deep well region 45, and is electrically connected to the first deep well region 45, and the first well region 45' is located under the upper surface 41a and connected to the upper surface 41a in the vertical direction. The second well 411' of the second conductivity type is formed on the second deep well 411 outside the operation region 43a and outside the first well 45', and contacts the second deep well 411 to electrically connect to the second deep well 411, and in the vertical direction, the second well 411' is located under the upper surface 41a and connected to the upper surface 41a.
The first conductive type contact 45 ″ has a first conductive type for serving as an electrical contact of the first well region 45', and the first conductive type contact 45 ″ is formed under the upper surface 41a and connected to the first well region 45' of the upper surface 41a in a vertical direction. A second conductive type contact 411 ″ of the second conductive type is formed under the upper surface 41a and connected to the second well 411 'of the upper surface 41a in the vertical direction as an electrical contact of the second well 411'.
The body region 46 having the first conductivity type is formed in the drift well region 42 of the operation region 43a, and the body region 46 is located under the upper surface 41a and connected to the upper surface 41a in the vertical direction. Body electrode 46 'has a second conductivity type for serving as an electrical contact for body region 46. In the vertical direction, body electrode 26' is formed below upper surface 41a and is connected to body region 46 at upper surface 41a. The hvw region 412 of the second conductivity type is formed in the second deep well 411, and the hvw region 412 does not contact the first deep well 45, the first well 45 'and the second well 411', and at least a portion of the hvw region 412 is located directly under all the drift regions 42a. In the present embodiment, all hvw regions 412 are located directly below all drift regions 42a.
A gate 47 is formed in the operating region 43a on the upper surface 41a of the semiconductor layer 41', and a part of the drift well region 42 is located below the gate 47 and connected to the gate 47 in the vertical direction. Wherein, the gate 47 at least comprises: dielectric layer 471, conductive layer 472, and spacer layer 473. The dielectric layer 471 is formed on the upper surface 41a and connected to the upper surface 41a, and the dielectric layer 471 is connected to the drift well region 42 in the vertical direction. The conductive layer 472 is used as an electrical contact for the gate 47, and is formed on all the dielectric layers 471 and connected to the dielectric layers 471. Spacers 473 are formed on both sides of conductive layer 472 to serve as electrical insulation layers on both sides of gate 47.
With reference to fig. 4, the source 48 and the drain 49 have the second conductivity type, in the vertical direction, the source 48 and the drain 49 are formed under the upper surface 41a and connected to the operating region 43a of the upper surface 41a, and the source 48 and the drain 49 are respectively located in the body region 46 under the gate 47 in the channel direction and in the drift well region 42 at the side far from the body region 46. In the channel direction, the inversion region 46a is located between the source 48 and the drift well 42, and is connected to the body region 46 of the upper surface 41a for serving as an inversion current channel of the high voltage device 400 during the on operation. In the channel direction, the drift region 42a is located between the drain 49 and the body region 46, and is connected to the drift well region 42 of the upper surface 41a for serving as a drift current channel of the high voltage device 400 during the on operation.
The present embodiment is different from the first embodiment in that, in the first embodiment, the drift oxide region 24 is a LOCOS structure, and in the present embodiment, the drift oxide region 44 is a Shallow Trench Isolation (STI) structure. STI structures are well known to those skilled in the art and will not be described in detail herein.
Referring to FIG. 5, a fourth embodiment of the present invention is shown. Fig. 5 shows a schematic cross-sectional view of a high voltage element 500. As shown in fig. 5, the high voltage device 500 includes: the semiconductor layer 51', the first deep well region 55, the second deep well region 511, the drift well region 52, the insulating structure 53, the high-voltage well region 55, the body region 56, the body electrode 56', the gate 57, the source 58, the drain 59, the first well region 55', the first conductivity-type contact 55", the second well region 511', and the second conductivity-type contact 512".
The semiconductor layer 51 'is formed on the substrate 51, and the semiconductor layer 51' has an upper surface 51a and a lower surface 51b opposite to each other in a vertical direction (as indicated by the solid arrow in fig. 5, the same applies below). The substrate 51 is, for example, but not limited to, a semiconductor silicon substrate of a first conductivity type. The semiconductor layer 51 'is formed on the substrate 51, for example, by an epitaxial process, or a portion of the substrate 51 is used as the semiconductor layer 51'. The manner of forming the semiconductor layer 51' is well known to those skilled in the art and will not be described herein.
Referring to fig. 5, an insulating structure 53 is formed on the upper surface 51a and connected to the upper surface 51a to define an operation region 53a. The insulating structure 53 is not limited to a local oxidation of silicon (LOCOS) structure as shown in fig. 5, and may be a Shallow Trench Isolation (STI) structure. The operation region 53a is a voltage-current main action region of the high voltage device 500 during the on operation.
The first deep well region 55 has a first conductivity type and is formed in the semiconductor layer 51'. The first deep well region 55 may be formed by, for example and without limitation, implanting a first conductivity type impurity into the semiconductor layer 51' in the form of accelerated ions in an ion implantation process step to form the first deep well region 55. The second deep well region 511 of the second conductivity type is formed in the semiconductor layer 51' under the first deep well region 55, and covers under the first deep well region 54 and contacts the first deep well region 55. The second deep well region 511 can be formed by implanting impurities of the second conductivity type into the substrate 51 and/or the semiconductor layer 51' in the form of accelerated ions in an ion implantation process step, for example, but not limited to. For example, when the semiconductor layer 51' is an epitaxial layer, the second conductive type impurity is implanted into the substrate 51 in the form of accelerated ions before the epitaxial layer is formed, and then an epitaxial process is performed to form the epitaxial layer as the semiconductor layer 51', and after the thermal process, a portion of the second conductive type impurity is diffused into the semiconductor layer 51' to form the second deep well region 511.
The drift well region 52 has a second conductivity type, is formed over the first deep well region 55 in the semiconductor layer 51', and covers over the first deep well region 55 and contacts the first deep well region 55, and in the vertical direction, the drift well region 52 is located under the upper surface 51a and connected to the upper surface 51a. The first well 55 'of the first conductivity type is formed on the second deep well 511 outside the operation region 53a and contacts the first deep well 55 for electrically connecting with the first deep well 55, and the first well 55' is located under the upper surface 51a and connected to the upper surface 51a in the vertical direction. The second well 511' of the second conductivity type is formed on the second deep well region 5211 outside the operation region 53a and outside the first well 55', and contacts the second deep well 511 for electrically connecting to the second deep well 511, and the second well 511' is located under the upper surface 51a and connected to the upper surface 51a in the vertical direction.
The first conductive type contact 55 ″ has a first conductive type and serves as an electrical contact of the first well region 55', and the first conductive type contact 55 ″ is formed under the upper surface 51a and connected to the first well region 55' of the upper surface 51a in a vertical direction. The second conductive type contact 511 ″ has a second conductive type and is used as an electrical contact of the second well region 511', and the second conductive type contact 511 ″ is formed under the upper surface 51a and is connected to the second well region 511' of the upper surface 51a in the vertical direction.
The body region 56 of the first conductivity type is formed in the drift well region 52 of the operation region 53a, and the body region 56 is located under the upper surface 51a and connected to the upper surface 51a in the vertical direction. The body electrode 56 'has a second conductivity type for serving as an electrical contact for the body region 56. In the vertical direction, the body electrode 56' is formed under the upper surface 51a and connected to the body region 56 of the upper surface 51a. The hvw region 512 of the second conductivity type is formed in the second deep well 511, and the hvw region 512 does not contact the first deep well 55, the first well 55 'and the second well 511', and at least a portion of the hvw region 512 is located right under all the drift regions 52 a. In the present embodiment, the hvw 512 and the second deep well 211 are defined in the same lithography process step in the same ion implantation region in the channel direction and the width direction (not shown), so that the hvw 212 and the second deep well 211 are completely overlapped from the top view (not shown).
A gate electrode 57 is formed in the operating region 53a on the upper surface 51a of the semiconductor layer 51', and a part of the drift well region 52 is located below the gate electrode 57 and connected to the gate electrode 57 in the vertical direction. The gate 57 at least includes: dielectric layer 571, conductive layer 572, and spacer layer 573. The dielectric layer 571 is formed on the upper surface 51a and connected to the upper surface 51a, and the dielectric layer 571 is connected to the drift well region 52 in the vertical direction. Conductive layer 572 serves as an electrical contact for gate 57, and is formed over all of dielectric layer 571 and connected to dielectric layer 571. Spacer layers 573 are formed on both sides of conductive layer 572 as electrical insulation layers on both sides of gate 57.
With reference to fig. 5, the source 58 and the drain 59 have the second conductivity type, in the vertical direction, the source 58 and the drain 59 are formed under the upper surface 51a and connected to the operating region 53a of the upper surface 51a, and the source 58 and the drain 59 are respectively located in the body region 56 under the gate 57 in the channel direction and in the drift well region 52 at the side far from the body region 56. In the channel direction, the inversion region 56a is located between the source 58 and the drift well region 52, and is connected to the body region 56 of the upper surface 51a for serving as an inversion current channel of the high voltage device 500 during the turn-on operation. In the channel direction, the drift region 52a is located between the drain 59 and the body region 56, and is connected to the drift well region 52 of the upper surface 51a for serving as a drift current channel of the high voltage device 500 in the on operation.
The present embodiment is different from the first embodiment in that, in the first embodiment, the drift oxide region 24 is a LOCOS structure, but in the present embodiment, the drift oxide region is not included, and the length of the drift region 52a in the channel direction is used to adjust the sustainable operating voltage.
Please refer to fig. 6A-6G, which illustrate a fifth embodiment of the present invention. Fig. 6A-6G illustrate a method of fabricating the high voltage device 200. FIG. 6B shows a cross-sectional view of AA' of FIG. 6A. As shown in fig. 6A and 6B, a semiconductor layer 21 'is first formed on a substrate 21, and the semiconductor layer 21' has an upper surface 21a and a lower surface 21B opposite to each other in a vertical direction (as indicated by the solid arrow in fig. 6B, the same applies hereinafter). The substrate 21 is, for example, but not limited to, a semiconductor silicon substrate of a first conductivity type. The semiconductor layer 21 'is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 21'. The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described herein.
With continued reference to fig. 6A and 6B, an insulating structure 23 and a drift oxide region 24 are formed on the upper surface 21a and connected to the upper surface 21a. The insulating structure 23 is used to define an operation region 23a (as indicated by the dashed box in fig. 6A). The insulating structure 23 is not limited to a local oxidation of silicon (LOCOS) structure as shown in the figure, and may be a Shallow Trench Isolation (STI) structure. The drift oxide region 24 is formed on the upper surface 21a and connected to the upper surface 21a, and is located on the drift region 22a in the operating region 23a and connected to the drift region 22a (refer to the dashed box in fig. 2).
Next, referring to fig. 6C, a first deep well 25 of the first conductivity type is formed in the semiconductor layer 21'. The first deep well region 25 can be formed by implanting, for example, but not limited to, first conductivity type impurities in the form of accelerated ions into the semiconductor layer 21' in an ion implantation process step to form the first deep well region 25. The second deep well region 211 of the second conductivity type is formed in the semiconductor layer 21' under the first deep well region 25, and covers under the first deep well region 25 and contacts the first deep well region 25. The second deep well region 211 can be formed by implanting impurities of the second conductivity type into the substrate 21 or/and the semiconductor layer 21' in the form of accelerated ions in an ion implantation process step, for example, but not limited to. For example, when the semiconductor layer 21' is an epitaxial layer, the second conductive type impurities are implanted into the substrate 21 in the form of accelerated ions before the epitaxial layer is formed, and then an epitaxial process step is performed to form the epitaxial layer as the semiconductor layer 21', and after the thermal process, a portion of the second conductive type impurities will be diffused into the semiconductor layer 21', so as to form the second deep well region 211.
Next, with reference to fig. 6C, the hvw region 212 of the second conductivity type is formed in the second deep well region 211, and the hvw region 212 does not contact the first deep well region 25, the first well region 25 'and the second well region 211', and at least a portion of the hvw region 212 is located right under all the drift regions 22a. In the present embodiment, the hvw region 212 and the second deep well region 211 are defined in the same ion implantation region in the channel direction and the width direction (not shown) by the same photolithography process step, so that the hvw region 212 and the second deep well region 211 are completely overlapped from the top view (not shown).
Next, referring to fig. 6D, the drift well region 22 of the second conductivity type is formed over the first deep well region 25 in the semiconductor layer 21', and covers the first deep well region 25 and contacts the first deep well region 25, and in the vertical direction, the drift well region 22 is located under the upper surface 21a and connected to the upper surface 21a. For example, a second conductivity type impurity can be implanted into semiconductor layer 22 in the form of accelerated ions, as indicated by the dashed arrows in fig. 6D, to form drift well region 22, using, for example, but not limited to, an ion implantation fabrication step.
Referring to fig. 6D, the first well region 25 'of the first conductivity type is formed on the second deep well region 211 outside the operation region 23a and contacts the first deep well region 25 for electrically connecting to the first deep well region 25, and the first well region 25' is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. Next, a second well region 211' of the second conductivity type is formed over the second deep well region 211 outside the operation region 23a and outside the first well region 25', and contacts the second deep well region 211 to electrically connect to the second deep well region 211, and the second well region 211' is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction.
Next, referring to fig. 6E, a body region 26 is formed in the drift well region 22 of the operation region 23a, and the body region 26 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The body region 26 has a first conductivity type, and the body region 26 is formed by, for example, but not limited to, doping impurities of the first conductivity type into the drift well region 22 by using the photoresist layer 261 formed by the photolithography process as a mask to form the body region 26.
Next, referring to fig. 6F, a dielectric layer 271 and a conductive layer 272 of the gate 27 are formed in the operating region 23a on the upper surface 21a of the semiconductor layer 21', and a portion of the body region 26 is located right under the gate 27 and connected to the gate 27, so as to provide an inversion current path for the high voltage device 200 during the turn-on operation.
Referring to fig. 6F, for example, after the dielectric layer 271 and the conductive layer 272 of the gate 27 are formed, a lightly doped region 281 is formed to prevent the body region 26 under the spacer layer 273 from forming an inversion current channel during the turn-on operation of the high voltage device 200. The lightly doped region 281 is formed by, for example, doping the second conductive type impurities into the body region 26 to form the lightly doped region 281. In this embodiment, for example, but not limited to, an ion implantation process step may be used to implant the second conductive type impurity into the body region 26 in the form of accelerated ions to form the lightly doped region 281.
Next, referring to fig. 6G, a spacer layer 273 is formed on the outside of the side surface of the conductive layer 272 to form the gate 27. Next, a body 26', a source 28, a drain 29, a first conductive contact 25", and a second conductive contact 211" are formed under the top surface 21a and in the operating region 23a of the top surface 21a. The source 28 and the drain 29 are respectively located in the body region 26 under the gate 27 outside the channel direction and in the drift well region 22 at the side far from the body region 26, and in the channel direction, the drift region 22a is located between the drain 29 and the body region 26 in the drift well region 22 near the upper surface 21a for serving as a drift current channel of the high-voltage device 200 in the on operation, and in the vertical direction, the source 28 and the drain 29 are located under the upper surface 21a and connected to the upper surface 21a. The second conductive type contact 211 ″ has a second conductive type and serves as an electrical contact of the second well region 211', and the second conductive type contact 211 ″ is formed under the upper surface 21a and connected to the second well region 211' of the upper surface 21a in a vertical direction. The second conductive type contact 211", the source 28 and the drain 29 have the second conductive type, and the steps of forming the second conductive type contact 211", the source 28 and the drain 29, such as but not limited to, using a photoresist layer formed by a photolithography process as a mask, dope the second conductive type impurities into the second well region 211', the body region 26 and the drift well region 22, respectively, to form the second conductive type contact 211", the source 28 and the drain 29.
The first conductive type contact 25 ″ has a first conductive type and serves as an electrical contact of the first well region 25', and the first conductive type contact 25 ″ is formed under the upper surface 21a and connected to the first well region 25' of the upper surface 21a in a vertical direction. Body electrode 26 'has a second conductivity type for serving as an electrical contact for body region 26. In the vertical direction, body electrode 26' is formed below upper surface 21a and is connected to body region 26 at upper surface 21a. The steps of forming the first conductive type contact 25 "and the body electrode 26', such as but not limited to, using a photoresist layer formed by a photolithography process as a mask, are to dope the first conductive type impurities into the first well region 25' and the body region 26, respectively, to form the first conductive type contact 25" and the body electrode 26'.
The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as threshold voltage adjustment regions, may be added without affecting the primary characteristics of the device; for example, the lithography technique is not limited to the mask technique, but may include electron beam lithography. All of which can be analogized to the teachings of the present invention. In addition, the embodiments described are not limited to a single application, and may be combined, for example, but not limited to, a combination of both embodiments. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, any one of the claims should not be limited thereby.

Claims (10)

1. A high voltage device, comprising:
a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface and a lower surface opposite to each other in a vertical direction, wherein the substrate has a first conductivity type;
an insulating structure formed on the upper surface and connected to the upper surface for defining an operation region;
a first deep well region of the first conductivity type formed in the semiconductor layer;
a second deep well region of a second conductivity type formed in the semiconductor layer below the first deep well region and covering all of the first deep well region below and in contact with the first deep well region;
a drift well region of the second conductivity type formed in the semiconductor layer over the first deep well region and covering a portion of the first deep well region over and in contact with the first deep well region, the drift well region being located below and connected to the upper surface in the vertical direction;
a first well region of the first conductivity type formed on the second deep well region outside the operation region and contacting the first deep well region for electrically connecting with the first deep well region, wherein the first well region is located under the upper surface and connected to the upper surface in the vertical direction;
a second well region of the second conductivity type formed outside the operation region and on the second deep well region outside the first well region, and contacting the second deep well region for electrically connecting with the second deep well region, and the second well region is located under the upper surface and connected to the upper surface in the vertical direction;
a body region of the first conductivity type formed in the drift well region in the operating region and located below and connected to the upper surface in the vertical direction;
a body electrode of the second conductivity type for serving as an electrical contact to the body region, the body electrode being formed below the top surface and connected to the body region of the top surface in the vertical direction;
a high-voltage well region of the second conductivity type formed in the second deep well region, wherein the high-voltage well region does not contact the first deep well region, the first well region and the second well region, and at least a portion of the high-voltage well region is located under all the drift regions;
a gate formed in the operating region on the upper surface, wherein in the vertical direction, a portion of the drift well region is located below the gate and is connected to the gate, wherein the gate comprises:
a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the drift well region;
a conductive layer, which is used as an electrical contact of the grid electrode, is formed on all the dielectric layers and is connected with the dielectric layers; and
a spacer layer formed on both sides of the conductive layer to serve as electrical insulation layers on both sides of the gate; and
a source and a drain of the second conductivity type formed below the upper surface and connected to the operating region of the upper surface in the vertical direction, the source and the drain being located in the body region under the outside of the gate and in the drift well region away from the body region side, respectively;
in a channel direction, an inversion region is located between the source electrode and the drift well, connected to the body region of the upper surface and used as an inversion current channel of the high-voltage element in a conducting operation;
in the channel direction, the drift region is located between the drain and the body region, connected to the drift well region on the upper surface, and used as a drift current channel of the high-voltage device in a conducting operation.
2. The high voltage device of claim 1, further comprising a drift oxide region formed on and connected to the top surface and located on and connected to the drift region in the operating region, wherein the drift oxide region comprises a local oxide structure, a shallow trench isolation structure or a chemical vapor deposition oxide region.
3. The device of claim 1, wherein the hvw well region has a higher concentration of impurities of a second conductivity type than the second deep well region.
4. The high-voltage device as claimed in claim 1, wherein the first deep well region, the second deep well region and the substrate form a parasitic transistor, and the high-voltage well region is configured to suppress a latch-up current generated by the parasitic transistor.
5. The high voltage device of claim 1, further comprising:
a first conductivity type contact of the first conductivity type for serving as an electrical contact of the first well region, the first conductivity type contact being formed under the upper surface and connected to the first well region of the upper surface in the vertical direction; and
a contact of a second conductivity type, having the second conductivity type, for serving as an electrical contact to the second well region, the contact of the second conductivity type being formed under the upper surface and connected to the second well region on the upper surface in the vertical direction.
6. A method for manufacturing a high voltage device comprises:
forming a semiconductor layer on a substrate, wherein the semiconductor layer has an upper surface and a lower surface opposite to each other in a vertical direction, and the substrate has a first conductivity type;
forming an insulating structure on the upper surface and connected to the upper surface to define an operation region;
forming a first deep well region of a first conductivity type formed in the semiconductor layer;
forming a second deep well region of a second conductivity type formed in the semiconductor layer under the first deep well region and covering and contacting the first deep well region;
forming a drift well region of the second conductivity type over the first deep well region in the semiconductor layer, covering a portion of the drift well region over and in contact with the first deep well region, the drift well region being located below and connected to the upper surface in the vertical direction;
forming a first well region of the first conductivity type on the second deep well region outside the operation region, contacting the first deep well region, electrically connecting to the first deep well region, and being located under and connected to the upper surface in the vertical direction;
forming a second well region of the second conductivity type, formed outside the operating region and on the second deep well region outside the first well region, and contacting the second deep well region for electrically connecting with the second deep well region, and the second well region is located under the upper surface and connected to the upper surface in the vertical direction;
forming a body region of the first conductivity type in the drift well region in the operation region, the body region being located below and connected to the upper surface in the vertical direction;
forming a body electrode of the second conductivity type for serving as an electrical contact to the body region, the body electrode being formed below the top surface and connected to the body region of the top surface in the vertical direction;
forming a high-voltage well region of the second conductivity type in the second deep well region, wherein the high-voltage well region does not contact the first deep well region, the first well region and the second well region, and at least a portion of the high-voltage well region is located under all the drift regions;
forming a gate in the operating region on the upper surface, wherein in the vertical direction, a portion of the drift well region is located below the gate and is connected to the gate, wherein the gate comprises:
a dielectric layer formed on the upper surface and connected to the upper surface, wherein the dielectric layer is connected to the drift well region in the vertical direction;
a conductive layer, which is used as an electrical contact of the grid electrode, is formed on all the dielectric layers and is connected with the dielectric layers; and
a spacer layer formed on both sides of the conductive layer to serve as electrical insulation layers on both sides of the gate; and
forming a source and a drain of the second conductivity type in the vertical direction, the source and the drain being formed under the upper surface and connected to the operating region of the upper surface, and the source and the drain being located in the body region under the outside of the gate and in the drift well region away from the body region side, respectively;
in a channel direction, an inversion region is located between the source electrode and the drift well, connected to the body region of the upper surface and used as an inversion current channel of the high-voltage element in a conducting operation;
in the channel direction, the drift region is located between the drain and the body region, connected to the drift well region on the upper surface, and used as a drift current channel of the high-voltage device in a conducting operation.
7. The method of claim 6, further comprising forming a drift oxide region on and connected to the top surface, the drift oxide region being located over and connected to the drift region in the operating region, wherein the drift oxide region comprises a local oxide structure, a shallow trench isolation structure or a chemical vapor deposition oxide region.
8. The method of claim 6, wherein a second conductivity type impurity concentration of the hvw region is higher than a second conductivity type impurity concentration of the second deep well region.
9. The method of claim 6, wherein the first deep well region, the second deep well region and the substrate form a parasitic transistor, and the HVW region is configured to inhibit the parasitic transistor from generating a latch-up current.
10. The method of manufacturing a high voltage device according to claim 6, further comprising:
forming a first conductivity type contact having the first conductivity type for serving as an electrical contact of the first well region, the first conductivity type contact being formed under the upper surface and connected to the first well region of the upper surface in the vertical direction; and
forming a second conductive contact of the second conductivity type for serving as an electrical contact of the second well region, the second conductive contact being formed under the upper surface and connected to the second well region at the upper surface in the vertical direction.
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