CN114759090A - High voltage device and method for manufacturing the same - Google Patents

High voltage device and method for manufacturing the same Download PDF

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Publication number
CN114759090A
CN114759090A CN202110648538.3A CN202110648538A CN114759090A CN 114759090 A CN114759090 A CN 114759090A CN 202110648538 A CN202110648538 A CN 202110648538A CN 114759090 A CN114759090 A CN 114759090A
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region
layer
substrate
semiconductor layer
source
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Inventor
游焜煌
陈建馀
廖庭维
熊志文
张钧隆
邱国卿
翁武得
邱建维
胡永中
杨大勇
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Richtek Technology Corp
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Richtek Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a high-voltage element and a manufacturing method thereof. The high-voltage element includes: semiconductor layer, well region, substrate region, grid, source and drain. The substrate region has a second conductivity type, is formed in the semiconductor layer and is connected to the well region in the channel direction. The grid electrode is formed on the semiconductor layer, and part of the substrate region is positioned right below the grid electrode and is connected with the grid electrode so as to provide an inversion region of the high-voltage element in the conducting operation. The source is located in the substrate region, the drain is located in the well region away from the substrate region, and a portion of the well region is located between the substrate region and the drain to separate the substrate region and the drain. The first concentration peak region of the impurity doping distribution of the substrate region is positioned right below the source electrode and contacts the source electrode. The second conductive type impurity concentration of the first concentration peak region is higher than that of the other region of the base region.

Description

High voltage device and method for manufacturing the same
Technical Field
The present invention relates to a high voltage device and a method of manufacturing the same, and more particularly, to a high voltage device capable of suppressing conduction of a parasitic transistor and a method of manufacturing the same.
Background
Fig. 1A and 1B respectively show a top view and a cross-sectional view of a conventional high voltage device 100. The high voltage device is a semiconductor device in which a voltage applied to a drain is higher than 5V during normal operation. In general, the drain 19 and the body region 15 of the high voltage device 100 have a drift region 12a (indicated by the dashed line in fig. 1B) separating the drain 19 and the body region 15, and the length of the drift region 12a in the channel direction (indicated by the dashed line arrows in fig. 1A and 1B) is adjusted according to the operating voltage applied to the high voltage device 100 during normal operation. As shown in fig. 1A and 1B, the high voltage device 100 includes: well region 12, drift oxide region 14, body region 15, body electrode 16, gate 17, source 18, and drain 19. The well 12 is of N-type conductivity and is formed on the substrate 11. The gate 17 covers a portion of the drift oxide region 14. The body electrode 16 and the body region 15 are P-type in conductivity. The source 18 and drain 19 are of N-type conductivity.
In general, the high voltage device 100 is fabricated by forming a plurality of cells in a mirror image arrangement sharing the body region 15 and the body pole 16 to form the high voltage device 100. Thus, as shown in fig. 1A and 1B, source 18 'is mirror symmetric to source 18, gate 17' is mirror symmetric to gate 17, and electrically connects source 18 'to source 18 (not shown), electrically connects gate 17' to gate 17 (not shown), and so on.
When the high voltage device 100 operates, holes in hot carriers generated by a high electric field are injected into the body 16 through the body region 15, and when the hot carrier current flows through the body region 15, which causes a voltage drop in the body region 15 to increase, and further causes a parasitic NPN Bipolar Junction Transistor (BJT) formed by the source 18, the body region 15, and the well region 12 to be turned on, thereby generating a large conduction current, damaging the structure of the high voltage device 100, and limiting a Safe Operation Area (SOA). The definition of the safe operation area is well known to those skilled in the art and will not be described herein.
In view of the above, the present invention provides a high voltage device capable of suppressing the conduction of a parasitic transistor when the high voltage device is operated, and improving the safe operation area, and a method for manufacturing the same.
Disclosure of Invention
In one aspect, the present invention provides a high voltage device comprising: a semiconductor layer formed on a substrate; a well region of a first conductivity type, wherein the well region is formed in the semiconductor layer; a substrate region of a second conductivity type, wherein the substrate region is formed in the semiconductor layer and connected to the well region in a channel direction; a gate formed on the semiconductor layer, wherein a portion of the substrate region is located right under the gate and connected to the gate to provide an inversion region of the high voltage device during a turn-on operation; and a source and a drain of the first conductivity type, wherein the source and the drain are formed below and connected to an upper surface of the semiconductor layer, wherein the source and the drain are respectively located at two sides of the gate, the source is located in the substrate region, the drain is located in the well region away from the substrate region, and a portion of the well region is located between the substrate region and the drain to separate the substrate region and the drain; wherein a first concentration peak region of the substrate region is located right below the source and contacts the source; wherein the first concentration peak region has a higher concentration of the second conductivity type impurity than other regions of the base region.
In one embodiment, a second concentration peak region of the substrate region is located below and connected to the upper surface of the semiconductor layer, wherein the second concentration peak region surrounds and is connected to the source, and the second conductivity type impurity concentration of the second concentration peak region is higher than that of the substrate region except for the first concentration peak region.
In one embodiment, the body region further includes a first layer formed by a first process step that simultaneously forms another first layer in another device in the semiconductor layer, the first layer extending downward from the upper surface to a depth greater than the source.
In one embodiment, the substrate region further includes a second layer formed by a second process step that simultaneously forms another second layer in another device in the semiconductor layer, the second layer extending downward from the upper surface to a depth greater than the first layer.
In one embodiment, the high voltage device further includes a buried layer formed at least partially in the semiconductor layer, wherein the buried layer has the first conductivity type and is located directly under the substrate region and the well region.
In one embodiment, the high voltage device further includes a drift oxide region formed over the semiconductor layer, wherein a portion of the gate is directly over and connected to the drift oxide region.
In one embodiment, the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a Shallow Trench Isolation (STI) structure, or a Chemical Vapor Deposition (CVD) oxide structure.
In one embodiment, the depth of the source extending downward from the upper surface is greater than the second concentration peak region.
In another aspect, the present invention provides a method for manufacturing a high voltage device, comprising: forming a semiconductor layer on a substrate; forming a well region in the semiconductor layer, wherein the well region has a first conductivity type; forming a substrate region in the semiconductor layer, the substrate region having a second conductivity type and being connected to the well region in a channel direction; forming a gate on the semiconductor layer, wherein a portion of the substrate region is located right under the gate and connected to the gate, so as to provide an inversion region of the high voltage device during a turn-on operation; and forming a source and a drain under an upper surface of the semiconductor layer and connecting the source and the drain to the upper surface, the source and the drain having a first conductivity type, wherein the source and the drain are respectively located at two sides of the gate, the source is located in the substrate region, the drain is located in the well region away from the substrate region, and a portion of the well region is located between the substrate region and the drain to separate the substrate region and the drain; wherein a first concentration peak region of the substrate region is located right below the source and contacts the source; wherein the first concentration peak region has a higher concentration of the second conductivity type impurity than other regions of the base region.
In one embodiment, a second peak concentration region of the substrate region is located below and connected to the upper surface of the semiconductor layer, wherein the second peak concentration region surrounds and is connected to the source, and the second conductive type impurity concentration of the second peak concentration region is higher than that of the substrate region except for the first peak concentration region.
In one embodiment, the substrate region further includes a first layer formed by a first process step that simultaneously forms another first layer in another device in the semiconductor layer, the first layer extending downward from the upper surface to a depth greater than the source.
In one embodiment, the substrate region further includes a second layer formed by a second process step that simultaneously forms another second layer in another device in the semiconductor layer, the second layer extending downward from the upper surface to a depth greater than the first layer.
In one embodiment, the method further comprises forming a buried layer, wherein at least a portion of the buried layer is formed in the semiconductor layer, the buried layer having the first conductivity type, the buried layer being located directly below the base region and the well region.
In one embodiment, the method further includes forming a drift oxide region over the semiconductor layer, wherein a portion of the gate is directly over and connected to the drift oxide region.
In one embodiment, the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a Shallow Trench Isolation (STI) structure, or a Chemical Vapor Deposition (CVD) oxide structure.
In one embodiment, the depth of the source extending downward from the upper surface is greater than the second concentration peak region.
One advantage of the present invention is that the present invention can disable the parasitic bjt and thereby inhibit the parasitic bjt.
The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of specific embodiments.
Drawings
Fig. 1A and 1B respectively show a top view and a cross-sectional view of a conventional high voltage device.
Fig. 2 is a schematic cross-sectional view illustrating a high voltage device according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view showing a high voltage element according to another embodiment of the present invention.
Fig. 4A-4K are schematic diagrams illustrating a method for fabricating a high voltage device according to an embodiment of the invention.
Description of the symbols in the drawings
100, 200, 300: high voltage element
11, 21, 31: substrate
12, 22, 32: well region
12a, 22a, 32 a: drift region
13, 36: body pole
14, 24, 34: drift oxide region
16, 35: body region
17, 17',27, 27',37, 37': grid electrode
18, 18',28, 28',38, 38': source electrode
19, 29, 39: drain electrode
21',31': semiconductor layer
21a, 31 a: upper surface of
21b, 31 b: lower surface
23: buried layer
25, 35: base region
25a, 35 a: reverse current path
251: first peak concentration region
252: second peak region of concentration
253: first layer
254: second layer
255: third layer
261, 281, 2511, 2521, 2531, 2541, 2551: the photoresist layer
271, 271',371, 371': dielectric layer
272, 272',372, 372': conductive layer
273, 273',373, 373': spacer layer
282, 282': lightly doped region
Detailed Description
The foregoing and other technical and other features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, which proceeds with reference to the accompanying drawings. The drawings in the present invention are schematic and are intended to show the process steps and the up-down order of the layers, and the shapes, thicknesses and widths are not drawn to scale.
Please refer to fig. 2, which is a schematic cross-sectional view illustrating a high voltage device 200 according to an embodiment of the invention. As shown in fig. 2, the high voltage device 200 includes: substrate (substrate)21, semiconductor layer 21', well region 22, drift oxide region 24, base region (bulk region)25, base contact (bulk contact)26, gate 27, source 28, drain 29, first concentration peak region 251, second concentration peak region 252, first layer 253, second layer 254, third layer 255, and buried layer (buried layer) 23. The first concentration peak region 251, the second concentration peak region 252, the first layer 253, the second layer 254, and the third layer 255 may constitute the base region 25. The high voltage device 200 is fabricated by forming the high voltage device 200 from a plurality of cells in a mirror image arrangement of the shared substrate region 25 and the substrate contact 26. Thus, as shown in FIG. 2, source 28 'mirrors source 28, gate 27' mirrors gate 27, and so on.
The semiconductor layer 21 'is formed on the substrate 21, and the semiconductor layer 21' has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 2, the same applies hereinafter). The substrate 21 is, for example but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21 'is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 21'. The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described herein.
Referring to fig. 2, the drift oxide region 24 is formed on the upper surface 21a and connected to the upper surface 21a, and is located on the drift region 22a (as indicated by the dashed line in fig. 2) and connected to the drift region 22 a. A partial gate 27 is located directly above the drift oxide region 24 and connects the drift oxide region 24. The drift oxide region 24 is not limited to a Chemical Vapor Deposition (CVD) oxide structure as shown in fig. 2, but may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. The steps for forming the LOCOS structure, STI structure and CVD oxide structure are well known to those skilled in the art and are not described herein.
The well 22 of the first conductivity type is formed in the semiconductor layer 21', and the well 22 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The base region 25 has a second conductivity type, is formed in the semiconductor layer 21', and is located under the upper surface 21a and connected to the upper surface 21a in a vertical direction. The substrate contact 26 is formed in the substrate region 25, has a second conductivity type, and serves as an electrical contact of the substrate region 25, and the substrate contact 26 is formed under the upper surface 21a and connected to the substrate region 25 of the upper surface 21a in a vertical direction. The base region 25 is formed in the semiconductor layer 21' and connects to the well region 22 in a channel direction (as indicated by the direction of the dotted arrow in fig. 2, the same applies below). The gate electrode 27 is formed on the upper surface 21a of the semiconductor layer 21', and a portion of the substrate region 25 is located right under the gate electrode 27 and connected to the gate electrode 27 in the vertical direction to provide an inversion current path 25a (also referred to as an inversion region) for the high voltage device 200 in the on operation.
With reference to fig. 2, the source 28 and the drain 29 have the first conductivity type, and in the vertical direction, the source 28 and the drain 29 are formed under the upper surface 21a and connected to the upper surface 21a, and the source 28 and the drain 29 are respectively located in the substrate region 25 under the two sides of the gate 27 in the channel direction and in the well region 22 away from the substrate region 25. A portion of well region 22 is located between substrate region 25 and drain 29 to separate substrate region 25 and drain 29. In the channel direction, the drift region 22a is located in the well region 22 between the drain 29 and the substrate region 25, near the upper surface 21a, and serves as a drift current channel for the high voltage device 200 during the on operation. In one embodiment, sources 28 and 28' are electrically connected to substrate contact 26 with a metal silicide layer (not shown).
Referring again to fig. 2, as mentioned above, the substrate region 25 includes the first peak concentration region 251, the second peak concentration region 252, the first layer 253, the second layer 254 and the third layer 255. The first concentration peak region 251 of the body region 25 is located directly below the sources 28 and 28 'and contacts the sources 28 and 28'. In one embodiment, the first peak concentration region 251 has a higher concentration of the second conductive type impurity than other regions of the substrate region 25. The second concentration peak region 252 of the base region 25 is located below the upper surface 21a of the semiconductor layer 21' and connects the upper surface 21a and is in an upper portion of the base region 25. The second peak concentration region 252 surrounds and connects the sources 28 and 28'. In one embodiment, the second concentration peak region 252 has a higher concentration of the second conductive type impurity than the base region 25 except for the first concentration peak region 251. In one embodiment, the depth of the source 28 extending downward from the upper surface 21a is greater than the depth of the second peak concentration region 252 extending downward from the upper surface 21 a.
The first layer 253 is located below the upper surface 21a of the semiconductor layer 21' and connects the upper surface 21a, and is formed by a first process step. The first process step simultaneously forms a further first layer in a further element in the semiconductor layer 21'. That is, the first layer 253 can be formed in the high voltage device 200 and another device simultaneously by using the same photolithography process and the same ion implantation process, without additional manufacturing cost. In one embodiment, the first layer 253 extends downward from the upper surface 21a to a depth greater than the depth of the source electrode 28 extending downward from the upper surface 21 a.
As shown in fig. 2, the second layer 254 is located below the upper surface 21a of the semiconductor layer 21' and connects the upper surface 21a, and is formed by a second process step. The second process step simultaneously forms a further second layer in a further element in the semiconductor layer 21'. That is, the second layer 254 can be formed in the high voltage device 200 and another device simultaneously by using the same photolithography process and the same ion implantation process, without additional manufacturing cost. In one embodiment, the second layer 254 extends downwardly from the top surface 21a to a depth greater than the depth of the first layer 253.
In one embodiment, the substrate region 25 is composed of a first peak concentration region 251, a second peak concentration region 252, a first layer 253, a second layer 254 and a third layer 255. The buried layer 23 is formed in the semiconductor layer 21' and has the first conductivity type, and the buried layer 23 is located directly under the second layer 254 of the substrate region 25 and the well region 22.
In the present invention, the first concentration peak region 251 (and the second concentration peak region 252) having a higher concentration of the second conductive type impurity is used, when the high voltage device 200 is operated, holes in hot carriers generated by a high electric field are injected into the substrate contact 26 through the substrate region 25, and when the hot carrier current flows through the substrate region 25, the hot carrier current flows through the first concentration peak region 251 (and the second concentration peak region 252) having a higher concentration of the second conductive type impurity, compared with the prior art, the voltage drop in the substrate region 25 according to the present invention is lower, so that the parasitic bipolar junction transistor cannot be turned on (the base voltage is insufficient), and further the conduction of the parasitic bipolar junction transistor is suppressed. The parasitic bipolar junction transistor is formed by a portion of the well region 22, a portion of the substrate region 25, a portion of the source 28, and a portion of the substrate contact 26, as illustrated by the solid line NPNBJT circuit symbol in fig. 2.
It should be noted that the inversion current channel 25a is a region where an inversion layer (inversion layer) is formed below the gate 27 to pass the on current due to the voltage applied to the gate 27 during the on operation of the high voltage device 200, and is located between the source 28 and the drift current channel, which is well known in the art and not described herein, and so on.
It should be noted that the drift current path refers to a region through which the high voltage device 200 passes the on current in a drift manner during the on operation, which is well known to those skilled in the art and will not be described herein, and so on.
Note that the upper surface 21a does not mean a completely flat plane, but means a surface of the semiconductor layer 21'. In one embodiment, for example, the portion of the upper surface 21a where the drift oxide region 24 contacts the upper surface 21a may also have a depressed portion.
It should be noted that the gate 27 includes a dielectric layer 271 connected to the upper surface, a conductive layer 272 with conductivity, and a spacer layer 273 with electrical insulation property, which are well known to those skilled in the art and will not be described herein.
The above-mentioned "first conductivity type" and "second conductivity type" refer to that in the high-voltage device, impurities of different conductivity types are doped in the semiconductor composition region (for example, but not limited to, the well region, the body region, the source and drain regions, etc.) so that the semiconductor composition region becomes the first or second conductivity type (for example, but not limited to, the first conductivity type is N-type, and the second conductivity type is P-type, or vice versa). Wherein the first conductivity type is electrically opposite to the second conductivity type.
It should be noted that the high voltage device means that the voltage applied to the drain during normal operation is higher than a specific voltage, such as 5V or 50V, and the lateral distance between the body region 25 and the drain 29 (the length of the drift region 22 a) is adjusted according to the operating voltage applied during normal operation, so that the device can operate at the higher specific voltage. This is well known to those skilled in the art and will not be described herein.
It is noted that one of the technical features of the present invention over the prior art is that: according to the present invention, taking the embodiment shown in fig. 2 as an example, when the high voltage device 200 operates, hot carriers (such as but not limited to holes in an N-type high voltage device) generated by a high electric field are injected into the "hot carrier absorption channel" provided by the substrate contact 26 through the substrate region 25 for absorption. Compared with the prior art, the resistance of the "hot carrier absorption channel" of the present invention is relatively low because the first concentration peak region 251 of the present invention is relatively close to the PN junction formed by the substrate region 25 and the well region 22, and the impurity concentration of the second conductivity type of the first concentration peak region 251 is higher than that of the other portion of the substrate region 25. Therefore, when the hot carriers flow through the "hot carrier absorption channel", the voltage drop of the hot carrier current formed in the substrate region 25 is lower, so that the base voltage of the parasitic bjt formed by the substrate region 25, the source 28 and the well region 22 is lower, which is insufficient to turn on the parasitic bjt and to inhibit the parasitic bjt from turning on when the high-voltage device 22 operates.
Fig. 3 is a schematic cross-sectional view showing a high voltage element 300 according to another embodiment of the present invention. The difference between this embodiment and the embodiment of fig. 2 is that in this embodiment, the high voltage device 300 does not include the first layer and the second layer, and the buried layer can be omitted because there is no first layer and no second layer. The substrate 31, the semiconductor layer 31 ', the well region 32, the drift oxide region 34, the gates 37 and 37', the sources 38 and 38 ', the drain 39, the first peak concentration region 351 and the second peak concentration region 352 of the present embodiment are similar to the substrate 21, the semiconductor layer 21', the well region 22, the drift oxide region 24, the gates 27 and 27 ', the sources 28 and 28', the drain 29, the first peak concentration region 251 and the second peak concentration region 252 of fig. 2, and therefore, a detailed description thereof is omitted.
In the present embodiment, the body region 35 serves as a base region for providing an inversion current path 35 a; the body electrode 36 serves as an electrical contact, i.e., a substrate contact, to the body region 35.
Please refer to fig. 4A-4K, which are schematic diagrams illustrating a method for manufacturing the high voltage device 200 according to an embodiment of the invention. As shown in fig. 4A, a substrate 21 is first provided, and the substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate.
Next, referring to fig. 4B, a buried layer 23 is formed below the well 22. In the vertical direction, the buried layer 23 is formed, for example, on both sides of the junction of the substrate 21 and the semiconductor layer 21 ', a part of the buried layer 23 is located in the substrate 21, and a part of the buried layer 23 is located in the semiconductor layer 21'. The buried layer 23 has a first conductivity type, and for example, but not limited to, first conductivity type impurities are implanted into the substrate 21 in the form of accelerated ions in an ion implantation process step, and the buried layer 23 is formed by thermal diffusion after the semiconductor layer 21' is formed. Wherein a semiconductor layer 21 'is formed on the substrate 21, the semiconductor layer 21' having an upper surface 21a and a lower surface 21B opposite to each other in a vertical direction (as indicated by the solid arrow in fig. 4B, the same applies below). The semiconductor layer 21 'is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 21'. The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described herein.
Well 22 is formed in the semiconductor layer 21', and the well 22 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The well region 22 has a first conductivity type, and impurities of the first conductivity type can be implanted into the semiconductor layer 21' in the form of accelerated ions, for example, but not limited to, by an ion implantation process step, as indicated by the dashed arrow in fig. 4B, to form the well region 22.
Next, referring to fig. 4C, a drift oxide region 24 is formed on the upper surface 21a and connected to the upper surface 21 a. The drift oxide region 24 is electrically insulating, and is not limited to a Chemical Vapor Deposition (CVD) oxide structure as shown in fig. 4C, but may also be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. The drift oxide region 24 is located on the drift region 22a and connected to the drift region 22a (see fig. 4F and fig. 2).
Next, a base region 25 is formed in the semiconductor layer 21'. In one embodiment, forming the base region 25 may include forming the second layer 254, forming the first layer 253, forming the third layer 255, forming the first peak concentration region 251, and forming the second peak concentration region 252. In another embodiment, forming the base region 25 may include forming the third layer 255, forming the first concentration peak region 251, and forming the second concentration peak region 252. Referring to fig. 4D, a second layer 254 is formed in the well 22, wherein the second layer 254 is vertically below the upper surface 21a and is connected to the upper surface 21 a. Second layer 254 has a second conductivity type and the step of forming second layer 254, such as but not limited to, using photoresist layer 2541 formed by a photolithography process step as a mask, dopants of the second conductivity type into well region 22 to form second layer 254. The present embodiment utilizes, for example but not limited to, an ion implantation process step to implant the second conductive type impurity into the well region 22 in the form of accelerated ions, as indicated by the straight dashed arrow in fig. 4D, to form the second layer 254. The above-described process of forming the second layer 254 can also form another second layer in another element in the semiconductor layer 21' at the same time.
Thereafter, referring to fig. 4E, a first layer 253 is formed in the second layer 254, and the first layer 253 is located below the upper surface 21a and connected to the upper surface 21a in the vertical direction. The first layer 253 has a second conductivity type, and the step of forming the first layer 253, such as but not limited to using a photoresist layer 2531 formed by a photolithography process step as a mask, dopes a second conductivity type impurity into the second layer 254 to form the first layer 253. The present embodiment may utilize, for example and without limitation, an ion implantation process step to implant a second conductive type impurity into the second layer 254 in the form of accelerated ions, as illustrated by the straight dashed arrow in fig. 4E, to form the first layer 253. The above-described process of forming the first layer 253 can also form another first layer in another element in the semiconductor layer 21' at the same time. In one embodiment, the first layer 253 extends downward from the upper surface 21a to a depth greater than the depth of the source electrode 28 extending downward from the upper surface 21 a. In one embodiment, the second layer 254 extends downwardly from the top surface 21a to a depth greater than the depth of the first layer 253.
Next, referring to fig. 4F, a third layer 255 is formed in the well 22, wherein the third layer 255 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The third layer 255 has the second conductivity type, and the step of forming the third layer 255, such as but not limited to, using the photoresist layer 2551 formed by the photolithography process as a mask, dopants of the second conductivity type into the well 22 to form the third layer 255. The present embodiment can utilize, for example but not limited to, an ion implantation process step to implant the second conductive type impurity into the well region 22 in the form of accelerated ions, as indicated by the straight dashed arrow in fig. 4F, to form the third layer 255.
Next, referring to fig. 4G, a first peak concentration region 251 is formed in the third layer 255. The first concentration peak region 251 is located in a lower portion of the third layer 255, and is located directly under the sources 28 and 28 'and contacts the sources 28 and 28' (refer to fig. 2 and 4I). The first peak concentration region 251 has the second conductivity type, and the step of forming the first peak concentration region 251, such as but not limited to, using the photoresist layer 2511 formed by the photolithography process step as a mask, dopants of the second conductivity type into the third layer 255 to form the first peak concentration region 251. The present embodiment can utilize, for example but not limited to, an ion implantation process step to implant the second conductive type impurity into the third layer 255 in the form of accelerated ions, as indicated by the straight dashed arrow in fig. 4G, to form the first concentration peak region 251. In one embodiment, the first peak concentration region 251 has a higher concentration of the second conductive type impurity than other regions of the substrate region 25.
Thereafter, referring to fig. 4H, a second peak concentration region 252 is formed in the third layer 255. The second peak concentration region 252 is located in an upper portion of the third layer 255, and is located below the upper surface 21a of the semiconductor layer 21 'and connected to the upper surface 21a, and the second peak concentration region 252 surrounds and is connected to the sources 28 and 28' (refer to fig. 2 and 4I). The second peak concentration region 252 has the second conductivity type, and the step of forming the second peak concentration region 252, such as but not limited to, using the photoresist layer 2521 formed by the photolithography process step as a mask, dopants of the second conductivity type into the third layer 255 to form the second peak concentration region 252. The present embodiment may utilize, for example and without limitation, an ion implantation process step to implant a second conductive type impurity into the third layer 255 in the form of accelerated ions, as indicated by the straight dashed arrow in fig. 4H, to form the second peak concentration region 252. In one embodiment, the second concentration peak region 252 has a higher concentration of the second conductive type impurity than the base region 25 except for the first concentration peak region 251. In one embodiment, the depth of the source 28 extending downward from the upper surface 21a is greater than the depth of the second peak concentration region 252 extending downward from the upper surface 21a (see fig. 4I).
It should be noted that the photoresist layers 2511, 2521 and 2551 may be shared, that is, in one embodiment, the photoresist layer 2551 may be used as the photoresist layers 2511 and 2521, so as to save the process steps and reduce the manufacturing cost.
Next, referring to fig. 4I, dielectric layers 271 and 271 'of the gate electrodes 27 and 27' and conductive layers 272 and 272 'are respectively formed on the upper surface 21a of the semiconductor layer 21', and in a vertical direction (as indicated by the solid arrows in fig. 4I, the same below), a portion of the substrate region 25 is located right below the gate electrodes 27 and 27 'and connected to the gate electrodes 27 and 27', so as to provide a reverse current path 25a (also referred to as an inversion region) of the high voltage device 200 during the turn-on operation.
With continued reference to FIG. 4I, for example, after the dielectric layers 271 and 271 ' and the conductive layers 272 and 272 ' of the gates 27 and 27 ' are formed, lightly doped regions 282 and 282 ' are formed to provide conduction channels under the spacer layers 273 and 273 ' during the conduction operation of the high voltage device 200; this is because the second concentration peak region 252 of the base region 25 under the spacer layers 273 and 273' cannot form an inversion current channel when the high voltage device 200 is in on-state operation. The lightly doped regions 282 and 282 'are formed by, for example, doping the second peak concentration region 252 of the substrate region 25 with impurities of the first conductivity type to form the lightly doped regions 282 and 282'. In this embodiment, for example, but not limited to, an ion implantation process step may be used to implant the first conductive type impurity in the form of accelerated ions into the second peak concentration region 252 of the base region 25, as indicated by the vertical dashed arrows in fig. 4I, to form lightly doped regions 282 and 282'. Since the lightly doped regions 282 and 282 ' have a first conductivity type impurity concentration much lower than the first conductivity type impurity concentration of the sources 28 and 28 ' and the second conductivity type impurity concentration of the substrate contact 26, the lightly doped regions 282 and 282 ' are omitted in the regions where the lightly doped regions 282 and 282 ' overlap the sources 28 and 28 ' and the substrate contact 26, and thus will be omitted in the subsequent figures. As shown in fig. 4I, spacers 273 and 273 ' are formed outside the sides of the conductive layers 272 and 272 ', respectively, to form gates 27 and 27 '.
Please continue to refer to FIG. 4I. As shown in fig. 4I, the source 28 and the drain 28' and the drain 29 are formed below the upper surface 21a and connected to the upper surface 21a in the vertical direction, and the source 28 and the drain 29 are respectively located in the substrate region 25 below the gate 27 outside the channel direction and in the well region 22 away from the substrate region 25 side, and in the channel direction (as indicated by the arrow direction of the horizontal dotted line in fig. 4I, the same applies below), the drift region 22a is located between the drain 29 and the substrate region 25 in the well region 22 close to the upper surface 21a for serving as a drift current channel of the high voltage device 200 in the on operation. The source electrodes 28 and 28 ' and the drain electrode 29 have a first conductivity type, and the source electrodes 28 and 28 ' and the drain electrode 29 are formed by, for example, but not limited to, doping impurities of the first conductivity type into the substrate region 25 and the well region 22 respectively by using the photoresist layer 281 formed by the photolithography process as a mask to form the source electrodes 28 and 28 ' and the drain electrode 29. In this embodiment, for example, but not limited to, an ion implantation process step may be used to implant the first conductive type impurities in the form of accelerated ions, as indicated by the vertical dashed arrows in fig. 4I, into the substrate region 25 and the well region 22 to form the sources 28 and 28' and the drain 29.
Next, referring to fig. 4J, as shown in fig. 4J, a substrate contact 26 is formed in the substrate region 25. The substrate contact 26 has a second conductivity type and serves as an electrical contact for the substrate region 25, and the substrate contact 26 is formed below the upper surface 21a in the substrate region 25 and connected to the upper surface 21a in the vertical direction. The step of forming the substrate contact 26, such as but not limited to, using the photoresist layer 261 formed by the photolithography process as a mask, dopants of the second conductivity type are doped into the substrate region 25 to form the substrate contact 26. In this embodiment, for example, but not limited to, an ion implantation process step may be used to implant the second conductive type impurity into the substrate region 25 in the form of accelerated ions, as indicated by the straight dashed arrow in fig. 4J, to form the substrate contact 26. Wherein the substrate contact 26 has a higher impurity concentration of the second conductivity type than the substrate region 25. And the substrate contact 26 has a second conductivity type impurity concentration lower than the first conductivity type impurity concentration of the source 28.
Referring to fig. 4K, as shown in fig. 4K, the photoresist layer 261 is removed and a metal silicide layer (not shown) may be formed on the substrate contact 26 and the source electrodes 228 and 228' to form the high voltage device 200.
The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as deep well regions, may be added without affecting the primary characteristics of the device; for example, the lithography technique is not limited to the mask technique, but may include electron beam lithography. All of which can be analogized to the teachings of the present invention. In addition, the embodiments described are not limited to a single application, and may be combined, for example, but not limited to, a combination of both embodiments. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, any one of the claims should not be limited thereby.

Claims (16)

1. A high voltage device, comprising:
a semiconductor layer formed on a substrate;
a well region of a first conductivity type, wherein the well region is formed in the semiconductor layer;
A substrate region of a second conductivity type, wherein the substrate region is formed in the semiconductor layer and connected to the well region in a channel direction;
a gate formed on the semiconductor layer, wherein a portion of the substrate region is located right under the gate and connected to the gate to provide an inversion region of the high voltage device during a turn-on operation; and
a source and a drain of the first conductivity type, wherein the source and the drain are formed under and connected to an upper surface of the semiconductor layer, wherein the source and the drain are respectively located at two sides of the gate, the source is located in the substrate region, the drain is located in the well region away from the substrate region, and a portion of the well region is located between the substrate region and the drain to separate the substrate region and the drain;
wherein a first concentration peak region of the substrate region is located right below the source and contacts the source;
wherein the first peak concentration region has a higher concentration of the second conductivity type impurity than other regions of the substrate region.
2. The high voltage device of claim 1, wherein a second peak concentration region of the substrate region is located below and connected to the top surface of the semiconductor layer, wherein the second peak concentration region surrounds and is connected to the source, and the second conductivity type impurity concentration of the second peak concentration region is higher than that of the substrate region except for the first peak concentration region.
3. The high voltage device of claim 1, wherein the substrate region further comprises a first layer formed by a first process step that simultaneously forms another first layer in another device in the semiconductor layer, the first layer extending downward from the top surface to a depth greater than the source electrode.
4. The high voltage device of claim 3, wherein the substrate region further comprises a second layer formed by a second process step, wherein the second process step simultaneously forms another second layer in another device in the semiconductor layer, and the second layer extends downward from the upper surface to a depth greater than the first layer.
5. The high voltage device of claim 1, further comprising a buried layer, at least a portion of which is formed in said semiconductor layer, wherein said buried layer has said first conductivity type, said buried layer being located directly below said base region and said well region.
6. The high voltage device of claim 1, further comprising a drift oxide region formed over the semiconductor layer, wherein a portion of the gate is directly over and connected to the drift oxide region.
7. The high voltage device of claim 6, wherein the drift oxide region comprises a local oxide structure, a shallow trench isolation structure or a chemical vapor deposition oxide structure.
8. The high voltage device of claim 2, wherein the source extends downward from the top surface to a depth greater than the second peak concentration region.
9. A method for fabricating a high voltage device, comprising:
forming a semiconductor layer on a substrate;
forming a well region in the semiconductor layer, wherein the well region has a first conductivity type;
forming a substrate region in the semiconductor layer, the substrate region having a second conductivity type and being connected to the well region in a channel direction;
forming a gate on the semiconductor layer, wherein a portion of the substrate region is located directly under the gate and connected to the gate, so as to provide an inversion region of the high voltage device during a turn-on operation; and
forming a source and a drain under an upper surface of the semiconductor layer and connecting the source and the drain to the upper surface, the source and the drain having a first conductivity type, wherein the source and the drain are respectively located at two sides of the gate, the source is located in the substrate region, the drain is located in the well region away from the substrate region, and a portion of the well region is located between the substrate region and the drain to separate the substrate region and the drain;
wherein a first concentration peak region of the substrate region is located right below the source and contacts the source;
Wherein the first peak concentration region has a higher concentration of the second conductivity type impurity than other regions of the substrate region.
10. The method according to claim 9, wherein a second peak concentration region of the substrate region is located below and connected to the top surface of the semiconductor layer, wherein the second peak concentration region surrounds and is connected to the source, and the second peak concentration region has a higher concentration of the second conductivity type impurity than the substrate region except for the first peak concentration region.
11. The method of claim 9, wherein the substrate region further comprises a first layer formed by a first process step, wherein the first process step forms another first layer in another device in the semiconductor layer at the same time, and the first layer extends downward from the top surface to a depth greater than the source electrode.
12. The method of claim 11, wherein the substrate region further comprises a second layer formed by a second process step, wherein the second process step simultaneously forms another second layer in another device in the semiconductor layer, and the second layer extends downward from the top surface to a depth greater than the first layer.
13. The method of claim 9, further comprising forming a buried layer, wherein at least a portion of the buried layer is formed in the semiconductor layer, the buried layer having the first conductivity type, the buried layer being located directly below the base region and the well region.
14. The method of claim 9, further comprising forming a drift oxide region over the semiconductor layer, wherein a portion of the gate is directly over and connected to the drift oxide region.
15. The method of claim 14, wherein the drift oxide region comprises a local oxide structure, a shallow trench isolation structure or a chemical vapor deposition oxide structure.
16. The method of claim 10, wherein a depth of the source extending downward from the top surface is greater than the second peak concentration.
CN202110648538.3A 2021-01-12 2021-06-10 High voltage device and method for manufacturing the same Pending CN114759090A (en)

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