CN111435683B

CN111435683B - High-voltage element and method for manufacturing same

Info

Publication number: CN111435683B
Application number: CN201910026979.2A
Authority: CN
Inventors: 黄宗义
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2019-01-11
Filing date: 2019-01-11
Publication date: 2023-06-27
Anticipated expiration: 2039-01-11
Also published as: CN111435683A

Abstract

The invention provides a high-voltage element and a manufacturing method thereof. The high voltage element is used in the power stage of the switching power supply circuit to be used as a lower bridge switch. The high voltage device includes at least one lateral diffusion metal oxide semiconductor device and at least one Schottky barrier diode. The lateral diffusion metal oxide semiconductor comprises a well region, a body region, a grid electrode, a source electrode and a drain electrode; the schottky barrier diode includes a schottky metal layer and a schottky semiconductor layer. The Schottky metal layer is electrically connected with the source electrode, and the Schottky semiconductor layer is adjacent to the well region.

Description

High-voltage element and method for manufacturing same

Technical Field

The present invention relates to a high voltage device and a method for manufacturing the same, and more particularly, to a high voltage device and a method for manufacturing the same capable of improving an operation speed and a safe operation area.

Background

Fig. 1A shows a schematic circuit diagram of a typical switching power supply circuit. The switching power supply circuit comprises a control circuit 1 and a power stage circuit 2. As shown, the power stage circuit 2 includes a high voltage element 11 serving as an upper bridge switch and a high voltage element 12 serving as a lower bridge switch, which operate according to an upper bridge signal UG and a lower bridge signal LG, respectively, to convert an input voltage Vin into an output voltage Vout; and an inductor current IL is generated at the inductor 13 of the power stage circuit 2.

Fig. 1B shows a schematic cross-sectional view of a high voltage element 12 used as a lower bridge switch. The high voltage element 12 as shown serves as a lower bridge switch. The high voltage device 12 is a device in which the voltage applied to the drain electrode 129 is higher than 5V in normal operation. Generally, the drain electrode 129 and the body region 125 of the high voltage device 12 have a drift region 122a (as indicated by the dashed line in fig. 1B) therebetween, the drain electrode 129 is separated from the body region 125, and the length of the drift region in the channel direction (as indicated by the dashed arrow in fig. 1B) is adjusted according to the operating voltage applied during the operation of the high voltage device 12. As shown in fig. 1B, the high-voltage element 12 includes: well region 122, drift oxide region 124, body region 125, body electrode 126, gate 127, source 128, and drain 129. The well region 122 is N-type, and is formed on the substrate 121, and the gate 127 covers a portion of the drift oxide region 124.

When the high voltage device 12 is operated, the parasitic diode (as indicated by the broken line diode circuit symbol) formed by the body region 125 and the well region 122 is not turned on during the idle period before the turn-on of the lower bridge switch due to the continuity of the inductor current IL flowing through the inductor 13, but the parasitic diode LD is turned on, and the phase node voltage LX of the phase node PH is lower than the forward voltage (forward voltage) of the parasitic diode LD. Therefore, the parasitic diode LD is formed by the body region 125 and the well region 122, and the reverse recovery time (reverse recovery time, trr) limits the operation speed of the high voltage device 12 and also limits the safe operation area (safe operation area, SOA), wherein the definition of the safe operation area is well known to those skilled in the art and will not be repeated herein.

In view of the above, the present invention provides a high voltage device and a method for manufacturing the same, which can increase the operation speed and the safe operation area, thereby increasing the application range.

Disclosure of Invention

In one aspect, the present invention provides a high voltage device for use in a power stage of a switching power supply circuit as a lower bridge switch, comprising: at least one laterally diffused metal oxide semiconductor (Lateral Diffused Metal Oxide Semiconductor, LDMOS) element comprising: a well region having a first conductivity type formed in a semiconductor layer; a body region of a second conductivity type formed in the well region; the grid electrode is formed above the well region and connected with the well region; and a source and a drain of the first conductivity type, the source and the drain being located in the body region and the well region, respectively, under different sides of the exterior of the gate; and at least one schottky barrier diode (Schottky barrier diode, SBD) comprising: a Schottky metal layer formed on the semiconductor layer, the Schottky metal layer being electrically connected with the source electrode; the Schottky semiconductor layer is formed in the semiconductor layer, forms Schottky contact with the Schottky metal layer, and is adjacent to the well region; wherein, a part of the body region right below the grid between the source electrode and a boundary of the body region defines an inversion region which is used as an inversion current channel of the lateral diffusion metal oxide semiconductor element in a conducting operation; the well region between the body region and the drain defines a drift region for a drift current channel of the LDMOS device in the on operation.

In another aspect, the present invention provides a method for manufacturing a high voltage device for use in a power stage of a switching power supply circuit as a lower bridge switch, the method comprising: forming at least one laterally diffused metal oxide semiconductor (Lateral Diffused Metal Oxide Semiconductor, LDMOS) element, the step of forming the laterally diffused metal oxide semiconductor comprising: forming a well region in a semiconductor layer, the well region having a first conductivity type; forming a body region in the well region, the body region having a second conductivity type; forming a grid above the well region and connected to the well region; forming a source electrode and a drain electrode which are respectively positioned in the body region and the well region below different sides of the outside of the grid electrode, wherein the source electrode and the drain electrode have the first conductivity type; and forming at least one schottky barrier diode (Schottky barrier diode, SBD) element, the step of forming the schottky barrier diode comprising: forming a schottky metal layer on the semiconductor layer, the schottky metal layer being electrically connected to the source electrode; forming a Schottky semiconductor layer in the semiconductor layer, wherein the Schottky semiconductor layer and the Schottky metal layer form Schottky contact, and the Schottky semiconductor layer is adjacent to the well region; wherein, a part of the body region between the source electrode and the well region defines an inversion region which is used as an inversion current channel of the lateral diffusion metal oxide semiconductor element in a conducting operation, and the inversion region is positioned right below a part of the grid electrode; the well region between the body region and the drain defines a drift region for a drift current channel of the LDMOS device in the on operation.

In a preferred embodiment, the high voltage device is formed by a basic unit after mirror image layout, wherein the basic unit comprises: at least a portion of the schottky barrier diode; and at least part of the lateral diffusion metal oxide semiconductor elements are alternately arranged in a mirror image manner in a channel direction and are connected in series to form a power element string when the number of the lateral diffusion metal oxide semiconductor elements is multiple; wherein the schottky barrier diode is adjacent to the power element string in the channel direction.

In a preferred embodiment, the high voltage device is formed by a basic unit after mirror image layout, wherein the basic unit comprises: at least one of the schottky barrier diodes; and at least part of the lateral diffusion metal oxide semiconductor elements are alternately arranged in series in a channel direction when the number of the lateral diffusion metal oxide semiconductor elements is plural; the number of the Schottky barrier diodes is not greater than the number of the lateral diffusion metal oxide semiconductor elements, each Schottky barrier diode is located between the body region and the drain electrode in the corresponding lateral diffusion metal oxide semiconductor element, and the Schottky semiconductor layer is connected with the drift region.

In a preferred embodiment, the at least one schottky barrier diode is located in an isolation region in the high voltage device, and the isolation region is located outside the at least one ldmos.

In a preferred embodiment, the schottky barrier diode further includes two insulating structures respectively located outside of both sides of the schottky metal layer, connected to the schottky semiconductor layer, separated by a schottky channel.

In a preferred embodiment, the schottky barrier diode further includes two channel-side well regions of the second conductivity type, respectively located in the schottky semiconductor layer below both sides of the schottky metal layer, separated by the schottky channel.

In a preferred embodiment, the schottky barrier diode further includes two channel-side body regions of the second conductivity type, respectively located in the schottky semiconductor layer below both sides of the schottky metal layer, separated by the schottky channel, wherein the channel-side body regions and the body regions are formed by the same process step.

In the foregoing embodiment, the schottky barrier diode preferably further includes two channel-side body regions of the second conductivity type, respectively located in the two channel-side body regions, separated by the schottky channel.

In the foregoing embodiment, the schottky barrier diode preferably further includes two polysilicon layers respectively disposed on the two channel-side body regions, and the polysilicon layers and the corresponding channel-side body regions are separated by the corresponding insulating structures.

In a preferred embodiment, the ldmos further comprises a drift oxide region formed on the drift region, the drift oxide region comprising a region oxide (local oxidation of silicon, LOCOS) structure, a shallow trench isolation (shallow trench isolation, STI) structure, or a chemical vapor deposition (chemical vapor deposition, CVD) oxide region.

In a preferred embodiment, the gate includes: a dielectric layer formed on the body region and the well region and connected to the body region and the well region; a conductive layer used as the electric contact of the grid electrode, forming all the dielectric layers and connecting to the dielectric layers; and a spacer layer formed on both sides of the conductive layer to serve as an electrical insulation layer on both sides of the gate.

The objects, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of specific embodiments.

Drawings

Fig. 1A shows a schematic circuit diagram of a typical switching power supply circuit.

Fig. 1B shows a schematic cross-sectional view of a prior art high voltage component 12 used as a lower bridge switch.

Fig. 2 shows a first embodiment of the invention.

Fig. 3 shows a second embodiment of the invention.

Fig. 4A-4C show a third embodiment of the invention.

Fig. 5A-5B show a fourth embodiment of the invention.

Fig. 6A-6B show a fifth embodiment of the invention.

Fig. 7 shows a sixth embodiment of the invention.

Fig. 8 shows a seventh embodiment of the invention.

Fig. 9 shows an eighth embodiment of the invention.

Fig. 10A-10G show a ninth embodiment of the invention.

Description of the symbols in the drawings

1. Control circuit

2. Power stage circuit

11

High voltage components

12, 22, 32, 42, 52, 62

13. Inductance

121

Substrate

221, 321, 421, 521, 621, 721, 821, 921

122 222, 322, 422, 522, 622 well regions

122a,222a,322a,422a,522a drift region

124

Drift oxide regions

224, 324, 424, 524, 624

125

Body regions

225, 325, 425, 525, 625

126

Body poles

226, 326, 426, 526, 626

127 Gate of 227, 327, 427, 527, 627, 935

128 Sources of 228, 328, 428, 528, 628

129

Drain electrodes

229, 329, 429, 529, 629

221',321',421',521',621',721',821',921' semiconductor layers

221a,321a, 521a upper surface

221b,321b, 521b lower surface

223 Metal silicide layers 323, 423, 523, 623

223a, 627a a inversion region

231 Layer of 331, 431, 531, 631, 731, 831, 931 schottky metal

232 332, 432, 532, 632, 732, 832, 932 schottky semiconductor layers

233 333, 633, 733, 833 insulating structure

234 The schottky channels of 334, 434, 534, 634, 735, 836, 937

734. Channel side well region

834 934 channel side body regions

835. Polysilicon layer

2251 2261, 2281 photoresist layers

2271 3271, 4271, 5271, 6271, 9351 dielectric layers

2272 3272, 4272, 5272, 6272, 9352 conductive layer

2273 3273, 4273, 5273, 6273, 9353 spacer layer

2281. Lightly doped region

AA ', BB', CC ', FF', axis

CELL LDMOS element region

DD ', EE ' GG ' tangent line

GND ground potential

IL inductor current

IMP1, IMP2, IMP3, IMP4 ion implantation process steps

ISO isolation zone

LD parasitic diode

LG (light-emitting diode) lower bridge signal

LT, LT', LT1, LT2, LT3, LT4, LT5, LT6, LT7, LT8, LT9LDMOS element

LX phase node voltage

M1, M1', M2, M2', M3, M3', M4, M4' basic units

ML, ML', ML1, ML2, ML3 metal wire

PDS power element string

PH phase node

SD, SD', SD1, SD2, SD3, SD4, SD5, SD6, SD7 Schottky barrier diode

UG bridge signal

Vin input voltage

Vout output voltage

Detailed Description

The foregoing and other technical aspects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments, which proceeds with reference to the accompanying drawings. The drawings in the present invention are schematic and are mainly intended to represent the process steps and the upper and lower order relationship between the layers, and the shapes, thicknesses and widths are not drawn to scale.

Referring to fig. 2, a first embodiment of the present invention is shown. Fig. 2 shows a schematic cross-sectional view of a high voltage element 22 for use as a lower bridge switch in a power stage for a switched power supply circuit. As shown in fig. 2, the high-voltage element 22 includes: lateral diffusion metal oxide semiconductor (Lateral Diffused Metal Oxide Semiconductor, LDMOS) devices LT and LT 'and schottky barrier diodes (Schottky barrier diode, SBD) SD and SD'. The LDMOS element LT includes: well 222, drift oxide 224, body 225, body 226, gate 227, source 228, and drain 229.

The semiconductor layer 221 'is formed on the substrate 221, and the semiconductor layer 221' has an upper surface 221a and a lower surface 221b opposite to each other in a vertical direction (as indicated by a solid arrow direction in fig. 2, the same applies hereinafter). The substrate 221 is, for example and without limitation, a P-type or N-type semiconductor substrate. The semiconductor layer 221 'is formed on the substrate 221, for example, by an epitaxial process, or a portion of the substrate 221 is used as the semiconductor layer 221'. The manner of forming the semiconductor layer 221' is well known to those skilled in the art, and will not be described herein.

With continued reference to fig. 2, a drift oxide region 224 is formed on the upper surface 221a and is connected to the upper surface 221a, and is located directly above a portion of the drift region 222a (as shown by the dashed box in the LDMOS device LT in fig. 2) and is connected to the drift region 222a. The drift oxide region 224 may be, for example but not limited to, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure.

The well region 222 has a first conductivity type and is formed in the semiconductor layer 221', and the well region 222 is located under the upper surface 221a and connected to the upper surface 221a in a vertical direction. The well 222 is formed by at least one ion implantation process step, for example. The body region 225 has a second conductivity type and is formed in the well region 222, and the body region 225 is located under the upper surface 221a and connected to the upper surface 221a in a vertical direction. The body electrode 226 has a second conductivity type for use as an electrical contact to the body region 225. In a vertical direction, the body electrode 226 is formed below the upper surface 221a and connected to the body region 225 of the upper surface 221a. The gate electrode 227 is formed on the upper surface 221a of the semiconductor layer 221', and in the vertical direction, a portion of the body region 225 is located directly under the gate electrode 227 and connected to the gate electrode 227 to provide an inversion region 223a of the high voltage device 22 in the on operation, the inversion region 223a being located directly under a portion of the gate electrode 227 and connected to the gate electrode 227.

With continued reference to fig. 2, the source 228 and the drain 229 have a first conductivity type, in a vertical direction, the source 228 and the drain 229 are formed under the upper surface 221a and connected to the upper surface 221a, and the source 228 and the drain 229 are respectively located in the body region 225 under the outside of the gate 227 in a channel direction (as indicated by a dotted arrow in the figure, and the well region 222 on a side away from the body region 225), and in the channel direction, the drift region 222a is located between the drain 229 and the body region 225 in the well region 222 near the upper surface 221a for serving as a drift current channel of the LDMOS device LT in the on operation.

It should be noted that, the inversion region 223a refers to a region under the gate 227 where the inversion layer is formed to pass the on-current due to the voltage applied to the gate 227 during the on operation of the LDMOS device LT, and is well known to those skilled in the art, and the disclosure of the present invention is omitted herein.

It should be noted that the first conductivity type and the second conductivity type may be P-type or N-type, and when the first conductivity type is P-type, the second conductivity type is N-type; when the first conductivity type is N type, the second conductivity type is P type.

It should be noted that, the drift current path refers to a region where the high voltage device 200 allows the on current to pass in a drifting manner during the on operation, which is well known to those skilled in the art, and will not be described herein.

Note that the upper surface 221a does not refer to a completely flat plane, but refers to one surface of the semiconductor layer 221'. In this embodiment, for example, the upper surface 221a of the portion of the drift oxide region 224 in contact with the semiconductor layer 221' has a depressed portion.

It should be noted that in a preferred embodiment, the gate 227 includes a dielectric layer 2271 connected to the upper surface, a conductive layer 2272 having conductivity, and a spacer layer 2273 having electrical insulation properties. The dielectric layer 2271 is formed on the body region 225 and the well region 222, and is connected to the body region 225 and the well region 222. The conductive layer 2272 is used as an electrical contact for the gate electrode 227, and is formed over all of the dielectric layers 2271 and connected to the dielectric layers 2271. Spacer layer 2273 is formed on both sides of conductive layer 2272 to serve as an electrically insulating layer on both sides of gate 227.

In addition, it should be noted that, in normal operation, the high voltage device means that the voltage applied to the drain is higher than a specific voltage, for example, 5V, and the channel direction distance (the length of the drift region 222 a) between the body region 225 and the drain 229 is adjusted according to the operation voltage received in normal operation, so that the high specific voltage can be operated. This is well known to those skilled in the art and will not be described in detail herein.

With continued reference to fig. 2, the schottky barrier diode SD includes a schottky metal layer 231 and a schottky semiconductor layer 232. The schottky metal layer 231 is formed on the semiconductor layer 221', and in a vertical direction, the schottky metal layer 231 is located on the upper surface 221a and connected to the upper surface 221a; the schottky metal layer 231 and the source electrode 228 are electrically connected via a metal wire ML. The schottky semiconductor layer 232 is formed in the semiconductor layer 221', the schottky semiconductor layer 232 and the schottky metal layer 231 form schottky contact, and the schottky semiconductor layer 232 is adjacent to the well region 222, and in a vertical direction, the schottky semiconductor layer 232 is located under the upper surface 221a and connected to the upper surface 221a. In the present embodiment, the schottky semiconductor layer 232 and the well region 222 are formed by the same process step, and are adjacent to each other in the channel direction and the vertical direction as shown in the drawing.

The schottky barrier diode SD further includes, for example, two insulating structures 233 respectively located outside the two sides of the schottky metal layer 231, connected to the schottky semiconductor layer 232, and separated by the schottky channel 234. The schottky channel 234 is a path that provides a reverse current flowing through the schottky barrier diode SD when the schottky barrier diode SD is turned on. The insulating structure 233, such as, but not limited to, a shallow trench isolation (shallow trench isolation, STI) structure as shown, may also be a region oxide (local oxidation of silicon, LOCOS) structure. The insulating structure 233 may be formed simultaneously with the drift oxide region 224 using the same process steps.

With continued reference to fig. 2, the high voltage device 22 is formed by a basic unit M1 centered on the AA' axis and having a mirror (layout) configuration, wherein the basic unit M1 includes: at least a part of the schottky barrier diode SD; and at least partially laterally diffusing the metal oxide semiconductor element LT. In this embodiment, as shown in the drawing, the schottky barrier diode SD is divided into a left half and a right half in the lateral direction, and the right half of the schottky barrier diode SD is used as a part of the basic cell M1, and the left half of the schottky barrier diode SD is formed after mirror layout. In the present embodiment, as shown in the figure, the basic cell M1 includes a complete drift oxide region 224, a gate 227, a source 228, and a drain 229, and a portion of the well region 222, the body region 225, and the body electrode 226; the left half of the body region 225 and the left half of the body electrode 226 are used as a part of the basic unit M1, and the right half of the body region 225 and the right half of the body electrode 226 are formed after mirror layout. The basic unit M1 is subjected to mirror layout to form a basic unit M1', and the mirror layout can be repeated to form the high voltage device 22. The basic unit M1' includes: at least a part of the schottky barrier diode SD'; and at least partially laterally diffusing the metal oxide semiconductor element LT'. It should be noted that, the basic unit M1' is an LDMOS element LT ' formed by a mirror image layout of the basic unit M1 on the right side of the AA ' as the axis; of course, according to the present invention, the basic unit M1 may be arranged in a left mirror image to form other LDMOS devices.

It should be noted that, in the present embodiment, in all LDMOS devices, such as LDMOS devices LT and LT', all well regions 222 are electrically connected to each other, all body regions 225 are electrically connected to each other, all body poles 226 are electrically connected to each other, all gates 227 are electrically connected to each other, all sources 228 are electrically connected to each other, and all drains 229 are electrically connected to each other. In all schottky barrier diodes, such as schottky barrier diodes SD and SD', all schottky metal layers 231 are electrically connected to each other and all schottky semiconductor layers 232 are electrically connected to each other. In a preferred embodiment, source 228 and body 226 are electrically connected to LDMOS device LT by silicide layer 223 as shown.

It is worth noting that the present invention is superior to one of the technical features of the prior art, in that: in accordance with the present invention, taking the embodiment shown in fig. 2 as an example, the high voltage device 22 includes schottky barrier diodes SD and SD 'in addition to the LDMOS devices LT and LT'. Since the reverse recovery time of the schottky barrier diodes SD and SD' is shorter than that of the parasitic diode LD, the operation speed of the high voltage element 22 can be remarkably improved according to the present invention; in addition, since the current can flow through the schottky barrier diodes SD and SD' during the idle period before the lower bridge switch is turned on, the current flowing through the parasitic diode LD is greatly reduced, the high voltage device 22 is prevented from being damaged due to the reverse current flowing through the parasitic diode LD, the safe operation area is improved, and the application range is further increased.

Referring to fig. 3, a second embodiment of the present invention is shown. Fig. 3 shows a schematic cross-sectional view of a high voltage element 32 for use as a lower bridge switch in a power stage for a switched power supply circuit. As shown in fig. 3, the high voltage element 32 is formed by a basic unit M2 centering on the BB' axis, after being subjected to a mirror (mirror) layout (layout), wherein the basic unit M2 includes: at least a part of the schottky barrier diode SD1; and LDMOS devices LT1 and LT2 and a portion of LDMOS device LT3.

In this embodiment, as shown in the drawing, the schottky barrier diode SD1 is divided into a left half and a right half in the lateral direction, and the right half of the schottky barrier diode SD1 is used as a part of the basic cell M2, and the left half of the schottky barrier diode SD1 is formed after mirror layout. In this embodiment, as shown, the LDMOS device LT1 includes a well region 322, a drift oxide region 324, a body region 325, a body electrode 326, a gate 327, a source 328, and a drain 329. The LDMOS devices LT1 and LT2 are mirror images of each other and share a body region 325 and a body electrode 326. Wherein the LDMOS devices LT2 and LT3 are arranged mirror images of each other and share the drain 329. The basic unit M2 is subjected to mirror layout to form a basic unit M2', and the mirror layout can be repeated to form the high voltage device 32. In the present embodiment, the basic unit M2 includes a plurality of LDMOS devices LT1 and LT2 and a portion of LDMOS device LT3, and the plurality of LDMOS devices LT1 and LT2 and the portion of LDMOS device LT3 are alternately arranged in mirror image in series in the channel direction to form a power device string, and the schottky barrier diode SD1 is adjacent to the power device string in the channel direction.

The semiconductor layer 321 'is formed on the substrate 321, and the semiconductor layer 321' has an upper surface 321a and a lower surface 321b opposite to each other in a vertical direction (as indicated by a solid arrow direction in fig. 3, the same applies hereinafter). The substrate 321 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 321 'is formed on the substrate 321, for example, by an epitaxial process, or a portion of the substrate 321 is used as the semiconductor layer 321'. The manner of forming the semiconductor layer 321' is well known to those skilled in the art, and will not be described herein.

With continued reference to fig. 3, a drift oxide region 324 is formed on the upper surface 321a and is connected to the upper surface 321a, and is located directly above a portion of the drift region 322a (as shown by the dashed box in the LDMOS device LT1 of fig. 3) and is connected to the drift region 322a. The drift oxide region 324 may be, for example but not limited to, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure.

The well region 322 has a first conductivity type and is formed in the semiconductor layer 321', and the well region 322 is located under the upper surface 321a and connected to the upper surface 321a in a vertical direction. The well region 322 is formed, for example, by at least one ion implantation process step. The body region 325 has a second conductivity type and is formed in the well region 322, and the body region 325 is located under the upper surface 321a and connected to the upper surface 321a in a vertical direction. The body electrode 326 has a second conductivity type for serving as an electrical contact of the body region 325. In the vertical direction, the body electrode 326 is formed under the upper surface 321a and connected to the body region 325 of the upper surface 321a. The gate electrode 327 is formed on the upper surface 321a of the semiconductor layer 321', and in the vertical direction, a portion of the body region 325 is located directly under the gate electrode 327 and connected to the gate electrode 327, so as to provide an inversion region of the high voltage device 32 in the on operation, and the inversion region is located directly under a portion of the gate electrode 327 and connected to the gate electrode 327.

With continued reference to fig. 3, the source 328 and the drain 329 have a first conductivity type, in a vertical direction, the source 328 and the drain 329 are formed under the upper surface 321a and connected to the upper surface 321a, and the source 328 and the drain 329 are respectively located in the body region 325 under the outside of the gate 327 in a channel direction (as indicated by a dotted arrow in the figure, and in the well region 322 on a side away from the body region 325), and in the channel direction, the drift region 322a is located between the drain 329 and the body region 325 in the well region 322 near the upper surface 321a for serving as a drift current channel of the LDMOS device LT1 in the on operation.

It should be noted that in a preferred embodiment, gate 327 includes dielectric layer 3271 connected to the upper surface, conductive layer 3272 having conductivity, and spacer layer 3273 having electrical insulation properties. The dielectric layer 3271 is formed on the body region 325 and the well region 322, and is connected to the body region 325 and the well region 322. The conductive layer 3272 serves as an electrical contact for the gate 327, is formed over all of the dielectric layers 3271 and is connected to the dielectric layers 3271. Spacer layer 3273 is formed on both sides of conductive layer 3272 to act as an electrical insulation layer on both sides of gate 327.

With continued reference to fig. 3, the schottky barrier diode SD1 includes a schottky metal layer 331, a schottky semiconductor layer 332, and two insulating structures 333. The schottky metal layer 331 is formed on the semiconductor layer 321', and in a vertical direction, the schottky metal layer 331 is located on the upper surface 321a and connected to the upper surface 321a; the schottky metal layer 331 is electrically connected to the source electrode 328 via a metal line ML 1. The schottky semiconductor layer 332 is formed in the semiconductor layer 321', the schottky semiconductor layer 332 forms a schottky contact with the schottky metal layer 331, and the schottky semiconductor layer 332 is adjacent to the well region 322, and the schottky semiconductor layer 332 is located under the upper surface 321a and connected to the upper surface 321a in a vertical direction. In the present embodiment, the schottky semiconductor layer 332 and the well region 322 are formed by the same process step and are adjacent to each other in the channel direction and the vertical direction as shown in the drawing.

Two insulating structures 333, which are respectively located outside the two sides of the schottky metal layer 331, are connected to the schottky semiconductor layer 332 and are separated by the schottky channel 334. The schottky channel 334 is a path that provides a reverse current flowing through the schottky barrier diode SD1 when the schottky barrier diode SD1 is turned on. The insulating structure 333 may be, for example and without limitation, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure. The insulating structure 333 may be formed simultaneously using the same process steps as the drift oxide region 324.

It should be noted that, in the present embodiment, in all LDMOS devices, such as LDMOS devices LT1, LT2 and LT3, all well regions 322 are electrically connected to each other, all body regions 325 are electrically connected to each other, all body poles 326 are electrically connected to each other, all gates 327 are electrically connected to each other, all sources 328 are electrically connected to each other, and all drains 329 are electrically connected to each other. In a preferred embodiment, source 328 is electrically connected to body 326 in LDMOS device LT1 by a metal silicide layer 323 as shown.

Referring to fig. 4A-4C, a third embodiment of the present invention is shown. Fig. 4A shows a top view of the high voltage device 42 used as a lower bridge switch in a power stage of a switching power supply circuit. Fig. 4B and 4C show schematic cross-sectional views of the high voltage device 42 of fig. 4A, DD 'and EE', respectively. As shown in fig. 4A to 4C, the high voltage element 42 is formed by a basic unit M3 centering on the CC' axis, after mirror (layout), wherein the basic unit M3 includes: schottky barrier diode SD2 and part of LDMOS element LT4.

In this embodiment, as shown in fig. 4A-4C, the LDMOS device LT4 includes a well region 422, a drift oxide region 424, a body region 425, a body electrode 426, a gate 427, a source 428, and a drain 429. Wherein LDMOS devices LT4 and LT5 are mirror images of each other and share body region 425 and body electrode 426. The basic unit M3 is subjected to mirror layout to form a basic unit M3', and the mirror layout can be repeated to form the high voltage device 42. In the present embodiment, the basic unit M3 includes a portion of the LDMOS element LT4 and a schottky barrier diode SD2, wherein the schottky barrier diode SD2 is located between the body region 425 and the drain 429 in the corresponding LDMOS element LT4, and the schottky semiconductor layer 432 is connected to the drift region 422 a.

The semiconductor layer 421 'is formed on the substrate 421, and the semiconductor layer 421' has an upper surface 421a and a lower surface 421B opposite to each other in a vertical direction (as indicated by solid arrows in fig. 4B and 4C, which are the same below). The substrate 421 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 421 'is formed on the substrate 421, for example, by an epitaxial process, or a portion of the substrate 421 is used as the semiconductor layer 421'. The manner of forming the semiconductor layer 421' is well known to those skilled in the art, and will not be described herein.

With continued reference to fig. 4A-4C, a drift oxide region 424 is formed on the upper surface 421a and is connected to the upper surface 421a, and is located directly above a portion of the drift region 422a (as shown by the thick dashed box in the LDMOS device LT4 in fig. 4B and 4C) and is connected to the drift region 422a. The drift oxide region 424 may be, for example but not limited to, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure.

The well region 422 has a first conductivity type and is formed in the semiconductor layer 421', and in a vertical direction, the well region 422 is located under the upper surface 421a and connected to the upper surface 421a. The well 422 is formed, for example, by at least one ion implantation process step. The body region 425 has a second conductivity type and is formed in the well region 422, and the body region 425 is located under the upper surface 421a and connected to the upper surface 421a in a vertical direction. The body electrode 426 has a second conductivity type for use as an electrical contact for the body region 425. In the vertical direction, the body electrode 426 is formed under the upper surface 421a and connected to the body region 425 of the upper surface 421a. The gate 427 is formed on the upper surface 421a of the semiconductor layer 421', and in a vertical direction, a portion of the body region 425 is located directly under the gate 427 and connected to the gate 427, so as to provide an inversion region of the high voltage device 42 in a turn-on operation, the inversion region being located directly under a portion of the gate 427 and connected to the gate 427.

With continued reference to fig. 4A-4C, the source 428 and the drain 429 have a first conductivity type, in a vertical direction, the source 428 and the drain 429 are formed under the upper surface 421a and are connected to the upper surface 421a, and the source 428 and the drain 429 are respectively located in the body region 425 under the outside of the gate 427 in the channel direction (as indicated by the dotted arrow, the same applies below) and in the well region 422 away from the body region 425 side, and in the channel direction, the drift region 422a is located between the drain 429 and the body region 425, in the well region 422 near the upper surface 421a, for serving as a drift current channel of the LDMOS device LT4 in the on operation.

It should be noted that in a preferred embodiment, as shown in fig. 4B, the gate 427 includes a dielectric layer 4271 connected to the upper surface, a conductive layer 4272 having conductivity, and a spacer layer 4273 having electrical insulation property. The dielectric layer 4271 is formed on the body region 425 and the well region 422, and is connected to the body region 425 and the well region 422. The conductive layer 4272 is used as an electrical contact for the gate 427, and is formed on all of the dielectric layers 4271 and connected to the dielectric layers 4271. Spacer layers 4273 are formed on both sides of conductive layer 4272 to act as an electrically insulating layer on both sides of gate 427.

With continued reference to fig. 4A-4C, schottky barrier diode SD2 includes schottky metal layer 431 and schottky semiconductor layer 432. The schottky metal layer 431 is formed on the semiconductor layer 421', and in a vertical direction, the schottky metal layer 431 is located on the upper surface 421a and connected to the upper surface 421a; the schottky metal layer 431 is electrically connected to the source electrode 428 via a metal line ML 2. The schottky semiconductor layer 432 is formed in the semiconductor layer 421' as illustrated by the thin frame line in fig. 4C, the schottky semiconductor layer 432 forms a schottky contact with the schottky metal layer 431, and the schottky semiconductor layer 432 is connected to the drift region 422a in the well region 422, and the schottky semiconductor layer 432 is located under the upper surface 421a and connected to the upper surface 421a in the vertical direction. In the present embodiment, the schottky semiconductor layer 432 and the well region 422 are formed by the same process step, and are adjacent to each other in the channel direction and the vertical direction as shown in the drawing.

This embodiment differs from the first embodiment in that in this embodiment, as shown in fig. 4A and 4C, the schottky barrier diode SD2 is directly above the drift region 422a, a hole is opened downward from the gate 427, through the drift region 422a, and the schottky barrier diode SD2 is arranged therein. Thus, the LDMOS element LT4 corresponds to the schottky barrier diode SD2.

It should be noted that, in the present embodiment, in all LDMOS devices, such as LDMOS devices LT4 and LT5, all well regions 422 are electrically connected to each other, all body regions 425 are electrically connected to each other, all body poles 426 are electrically connected to each other, all gates 427 are electrically connected to each other, all sources 428 are electrically connected to each other, and all drains 429 are electrically connected to each other. In a preferred embodiment, source 428 and body 426 of LDMOS device LT4 are electrically connected by silicide layer 423 as shown.

Referring to fig. 5A-5B, a fourth embodiment of the present invention is shown. Fig. 5A shows a top view of a high voltage device 52 used as a lower bridge switch in a power stage of a switching power supply circuit. Fig. 5B shows a schematic cross-sectional view of the high-voltage element 52 taken along line GG' in fig. 5A. As shown in fig. 5A to 5B, the high voltage element 52 is formed by a basic unit M4 centering on the FF' axis, after mirror (layout), wherein the basic unit M4 includes: schottky barrier diode SD3 and portions of LDMOS element LT6, LDMOS element LT7 and LDMOS element LT8.

In this embodiment, as shown in fig. 5A-5B, the LDMOS device LT7 includes a well region 522, a drift oxide region 524, a body region 525, a body electrode 526, a gate 527, a source 528, and a drain 529. Wherein LDMOS devices LT7 and LT8 are mirror images of each other and share body region 525 and body electrode 526; LDMOS elements LT6 and LT7 are adjacent in the channel direction and share drain 529, with schottky barrier diode SD3 located between body region 525 and drain 529 in the corresponding LDMOS element LT 6. In this embodiment, the basic unit M4 includes an LDMOS element LT7, a portion of the LDMOS element LT6, and a portion of the LDMOS element LT8, and is connected in series in a channel direction in an alternating mirror arrangement except for a schottky barrier diode SD3, where the schottky barrier diode SD3 is located between the body region 525 and the drain electrode 529 of the corresponding LDMOS element LT6, that is, in the power element string. The basic unit M4 is subjected to mirror layout to form a basic unit M4', and the mirror layout may be repeated to form the high voltage device 52. In the present embodiment, the schottky barrier diode SD3 is located between the body region 525 and the drain electrode 529 in the corresponding LDMOS element LT6, and the schottky semiconductor layer 532 is connected to the drift region 522 a.

The semiconductor layer 521 'is formed on the substrate 521, and the semiconductor layer 521' has an upper surface 521a and a lower surface 521B opposite to each other in a vertical direction (as indicated by solid arrow directions in fig. 4B and 4C, which are the same below). The substrate 521 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 521 'is formed on the substrate 521, for example, by an epitaxial process, or a portion of the substrate 521 is used as the semiconductor layer 521'. The manner of forming the semiconductor layer 521' is well known to those skilled in the art, and will not be described herein.

With continued reference to fig. 5A-5B, a drift oxide region 524 is formed on the upper surface 521a and is connected to the upper surface 521a, and is located directly above a portion of the drift region 522a (as shown by the thick dashed box in the LDMOS device LT7 in fig. 5B) and is connected to the drift region 522a. The drift oxide region 524 may be, for example but not limited to, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure.

The well 522 has a first conductivity type and is formed in the semiconductor layer 521', and in a vertical direction, the well 522 is located below the upper surface 521a and connected to the upper surface 521a. The well 522 is formed, for example, by at least one ion implantation process step. The body region 525 has a second conductivity type, is formed in the well region 522, and is located under the upper surface 521a and connected to the upper surface 521a in the vertical direction. The body electrode 526 has a second conductivity type for serving as an electrical contact of the body region 525, and the body electrode 526 is formed under the upper surface 521a in a vertical direction and connected to the body region 525 of the upper surface 521a. The gate electrode 527 is formed on the upper surface 521a of the semiconductor layer 521', and in a vertical direction, a portion of the body region 525 is located directly under the gate electrode 527 and connected to the gate electrode 527, so as to provide a reverse region of the high voltage device 52 in a turn-on operation, the reverse region being located directly under a portion of the gate electrode 527 and connected to the gate electrode 527.

With continued reference to fig. 5A-5B, the source 528 and the drain 529 have the first conductivity type, in the vertical direction, the source 528 and the drain 529 are formed under the upper surface 521a and connected to the upper surface 521a, and the source 528 and the drain 529 are respectively located in the body region 525 under the outside of the gate 527 in the channel direction (as indicated by the dotted arrow in the figure, the same applies below) and in the well region 522 away from the side of the body region 525, and in the channel direction, the drift region 522a is located between the drain 529 and the body region 525, in the well region 522 near the upper surface 521a, for serving as a drift current channel of the LDMOS element LT7 in the on operation.

It should be noted that, in a preferred embodiment, as shown in fig. 5B, the gate 527 includes a dielectric layer 5271 connected to the upper surface, a conductive layer 5272 having conductivity, and a spacer layer 5273 having electrical insulation properties. The dielectric layer 5271 is formed on the body region 525 and the well region 522, and is connected to the body region 525 and the well region 522. The conductive layer 5272 serves as an electrical contact for the gate 527, and is formed over all of the dielectric layers 5271 and connected to the dielectric layers 5271. Spacer layers 5273 are formed on both sides of the conductive layer 5272 as electrically insulating layers on both sides of the gate 527.

With continued reference to fig. 5A-5B, schottky barrier diode SD3 includes schottky metal layer 531 and schottky semiconductor layer 532. The schottky metal layer 531 is formed on the semiconductor layer 521', and in a vertical direction, the schottky metal layer 531 is located on the upper surface 521a and connected to the upper surface 521a; the schottky metal layer 531 and the source electrode 528 are electrically connected via a metal wire. The schottky semiconductor layer 532 is formed in the semiconductor layer 521', as illustrated by the thin frame line in fig. 5B, the schottky semiconductor layer 532 forms a schottky contact with the schottky metal layer 531, and the schottky semiconductor layer 532 is connected to the drift region 522a in the well region 522, and the schottky semiconductor layer 532 is located under the upper surface 521a and connected to the upper surface 521a in the vertical direction. In the present embodiment, the schottky semiconductor layer 532 and the well region 522 are formed by the same process step and are adjacent to each other in the channel direction and the vertical direction as shown in the drawing.

The present embodiment is different from the third embodiment in that, in the present embodiment, as shown in fig. 5A and 5B, the schottky barrier diode SD3 is located in the LDMOS element LT6, and the LDMOS element LT6 is connected in series with a plurality of LDMOS elements to form the basic unit M4.

Note that in this embodiment, in all LDMOS elements, such as LDMOS elements LT6, LT7, and LT8, all well regions 522 are electrically connected to each other, all body regions 525 are electrically connected to each other, all body poles 526 are electrically connected to each other, all gates 527 are electrically connected to each other, all sources 528 are electrically connected to each other, and all drains 529 are electrically connected to each other. In a preferred embodiment, in LDMOS device LT7, source 528 is electrically connected to body 526 by silicide layer 523 as shown.

Referring to fig. 6A-6B, a fifth embodiment of the present invention is shown. Fig. 6A shows a schematic top view of a high voltage device 62 used as a lower bridge switch in a power stage of a switching power supply circuit. Fig. 6B shows a schematic cross-sectional view of the schottky barrier diode SD4 and the LDMOS device LT9 connected thereto in fig. 6A.

As shown in fig. 6A, the high voltage device 62 includes an LDMOS device region CELL and an isolation region ISO. The LDMOS device region CELL includes a plurality of power device strings PDS, each having a plurality of LDMOS devices LT9 connected in series in an alternating mirror arrangement to form a power device string PDS. The isolation region ISO is located outside the LDMOS device region CELL and includes at least one schottky barrier diode SD4, wherein the schottky barrier diode SD4 is connected to the LDMOS device LT 9. The isolation region ISO is used to isolate the high voltage device 62 from other devices on the same substrate.

As shown in fig. 6B, the high-voltage element 62 includes: lateral diffusion metal oxide semiconductor (Lateral Diffused Metal Oxide Semiconductor, LDMOS) devices LT and LT 'and schottky barrier diodes (Schottky barrier diode, SBD) SD and SD'. The LDMOS element LT9 includes: well 622, drift oxide 624, body 625, body 626, gate 627, source 628 and drain 629.

The semiconductor layer 621 'is formed on the substrate 621, and the semiconductor layer 621' has an upper surface 621a and a lower surface 621B opposite to each other in a vertical direction (as indicated by a solid arrow direction in fig. 6B, the same applies hereinafter). The substrate 621 is, for example and without limitation, a P-type or N-type semiconductor substrate. The semiconductor layer 621 'is formed on the substrate 621, for example, by an epitaxial process step, or a portion of the substrate 621 is used as the semiconductor layer 621'. The manner of forming the semiconductor layer 621' is well known to those skilled in the art and will not be described herein.

With continued reference to fig. 6B, a drift oxide region 624 is formed on the upper surface 621a and is connected to the upper surface 621a, and is located directly above a portion of the drift region 622a (shown as a dashed box in the LDMOS device LT9 in fig. 6B) and is connected to the drift region 622a. The drift oxide region 624 may be, for example but not limited to, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure.

The well 622 has a first conductivity type and is formed in the semiconductor layer 621', and in a vertical direction, the well 622 is located under the upper surface 621a and connected to the upper surface 621a. The well 622 is formed, for example, by at least one ion implantation process step. The body region 625 has a second conductivity type, is formed in the well region 622, and is located under the upper surface 621a and connected to the upper surface 621a in the vertical direction. The body electrode 626 has a second conductivity type for use as an electrical contact for the body region 625. In the vertical direction, the body electrode 626 is formed under the upper surface 621a and connected to the body region 625 of the upper surface 621a. The gate 627 is formed on the upper surface 621a of the semiconductor layer 621', and in a vertical direction, a portion of the body region 625 is located directly under the gate 627 and connected to the gate 627, so as to provide an inversion region 623a of the high voltage device 62 in a turn-on operation, the inversion region 623a being located directly under a portion of the gate 627 and connected to the gate 627.

With continued reference to fig. 6B, the source electrode 628 and the drain electrode 629 have a first conductivity type, in a vertical direction, the source electrode 628 and the drain electrode 629 are formed under the upper surface 621a and connected to the upper surface 621a, and the source electrode 628 and the drain electrode 629 are respectively located in the body region 625 under the outside of the gate 627 in a channel direction (as indicated by a dotted arrow in the figure, the same applies below) and in the well region 622 away from the body region 625 side, and in the channel direction, the drift region 622a is located between the drain electrode 629 and the body region 625, in the well region 622 near the upper surface 621a for serving as a drift current channel of the LDMOS device LT in the on operation.

In a preferred embodiment, the gate 627 includes a dielectric layer 6271 connected to the upper surface, a conductive layer 6272 having conductivity, and a spacer 6273 having electrical insulating properties. Dielectric layer 6271 is formed on body region 625 and well region 622, and is connected to body region 625 and well region 622. The conductive layer 6272 is used as an electrical contact for the gate 627, and is formed over all of the dielectric layers 6271 and connected to the dielectric layers 6271. Spacer layers 6273 are formed on both sides of the conductive layer 6272 to serve as electrical insulation layers on both sides of the gate 627.

With continued reference to fig. 6B, schottky barrier diode SD4 includes schottky metal layer 631 and schottky semiconductor layer 632. The schottky metal layer 631 is formed on the semiconductor layer 621', and in a vertical direction, the schottky metal layer 631 is located on the upper surface 621a and connected to the upper surface 621a; the schottky metal layer 631 and the source electrode 628 are electrically connected via a metal wire ML 3. The schottky semiconductor layer 632 is formed in the semiconductor layer 621', the schottky semiconductor layer 632 forms a schottky contact with the schottky metal layer 631, and the schottky semiconductor layer 632 is adjacent to the well region 622, and in a vertical direction, the schottky semiconductor layer 632 is under the upper surface 621a and connected to the upper surface 621a. In the present embodiment, the schottky semiconductor layer 632 and the well region 622 are formed by the same process step, and are adjacent to each other in the channel direction and the vertical direction as shown in the drawing.

The schottky barrier diode SD further includes, for example, two insulating structures 633, each of which is located outside of both sides of the schottky metal layer 631, connected to the schottky semiconductor layer 632, and separated by a schottky channel 634. The schottky channel 634 is a path that provides a reverse current to flow through the schottky barrier diode SD4 when the schottky barrier diode SD is turned on. The insulating structure 633 may be, for example and without limitation, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure. The insulating structure 633 may be formed simultaneously with the drift oxide region 624 using the same process steps.

In this embodiment, in all LDMOS devices LT9, all well regions 622 are electrically connected to each other, all body regions 625 are electrically connected to each other, all body poles 626 are electrically connected to each other, all gates 627 are electrically connected to each other, all sources 628 are electrically connected to each other, and all drains 629 are electrically connected to each other. In a preferred embodiment, in the LDMOS device LT9, the source electrode 628 is electrically connected to the body electrode 626 by a silicide layer 623 as shown.

Referring to fig. 7, a sixth embodiment of the present invention is shown. Fig. 7 shows a schematic cross-sectional view of a schottky barrier diode SD 5. As shown in fig. 7, the schottky barrier diode SD5 includes: a schottky metal layer 731, a schottky semiconductor layer 732, two insulating structures 733, and two channel side well regions 734. Wherein a schottky metal layer 731 is formed on the semiconductor layer 721'. A schottky semiconductor layer 732 is formed in the semiconductor layer 721', the schottky semiconductor layer 732 forms a schottky contact with the schottky metal layer 731, and the schottky semiconductor layer 732 adjoins the first conductive type well region 722 of the LDMOS device. In the present embodiment, as shown in the drawing, the schottky semiconductor layer 732 and the first conductive type well region 722 of the LDMOS device are formed by the same process step and are adjacent to each other in the channel direction.

Two insulating structures 733, which are respectively located outside the two sides of the schottky metal layer 731, are connected to the schottky semiconductor layer 732 and are separated by a schottky channel 735. The schottky channel 735 is a path that provides a reverse current to flow through the schottky barrier diode SD5 when the schottky barrier diode SD5 is turned on. The insulating structure 733 may be, for example but not limited to, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure. The insulating structure 733 may be formed simultaneously with the same process steps as the drift oxide region of the LDMOS device. The two channel-side well regions 734 have the second conductivity type and are separated by the schottky channel 735 in the semiconductor layer 721' below both sides of the schottky metal layer 731, and the channel-side well regions 734 are formed, for example, by the same process steps as the second conductivity type well regions of other devices on the substrate 721.

Referring to fig. 8, a seventh embodiment of the present invention is shown. Fig. 8 shows a schematic cross-sectional view of a schottky barrier diode SD 6. As shown in fig. 8, the schottky barrier diode SD6 includes: a schottky metal layer 831, a schottky semiconductor layer 832, two insulating structures 833, two polysilicon layers 835, and two channel side body regions 834. Wherein a schottky metal layer 831 is formed on the semiconductor layer 821'. A schottky semiconductor layer 832 is formed in the semiconductor layer 821', the schottky semiconductor layer 832 forms a schottky contact with the schottky metal layer 831, and the schottky semiconductor layer 832 is adjacent to the first conductive type well region 822 of the LDMOS device. In the present embodiment, as shown in the drawing, the schottky semiconductor layer 832 and the first conductive type well region 822 of the LDMOS device are formed by the same process step and are adjacent to each other in the channel direction.

Two insulating structures 833, each located under the outer portions of the schottky metal layer 831, are connected to the schottky semiconductor layer 832 and separated by the schottky channel 836. The schottky channel 836 is a path that provides a reverse current flowing through the schottky barrier diode SD6 when the schottky barrier diode SD6 is turned on. The insulating structure 833 may be, for example but not limited to, a shallow trench isolation (shallow trench isolation, STI) structure as shown, or a region oxide (local oxidation of silicon, LOCOS) structure. The insulating structure 833 may be formed simultaneously with the same process steps as the drift oxide region of the LDMOS device.

The two channel-side body regions 834 have a second conductivity type and are separated by schottky channels 836 in the semiconductor layer 821' below the sides of the schottky metal layer, respectively, and the two channel-side body regions 834 are formed, for example, by the same process steps as the second conductivity type body regions of other devices on the substrate 821. Two polysilicon layers 835 are respectively located on the two channel-side body regions 834, and the polysilicon layers 835 are separated from the corresponding channel-side body regions 834 by corresponding insulating structures 833. The two polysilicon layers 835 are formed, for example, by the same process steps as the conductive layers of the gates of the other elements on the substrate 821.

Referring to fig. 9, an eighth embodiment of the present invention is shown. Fig. 9 shows a schematic cross-sectional view of a schottky barrier diode SD 7. As shown in fig. 9, the schottky barrier diode SD7 includes: a schottky metal layer 931, a schottky semiconductor layer 932, two channel side body regions 934, two gates 935, and two channel side body electrodes 936. In which a schottky metal layer 931 is formed on a semiconductor layer 921'. A schottky semiconductor layer 932 is formed in the semiconductor layer 921', the schottky semiconductor layer 932 forms a schottky contact with the schottky metal layer 931, and the schottky semiconductor layer 932 adjoins the first conductive type well region 922 of the LDMOS element. In the present embodiment, as shown in the drawing, the schottky semiconductor layer 932 and the first conductive type well region 922 of the LDMOS device are formed by the same process step and are adjacent to each other in the channel direction.

The two channel-side body regions 934, having the second conductivity type, are respectively located under both sides of the schottky metal layer 931, are formed in the semiconductor layer 921', and are separated by the schottky channel 937. The schottky channel 937 is a path that provides a reverse current flowing through the schottky barrier diode SD6 when the schottky barrier diode SD6 is turned on. The channel-side body region 934 is formed, for example, by the same process steps as the second conductivity-type body regions of the other elements on the substrate 921. The two-channel side body poles 936 have the second conductivity type and are respectively located in the two-channel side body regions 934, separated by the schottky channel 937. The channel-side body pole 936 is formed, for example, by the same process steps as the second conductivity type body poles of the other elements on the substrate 921.

Two gates 935 are respectively located on the two channel-side body regions 934, and the gates 935 include a dielectric layer 9351 connected to the upper surface, a conductive layer 9352 having conductivity, and a spacer layer 9353 having electrical insulation properties. The conductive layer 9352 is separated from the corresponding channel-side body region 934 by a corresponding dielectric layer 9351 or spacer layer 9353. The two gates 935 are formed, for example, by the same process steps as the gates of the other elements on the substrate 921.

Referring to fig. 10A-10G, and concurrently referring to fig. 2, fig. 10A-10G illustrate a ninth embodiment of the present invention. Fig. 10A to 10G show schematic cross-sectional views of a method of manufacturing the high-voltage element 22. As shown in fig. 10A, a semiconductor layer 221 'is first formed on a substrate 221, and the semiconductor layer 221' has an upper surface 221a and a lower surface 221b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 10A, the same applies below). At this time, the drift oxide region 224 and the insulating structure 233 are not formed yet, and the upper surface 221a is not completely defined yet. After the high voltage element 22 is formed, the upper surface 221a is illustrated as a thick broken line. The substrate 221 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 221 'is formed on the substrate 221, for example, by an epitaxial process, or is formed as a portion of the substrate 221 as the semiconductor layer 221'. The manner of forming the semiconductor layer 221' is well known to those skilled in the art, and will not be described herein.

With continued reference to fig. 10A, a well region 222 is formed by doping a first impurity into the semiconductor layer 221', for example, but not limited to, using a plurality of ion implantation process steps. The well region 222 is formed in the semiconductor layer 221', and in a vertical direction, the well region 222 is located under the upper surface 221a and connected to the upper surface 221a. The well region 222 is formed by, for example, a plurality of ion implantation process steps.

Next, referring to fig. 10B, a drift oxide region 224 and two insulating structures 233 are formed on the upper surface 221a and connected to the upper surface 221a. The drift oxide region 224 may be, for example but not limited to, a region oxide (local oxidation of silicon, LOCOS) structure as shown, or a shallow trench isolation (shallow trench isolation, STI) structure. The insulating structure 233 is not limited to the shallow trench isolation (shallow trench isolation, STI) structure as shown, but may be a region oxide (local oxidation of silicon, LOCOS) structure. A drift oxide region 224 is formed on the upper surface 221a and is connected to the upper surface 221a, and is located directly above a portion of the drift region 222a (as shown by the dashed box in the LDMOS device LT in fig. 2), and is connected to the drift region 222a. Two insulating structures 233, which are respectively located outside the two sides of the schottky metal layer 231, are connected to the schottky semiconductor layer 232 and are separated by the schottky channel 234. The schottky channel 234 is a path that provides a reverse current flowing through the schottky barrier diode SD when the schottky barrier diode SD is turned on.

Next, referring to fig. 10C, a dielectric layer 2271 and a conductive layer 2272 of the gate 227 are formed on the upper surface 221a of the semiconductor layer 221', and a portion of the body region 226 is located directly below the dielectric layer 2271 and the conductive layer 2272 of the gate 227 and connected to the dielectric layer 2271 of the gate 227 in a vertical direction (as indicated by a solid arrow in fig. 10C, and the same applies below) to provide an inversion region 223a of the LDMOS device LT in the on operation.

Next, referring to fig. 10D, a body region 225 is formed in the well region 222, and the body region 225 is located under the upper surface 221a and connected to the upper surface 221a in the vertical direction. The body region 225 has a second conductivity type, and the body region 225 is formed by, for example and without limitation, forming a photoresist layer 2251 as a mask by a photolithography process step, doping a second conductivity type impurity into the well region 222 to form the body region 225. For example, the body region 225 may be formed by implanting impurities of the second conductivity type into the well region 222 in the form of accelerated ions, such as, but not limited to, ion implantation process steps IMP11 and IMP12 having an inclined angle.

With continued reference to fig. 10D, for example, after forming the dielectric layer 2271 and the conductive layer 2272 of the gate 227, a lightly doped region 2281 is formed to avoid that the body region 225 under the spacer layer 2273 cannot form a reverse current channel when the LDMOS device LT is turned on. A method of forming the lightly doped region 2281, for example, doping the first conductive type impurity into the body region 225 to form the lightly doped region 2281. In this embodiment, the first conductive type impurity may be implanted into the body region 225 to form the lightly doped region 2281 by, for example, but not limited to, an ion implantation process step IMP2 in the form of accelerated ions. Note that the first conductivity type impurity concentration of the lightly doped region 2281 is lower than the first conductivity type impurity concentrations of the source electrode 228 and the drain electrode 229, and therefore, a portion where the lightly doped region 2281 overlaps with the source electrode 228 and the drain electrode 229 is relatively negligible.

Next, referring to fig. 10E, a spacer layer 2273 is formed outside the side of the conductive layer 2272 to form a gate 227. Next, the source electrode 28 and the drain electrode 229 are formed under the upper surface 221a and connected to the upper surface 221a, and the source electrode 228 and the drain electrode 229 are respectively located in the body region 226 under the outer portion of the gate electrode 227 in the channel direction and in the well region 222 away from the body region 226 side, and the drift region 222a is located between the drain electrode 229 and the body region 225 in the channel direction, in the well region 222 close to the upper surface 221a, for serving as a drift current channel of the LDMOS device LT in the on operation, and the source electrode 228 and the drain electrode 229 are located under the upper surface 221a and connected to the upper surface 221a in the vertical direction. The source 228 and drain 229 have a first conductivity type, and the steps of forming the source 228 and drain 229, such as but not limited to forming the photoresist layer 2281 by a photolithography process step, are performed as a mask, and the first conductivity type impurities are implanted into the body region 225 and the well region 222, respectively, in the form of accelerated ions, such as but not limited to ion implantation process step IMP3, to form the source 228 and drain 229.

Next, referring to fig. 10F, as shown in fig. 10F, a body electrode 226 is formed in the body region 225. The body electrode 226 has a second conductivity type for use as an electrical contact to the body region 226. In a vertical direction, the body electrode 226 is formed under the upper surface 221a and connected to the body region 225 of the upper surface 221a. The step of forming the body electrode 226, such as, but not limited to, doping the body region 225 with a second conductivity type impurity using the photoresist layer 2261 formed by a photolithography process step as a mask, forms the body electrode 226. In this embodiment, the second conductive type impurity may be implanted into the body region 225 to form the body electrode 226 by using, for example, but not limited to, an ion implantation process step IMP4 in the form of accelerated ions.

Next, referring to fig. 10G, as shown in fig. 10G, a schottky barrier diode SD is formed, including a schottky metal layer 231 and a schottky semiconductor layer 232. The schottky metal layer 231 is formed on the semiconductor layer 221', and in a vertical direction, the schottky metal layer 231 is located on the upper surface 221a and connected to the upper surface 221a; the schottky metal layer 231 and the source electrode 228 are electrically connected via a metal wire ML. The schottky semiconductor layer 232 is formed in the semiconductor layer 221', the schottky semiconductor layer 232 and the schottky metal layer 231 form schottky contact, and the schottky semiconductor layer 232 is adjacent to the well region 222, and in a vertical direction, the schottky semiconductor layer 232 is located under the upper surface 221a and connected to the upper surface 221a. In the present embodiment, the schottky semiconductor layer 232 and the well region 222 are formed by the same process step, and are adjacent to each other in the channel direction and the vertical direction as shown in the drawing.

The two insulating structures 233 of the schottky barrier diode SD are respectively located outside the two sides of the schottky metal layer 231, connected to the schottky semiconductor layer 232, and separated by the schottky channel 234. The schottky channel 234 is a path that provides a reverse current flowing through the schottky barrier diode SD when the schottky barrier diode SD is turned on. The insulating structure 233, such as, but not limited to, a shallow trench isolation (shallow trench isolation, STI) structure as shown, may also be a region oxide (local oxidation of silicon, LOCOS) structure. The insulating structure 233 may be formed simultaneously with the drift oxide region 224 using the same process steps.

The high voltage element 22 is formed by a basic unit M1 centered on the AA' axis, after mirror (layout) wherein the basic unit M1 comprises: at least a part of the schottky barrier diode SD; and at least partially laterally diffusing the metal oxide semiconductor element LT. In this embodiment, the basic unit M1 is formed in a mirror image layout manner in each step, and the basic unit M1' is formed by comparison. As shown in the figure, the schottky barrier diode SD is divided into a left half and a right half in the lateral direction, and the right half of the schottky barrier diode SD is used as a part of the basic cell M1, and the left half of the schottky barrier diode SD is formed after mirror layout. In the present embodiment, as shown in the figure, the basic cell M1 includes a complete drift oxide region 224, a gate 227, a source 228, and a drain 229, and a portion of the well region 222, the body region 225, and the body electrode 226; the left half of the body region 225 and the left half of the body electrode 226 are used as a part of the basic unit M1, and the right half of the body region 225 and the right half of the body electrode 226 are formed after mirror layout. The basic unit M1 is subjected to mirror layout to form a basic unit M1', and the mirror layout can be repeated to form the high voltage device 22. The basic unit M1' includes: at least a part of the schottky barrier diode SD'; and at least partially laterally diffusing the metal oxide semiconductor element LT'. It should be noted that, the basic unit M1' is an LDMOS element LT ' formed by a mirror image layout of the basic unit M1 on the right side of the AA ' as the axis; of course, according to the present invention, the basic unit M1 may be arranged in a left mirror image, so as to form other LDMOS devices and schottky barrier diodes.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of easily understanding the present invention by those skilled in the art, and is not intended to limit the scope of the claims of the present invention. Various equivalent changes may be made by those skilled in the art within the same spirit of the invention. For example, other process steps or structures, such as deep well regions, etc., may be added without affecting the main characteristics of the device; as another example, the lithography technique is not limited to a photomask technique, but may also include an electron beam lithography technique. All of which may be analogized in accordance with the teachings of the present invention. Furthermore, the various embodiments described are not limited to single use, but may be used in combination, for example, but not limited to, combining the two embodiments. For example, the schottky barrier diodes SD5, SD6 and SD7 shown in fig. 7, 8 and 9 can be applied to the first to fifth and ninth embodiments. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations. Furthermore, it is not necessary for any embodiment of the present invention to achieve all of the objects or advantages and, therefore, the scope of the claims should not be limited by any of the claims.

Claims

1. A high voltage device for use in a power stage of a switching power supply circuit as a lower bridge switch, comprising:

at least one laterally diffused metal oxide semiconductor element comprising:

a well region having a first conductivity type formed in a semiconductor layer;

a body region of a second conductivity type formed in the well region;

the grid electrode is formed above the well region and connected with the well region; and

a source and a drain having the first conductivity type, the source being located in the body region under one side of the exterior of the gate, the drain being located in the well region under the other side of the exterior of the gate; and

at least one schottky barrier diode comprising:

a Schottky metal layer formed on the semiconductor layer, the Schottky metal layer being electrically connected with the source electrode; and

a Schottky semiconductor layer formed in the semiconductor layer, the Schottky semiconductor layer forming a Schottky contact with the Schottky metal layer, and the Schottky semiconductor layer being adjacent to the well region;

wherein, a part of the body region right below the grid between the source electrode and a boundary of the body region defines an inversion region which is used as an inversion current channel of the lateral diffusion metal oxide semiconductor element in a conducting operation;

Wherein, a part of the well region between the body region and the drain defines a drift region for being used as a drift current channel of the lateral diffusion metal oxide semiconductor element in the on operation;

the Schottky barrier diode further comprises two insulating structures which are respectively positioned outside two sides of the Schottky metal layer, connected to the Schottky semiconductor layer and separated by a Schottky channel;

the schottky barrier diode further comprises two channel side body regions of the second conductivity type respectively located in the schottky semiconductor layer below two sides of the schottky metal layer and separated by the schottky channel, wherein the channel side body regions and the body regions are formed by the same process steps.

2. The high voltage device of claim 1, wherein the high voltage device is formed by a base unit having a mirrored layout, wherein the base unit comprises:

at least a portion of the schottky barrier diode; and

at least part of the lateral diffusion metal oxide semiconductor elements are alternately arranged in a mirror image manner in a channel direction and are connected in series to form a power element string when a plurality of the lateral diffusion metal oxide semiconductor elements are arranged;

Wherein the schottky barrier diode is adjacent to the power element string in the channel direction.

3. The high voltage device of claim 1, wherein the high voltage device is formed by a base unit having a mirrored layout, wherein the base unit comprises:

at least one of the schottky barrier diodes; and

at least part of the lateral diffusion metal oxide semiconductor elements are alternately arranged in series in a channel direction when a plurality of the lateral diffusion metal oxide semiconductor elements are arranged;

the number of the Schottky barrier diodes is not greater than the number of the lateral diffusion metal oxide semiconductor elements, each Schottky barrier diode is located between the body region and the drain electrode in the corresponding lateral diffusion metal oxide semiconductor element, and the Schottky semiconductor layer is connected with the drift region.

4. The device of claim 1, wherein the at least one schottky barrier diode is located in an isolation region of the device and the isolation region is located outside the at least one ldmos.

5. The high voltage device of claim 1, wherein said schottky barrier diode further comprises two channel side body regions of said second conductivity type, respectively located in said two channel side body regions, separated by said schottky channel.

6. The device of claim 1, wherein the schottky barrier diode further comprises two polysilicon layers on the two channel-side body regions, respectively, and the polysilicon layers and the corresponding channel-side body regions are separated by the corresponding insulating structures.

7. The device of claim 1, wherein the ldmos further comprises a drift oxide region formed on the drift region, the drift oxide region comprising a region oxide structure, a shallow trench isolation structure, or a chemical vapor deposition oxide region.

8. The high voltage device of claim 1, wherein the gate comprises:

a dielectric layer formed on the body region and the well region and connected to the body region and the well region;

a conductive layer used as the electric contact of the grid electrode, forming all the dielectric layers and connecting to the dielectric layers; and

and a spacer layer formed on both sides of the conductive layer to serve as an electrical insulation layer on both sides of the gate.

9. A method of manufacturing a high voltage device for use in a power stage of a switching power supply circuit as a lower bridge switch, the method comprising:

Forming at least one laterally diffused metal oxide semiconductor element, the step of forming the laterally diffused metal oxide semiconductor element comprising:

forming a well region in a semiconductor layer, the well region having a first conductivity type;

forming a body region in the well region, the body region having a second conductivity type;

forming a grid above the well region and connected to the well region; and

forming a source electrode in the body region below an outer side of the gate electrode;

forming a drain electrode in the well region below the other side of the outside of the gate electrode, wherein the source electrode and the drain electrode have the first conductivity type; and

forming at least one schottky barrier diode element, the step of forming the schottky barrier diode comprising:

forming a schottky metal layer on the semiconductor layer, the schottky metal layer being electrically connected to the source electrode; and

forming a schottky semiconductor layer in the semiconductor layer, wherein the schottky semiconductor layer and the schottky metal layer form schottky contact, and the schottky semiconductor layer is adjacent to the well region;

wherein the step of forming the schottky barrier diode further comprises: forming two insulation structures respectively positioned outside two sides of the Schottky metal layer, connected to the Schottky semiconductor layer and separated by a Schottky channel;

wherein the step of forming the schottky barrier diode further comprises: two channel side body regions are formed having the second conductivity type and respectively located in the Schottky semiconductor layer below two sides of the Schottky metal layer and separated by the Schottky channel, wherein the channel side body regions and the body regions are formed by the same process steps.

10. The method of claim 9, wherein the high voltage device is formed by a basic unit after mirror image layout, wherein the basic unit comprises:

at least a portion of the schottky barrier diode; and

11. The method of claim 9, wherein the high voltage device is formed by a basic unit after mirror image layout, wherein the basic unit comprises:

at least one of the schottky barrier diodes; and

12. The method of claim 9, wherein the at least one schottky barrier diode is located in an isolation region of the high voltage device, and the isolation region is located outside the at least one ldmos.

13. The method of manufacturing a high voltage device according to claim 9, wherein the step of forming the schottky barrier diode further comprises: two channel-side body poles of the second conductivity type are formed in the two channel-side body regions, respectively, separated by the schottky channel.

14. The method of manufacturing a high voltage device according to claim 9, wherein the step of forming the schottky barrier diode further comprises: two polysilicon layers are formed on the two channel side body regions respectively, and the polysilicon layers and the corresponding channel side body regions are separated by the corresponding insulating structures.

15. The method of claim 9, further comprising forming a drift oxide region on the drift region, the drift oxide region comprising a region oxide structure, a shallow trench isolation structure, or a chemical vapor deposition oxide region.

16. The method of manufacturing a high voltage device according to claim 9, wherein the step of forming the gate electrode comprises:

forming a dielectric layer on the body region and the well region and connected to the body region and the well region;

forming a conductive layer on all the dielectric layers and connected to the dielectric layers to serve as an electrical contact of the grid electrode; and

A spacer layer is formed on both sides of the conductive layer to serve as an electrical insulation layer on both sides of the gate.