KR100961549B1 - Semiconductor device with high voltage transistor and logic transistor - Google Patents

Semiconductor device with high voltage transistor and logic transistor Download PDF

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KR100961549B1
KR100961549B1 KR1020030052414A KR20030052414A KR100961549B1 KR 100961549 B1 KR100961549 B1 KR 100961549B1 KR 1020030052414 A KR1020030052414 A KR 1020030052414A KR 20030052414 A KR20030052414 A KR 20030052414A KR 100961549 B1 KR100961549 B1 KR 100961549B1
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well
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권병기
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

본 발명은 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자에 관한 것으로, 특히 본 발명의 고전압 트랜지스터는 반도체 기판에서 제 1영역에 P-웰과, P-웰내에서 서로 소정 간격 이격되는 N-드리프트 영역과, N-드리프트 영역내에 있는 N+소오스/드레인 영역과, N-드리프트 영역 사이의 P-웰 상부면에 게이트 절연막을 개재하여 적층된 게이트 전극을 포함한다. 그리고 본 발명의 로직 트랜지스터는 반도체 기판에서 제 2영역에 N웰과 N웰내에 형성된 P-웰과, P-웰내에 있는 N+소오스/드레인 영역과, N+소오스/드레인 영역 사이의 P-웰 상부면에 게이트 절연막을 개재하여 적층된 게이트 전극을 포함한다. 따라서 본 발명은 로직 트랜지스터의 P-웰 하부와 기판 사이에 반대 도전형 불순물이 주입된 N웰을 추가함으로써 P-웰에 백 바이어스 전원이 인가되더라도 하부의 N웰에서 P-웰의 브레이크 다운 현상을 보상함으로써 로직 트랜지스터의 전기적 특성을 향상시킬 수 있다.The present invention relates to a semiconductor device having a high voltage transistor and a logic transistor. In particular, the high voltage transistor of the present invention includes a P-well in a first region of the semiconductor substrate, an N-drift region spaced a predetermined distance from each other in the P-well, An N + source / drain region in the N-drift region and a gate electrode stacked on the upper surface of the P-well between the N-drift region with a gate insulating film interposed therebetween. The logic transistor of the present invention is a P-well formed in an N well and an N well in a second region of a semiconductor substrate, an N + source / drain region in the P-well, and a P-well upper surface between the N + source / drain region. The gate electrode is stacked on the substrate via a gate insulating film. Therefore, the present invention adds an N well in which opposite conductivity type impurities are injected between the P-well lower portion of the logic transistor and the substrate to prevent breakdown of the P-well in the lower N well even when the back bias power is applied to the P-well. By compensating, the electrical characteristics of the logic transistor can be improved.

로직 트랜지스터, P-웰, N웰, 백 바이어스, 브레이크 다운Logic Transistors, P-well, Nwell, Back Bias, Breakdown

Description

고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자{SEMICONDUCTOR DEVICE WITH HIGH VOLTAGE TRANSISTOR AND LOGIC TRANSISTOR} Semiconductor device having a high voltage transistor and a logic transistor {SEMICONDUCTOR DEVICE WITH HIGH VOLTAGE TRANSISTOR AND LOGIC TRANSISTOR}             

도 1은 종래 기술에 의한 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자의 수직 단면도,1 is a vertical cross-sectional view of a semiconductor device having a high voltage transistor and a logic transistor according to the prior art,

도 2는 본 발명에 따른 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자의 수직 단면도.2 is a vertical sectional view of a semiconductor device having a high voltage transistor and a logic transistor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 고전압 트랜지스터 영역 2 : 로직 트랜지스터 영역1: high voltage transistor region 2: logic transistor region

100 : P- 기판 102 : 제 1웰(P-웰)100: P-substrate 102: the first well (P-well)

104 : 제 2웰(N웰) 106 : 제 3웰(P-웰)104: second well (N well) 106: third well (P-well)

107 : 제 4웰(N-웰) 108 : 드리프트 영역107: fourth well (N-well) 108: drift region

109 : 소자 분리막 110, 114 : 게이트 절연막109: device isolation film 110, 114: gate insulating film

112, 116 : 게이트전극 118 : 스페이서112, 116: gate electrode 118: spacer

120, 122 : N+ 소오스/드레인 영역120, 122: N + source / drain regions

124 : P+ 소오스/드레인 영역
124: P + source / drain regions

본 발명은 반도체 소자에 관한 것으로서, 특히 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자에 관한 것이다. The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high voltage transistor and a logic transistor.

일반적으로 고전압 트랜지스터는 로직 회로 제조 공정에 엠비디드(embedded)로 셋업되면서 동시에 로직 회로와 동일한 수행 능력을 갖도록 셋업된다. 고전압 트랜지스터는 주로 다른 반도체 소자에 비해 우수한 스위칭 속도를 가지고 있기 때문에 LCD 소자의 구동 회로로 사용되고 있다.In general, high voltage transistors are set up embedded in the logic circuit manufacturing process and at the same time have the same performance capabilities as the logic circuit. High voltage transistors are mainly used as driving circuits for LCD devices because they have superior switching speeds compared to other semiconductor devices.

도 1은 종래 기술에 의한 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자의 수직 단면도이다. 도 1을 참조하면, 종래 고전압 트랜지스터 및 로직 트랜지스터의 반도체 소자 구조는 다음과 같이 반도체 기판으로서 P- 기판(10)의 제 1영역(1)에 고전압 트랜지스터가 형성되어 있으며 제 2영역(2)에 로직 트랜지스터가 형성되어 있다.1 is a vertical cross-sectional view of a semiconductor device having a high voltage transistor and a logic transistor according to the prior art. Referring to FIG. 1, a semiconductor device structure of a conventional high voltage transistor and a logic transistor is a semiconductor substrate, in which a high voltage transistor is formed in a first region 1 of a P-substrate 10 and a second region 2 is formed as follows. Logic transistors are formed.

즉, P-기판(10)의 제 1 영역(1)에는 제 1도전형 불순물, P형 불순물 이온이 저농도로 주입된 P-웰(well)(12)이 형성되어 있으며 P-웰(12)내에 제 2도전형 불순물, N형 불순물 이온이 저농도로 주입되며 서로 일정 간격(채널 길이)으로 분리되도록 고전압 트랜지스터의 N-드리프트 영역(drift region)(16)이 형성되어 있다. N-드리프트 영역(16) 표면에 소자의 활성 영역과 비활성 영역을 구분하기 위한 소자 분리막(18)이 형성되어 있다. 그리고 N-드리프트 영역(16)내에 제 2도전형 불 순물, N형 불순물 이온이 고농도로 주입된 고전압 트랜지스터의 N+소오스/드레인 영역(30)이 형성되어 있으며 고전압 트랜지스터는 애벌런치 브레이크다운 현상을 향상시키기 위하여 N+소오스/드레인 영역(30) 아래에 N-드리프트 영역(16)이 있는 DDD(Double Diffused Drain) 구조를 채택하고 있다. N-드리프트 영역(16) 사이의 P-웰(12) 상부에 게이트 절연막(20)을 개재하여 고전압 트랜지스터의 게이트 전극(22)이 형성되어 있으며 게이트 전극(22)의 일부분이 N-드리프트 영역(16)과 일정 부분이 오버랩되어 있다.That is, a P-well 12 having a low concentration of first conductive impurities and P-type impurity ions is formed in the first region 1 of the P-substrate 10. The N-drift region 16 of the high voltage transistor is formed so that the second conductive impurity and N-type impurity ions are implanted at low concentration and separated from each other at a predetermined interval (channel length). The device isolation layer 18 is formed on the surface of the N-drift region 16 to distinguish between an active region and an inactive region of the device. The N + source / drain region 30 of the high voltage transistor in which the second conductive impurity and the N type impurity ions are implanted at a high concentration is formed in the N-drift region 16, and the high voltage transistor improves the avalanche breakdown phenomenon. In order to achieve this, a double diffused drain (DDD) structure having an N-drift region 16 under the N + source / drain region 30 is adopted. The gate electrode 22 of the high voltage transistor is formed on the P-well 12 between the N-drift regions 16 through the gate insulating film 20, and a portion of the gate electrode 22 is formed in the N-drift region ( 16) and a portion overlap.

또한 P-기판(10)의 제 2 영역(2)에는 제 1도전형 불순물, P형 불순물 이온이 저농도로 주입된 로직 트랜지스터의 P-웰(14)이 형성되어 있다. P-웰(14) 표면에 소자의 활성 영역과 비활성 영역을 구분하기 위한 소자 분리막(18)이 형성되어 있다. 그리고 P-웰(14)내에 제 2도전형 불순물, N형 불순물 이온이 고농도로 주입된 로직 트랜지스터의 N+소오스/드레인 영역(32)이 형성되어 있다. P-웰(14) 상부에 게이트 절연막(24)을 개재하여 로직 트랜지스터의 게이트 전극(26)이 형성되어 있으며 이들 측벽에는 절연 물질로 된 스페이서(spacer)(28)가 형성되어 있다. 이때 N+소오스/드레인 영역(32)은 게이트 전극(26) 에지 부근의 웰(14)내에 N형 불순물이 저농도로 주입된 LDD(Lightly Doped Drain) 구조로 형성할 수도 있다.In the second region 2 of the P-substrate 10, the P-well 14 of the logic transistor in which the first conductive impurity and P-type impurity ions are implanted at low concentration is formed. A device isolation layer 18 is formed on the surface of the P-well 14 to distinguish between active and inactive regions of the device. In the P-well 14, an N + source / drain region 32 of the logic transistor in which the second conductive impurity and N-type impurity ions are implanted at a high concentration is formed. The gate electrode 26 of the logic transistor is formed on the P-well 14 via the gate insulating film 24, and spacers 28 made of an insulating material are formed on these sidewalls. In this case, the N + source / drain region 32 may be formed as a lightly doped drain (LDD) structure in which N-type impurities are injected at low concentration into the well 14 near the edge of the gate electrode 26.

이러한 고전압 및 로직 트랜지스터는 N채널 트랜지스터대신에 상기 구조와 동일하며 제 1 및 제 2도전형 불순물 이온만 바꾸어 P-기판(10)에 N-웰, 고전압 트랜지스터의 경우에는 P-드리프트 영역, P+소오스/드레인 영역을 갖는 P채널 트랜지스터로 변환이 가능하다. The high voltage and logic transistors have the same structure as the above structure instead of the N-channel transistors, and only the first and second conductive impurity ions are replaced with N-wells on the P-substrate 10, and P-drift regions and P + sources in the case of high-voltage transistors. Conversion to a P-channel transistor having a / drain region is possible.                         

그런데, 일반적으로 N채널 트랜지스터가 형성되는 P-웰에 백 바이어스(Back bias) 전원을 인가할 경우 특히 로직 트랜지스터의 P-웰에 브레이크다운(break down) 현상이 발생하게 된다.
However, in general, when a back bias power is applied to a P-well in which an N-channel transistor is formed, breakdown occurs particularly in the P-well of a logic transistor.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 로직 트랜지스터의 P-웰 하부와 기판 사이에 반대 도전형 불순물이 주입된 N웰을 추가함으로써 P-웰에 백 바이어스 전원이 인가되더라도 하부의 N웰에서 P-웰의 브레이크 다운 현상을 보상함으로써 로직 트랜지스터의 전기적 특성을 향상시킬 수 있는 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자를 제공하는데 있다.
An object of the present invention is to solve the above-mentioned problems of the prior art by adding an N well in which opposite conductivity-type impurities are injected between the P-well bottom of the logic transistor and the substrate, even if the back bias power is applied to the P-well. To provide a semiconductor device having a high voltage transistor and a logic transistor that can improve the electrical characteristics of the logic transistor by compensating the breakdown of the P-well in the N-well of.

상기 목적을 달성하기 위하여 본 발명의 반도체 소자는 반도체 기판에서 제 1영역에 제 1도전형 불순물이 주입된 제 1웰과, 제 1웰내에서 서로 소정 간격 이격되도록 제 2도전형 불순물이 주입된 제 1드리프트 영역과, 제 1드리프트 영역내에 제 2도전형 불순물이 주입된 소오스/드레인 영역과, 제 1드리프트 영역 사이의 제 1웰 상부면에 게이트 절연막을 개재하여 적층된 게이트 전극을 갖는 고전압 트랜지스터와, 반도체 기판에서 제 2영역에 제 2도전형 불순물이 주입된 제 2웰과 제 2웰내에 제 1도전형 불순물이 주입된 제 3웰과, 제 3웰내에 서로 소정 간격 이격되도록 제 2도전형 불순물이 주입된 소오스/드레인 영역과, 소오스/드레인 영역 사이의 제 3웰 상부면에 게이트 절연막을 개재하여 적층된 게이트 전극을 갖는 로직 트랜지스터를 포함한다.
In order to achieve the above object, a semiconductor device of the present invention includes a first well in which a first conductive impurity is implanted into a first region of a semiconductor substrate, and a second conductive impurity implanted so as to be spaced apart from each other by a predetermined interval in the first well. A high voltage transistor having a drift region, a source / drain region in which a second conductive type impurity is implanted in the first drift region, and a gate electrode stacked on the upper surface of the first well between the first drift region with a gate insulating film interposed therebetween; And a second well in which the second conductive impurity is implanted into the second region of the semiconductor substrate, a third well in which the first conductive impurity is implanted in the second well, and a second conductive type so as to be spaced apart from each other in the third well by a predetermined interval. And a logic transistor having a source / drain region implanted with impurities and a gate electrode stacked on the upper surface of the third well between the source / drain region with a gate insulating layer interposed therebetween.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2는 본 발명에 따른 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자의 수직 단면도이다. 도 2를 참조하면, 본 발명에 따라 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자 구조는 다음과 같이 반도체 기판으로서 P- 기판(100)의 제 1영역(1)에 고전압 트랜지스터가 형성되어 있으며 P-기판(100)의 제 2영역(2)에 로직 트랜지스터가 형성되어 있다. 본 발명의 실시예에서는 로직 트랜지스터를 N채널 및 P채널 트랜지스터가 모두 있는 CMOS 트랜지스터 형태를 취한다.2 is a vertical cross-sectional view of a semiconductor device having a high voltage transistor and a logic transistor according to the present invention. Referring to FIG. 2, according to the present invention, a semiconductor device having a high voltage transistor and a logic transistor has a high voltage transistor formed in a first region 1 of a P-substrate 100 as a semiconductor substrate as follows. A logic transistor is formed in the second region 2 of (100). In the embodiment of the present invention, the logic transistor takes the form of a CMOS transistor having both N-channel and P-channel transistors.

P-기판(100)의 제 1 영역(1)에는 제 1도전형 불순물, P형 불순물 이온이 저농도로 주입된 제 1웰인 P-웰(102)이 형성되어 있으며 P-웰(102)내에 제 2도전형 불순물, N형 불순물 이온이 저농도로 주입되며 서로 일정 간격(채널 길이)으로 분리되도록 고전압 트랜지스터의 N-드리프트 영역(108)이 형성되어 있다. N-드리프트 영역(108) 표면에 소자의 활성 영역과 비활성 영역을 구분하기 위한 소자 분리막(109)이 형성되어 있다. 그리고 N-드리프트 영역(108)내에 제 2도전형 불순물, N형 불순물 이온이 고농도로 주입된 고전압 트랜지스터의 N+소오스/드레인 영역(120)이 형성되어 있으며 고전압 트랜지스터는 애벌런치 브레이크다운 현상을 향상시키기 위하여 N+소오스/드레인 영역(120) 아래에 N-드리프트 영역(108)이 있는 DDD 구조를 채택하고 있다. N-드리프트 영역(108) 사이의 P-웰(102) 상부에 게이트 절연막(110)을 개재하여 고전압 트랜지스터의 게이트 전극(112)이 형성되어 있으며 게이트 전극(112)의 일부분이 N-드리프트 영역(108)과 일정 부분이 오버랩되어 있다. 본 발명에 적용된 고전압 트랜지스터는 N채널 트랜지스터대신에 상기 구조와 동일하며 제 1 및 제 2도전형 불순물 이온만 바꾸어 P-기판(100)에 N-웰, N-드리프트 영역, P+소오스/드레인 영역을 갖는 P채널 트랜지스터로 변환, 추가가 가능하다.In the first region 1 of the P-substrate 100, a P-well 102, which is a first well implanted with a low concentration of first conductive impurities and P-type impurity ions, is formed and formed in the P-well 102. The N-drift region 108 of the high voltage transistor is formed so that two-conductive impurities and N-type impurity ions are implanted at low concentration and separated from each other at a predetermined interval (channel length). An isolation layer 109 is formed on the surface of the N-drift region 108 to distinguish between an active region and an inactive region of the device. In addition, the N + source / drain region 120 of the high voltage transistor in which the second conductive impurity and the N-type impurity ions are implanted at a high concentration is formed in the N-drift region 108, and the high voltage transistor improves the avalanche breakdown phenomenon. For this purpose, a DDD structure having an N-drift region 108 under the N + source / drain region 120 is adopted. A gate electrode 112 of the high voltage transistor is formed on the P-well 102 between the N-drift regions 108 through the gate insulating layer 110, and a portion of the gate electrode 112 is formed in the N-drift region ( 108) and a portion overlap. The high voltage transistor applied to the present invention has the same structure as the above structure instead of the N-channel transistor, and replaces the N-well, N-drift region and P + source / drain region on the P-substrate 100 by changing only the first and second conductive impurity ions. Conversion and addition to a P-channel transistor is possible.

그리고 본 발명에 따라 P-기판(100)의 로직 트랜지스터 영역인 제 2 영역(2)에는 N채널 트랜지스터가 형성되어 있는데, 그 구조는 다음과 같다. 즉, 제 2도전형 불순물로서, N형 불순물 이온이 주입된 제 2웰인 N웰(104)이 형성되어 있으며 N웰(104)내에 제 1도전형 불순물, P형 불순물 이온이 저농도로 주입된 제 3웰인 P-웰(106)이 형성되어 있다. P-웰(106) 표면에 소자의 활성 영역과 비활성 영역을 구분하기 위한 소자 분리막(109)이 형성되어 있다. 그리고 P-웰(106)내에 제 2도전형 불순물, N형 불순물 이온이 고농도로 주입된 로직 트랜지스터의 N+소오스/드레인 영역(122)이 형성되어 있다. P-웰(106) 상부에 게이트 절연막(114)을 개재하여 로직 트랜지스터의 게이트 전극(116)이 적층되어 있으며 이들 측벽에는 절연 물질로 된 스페이서(118)가 형성되어 있다. 이때 N+소오스/드레인 영역(122)은 게이트 전극(116) 에지 부근의 P-웰(106)내에 N형 불순물이 저농도로 주입된 LDD 구조로 형성할 수도 있다. According to the present invention, an N-channel transistor is formed in the second region 2, which is a logic transistor region of the P-substrate 100. The structure thereof is as follows. That is, as the second conductivity type impurity, an N well 104 which is a second well into which N type impurity ions are implanted is formed, and a first implanted impurity and a P type impurity ion are injected into the N well 104 at low concentration. A 3-well P-well 106 is formed. An isolation layer 109 is formed on the surface of the P-well 106 to distinguish between active and inactive regions of the device. In the P-well 106, an N + source / drain region 122 of the logic transistor in which the second conductive impurity and N-type impurity ions are implanted at a high concentration is formed. The gate electrode 116 of the logic transistor is stacked on the P-well 106 via the gate insulating layer 114, and spacers 118 made of an insulating material are formed on these sidewalls. In this case, the N + source / drain region 122 may be formed as an LDD structure in which N-type impurities are injected at low concentration into the P-well 106 near the edge of the gate electrode 116.                     

또한 P-기판(100)의 로직 트랜지스터 영역인 제 2영역(2)에는 P채널 트랜지스터가 형성된다. 제 2영역(2)의 P-기판(100)내 제 2웰인 N웰(104)이 P채널 트랜지스터 영역까지 연장되어 형성되어 있으며 N웰(104)내에 제 2도전형 불순물, N형 불순물 이온이 저농도로 주입된 제 4웰인 N-웰(107)이 형성되어 있다. N-웰(107) 표면에 소자 분리막(109)이 형성되어 있다. 그리고 N-웰(107)내에 제 1도전형 불순물, P형 불순물 이온이 고농도로 주입된 로직 트랜지스터의 P+소오스/드레인 영역(124)이 형성되어 있으며 P+소오스/드레인 영역(124)은 게이트 전극(116) 에지 부근의 N-웰(107)내에 P형 불순물이 저농도로 주입된 LDD 구조로 형성된다. N-웰(107) 상부에는 게이트 절연막(114) 및 게이트 전극(116)이 적층되어 있으며 이들 측벽에는 절연 물질로 된 스페이서(118)가 형성되어 있다.In addition, a P-channel transistor is formed in the second region 2, which is a logic transistor region of the P-substrate 100. The N well 104, which is the second well in the P-substrate 100 of the second region 2, extends to the P-channel transistor region, and the second conductive impurity and N-type impurity ions are formed in the N well 104. N-well 107, which is a fourth well injected at low concentration, is formed. The device isolation layer 109 is formed on the surface of the N-well 107. In addition, a P + source / drain region 124 of a logic transistor in which a first conductive impurity and a P-type impurity ion are implanted at a high concentration is formed in the N-well 107, and the P + source / drain region 124 is formed as a gate electrode ( 116) A P-type impurity is formed into the LDD structure in which N-well 107 near the edge is implanted at a low concentration. The gate insulating layer 114 and the gate electrode 116 are stacked on the N-well 107, and spacers 118 made of an insulating material are formed on these sidewalls.

이러한 구조를 갖는 본 발명의 반도체 소자에 있어서 로직 트랜지스터 영역(2)의 P-웰(106)과 기판(100) 사이에 N웰(104)을 추가함으로써 P-웰(106)에 백 바이어스 전원이 인가되더라도 하부의 N웰(104)에서 P-웰(106)의 브레이크 다운 현상을 보상하여 준다. 그리고 본 발명은 N채널 트랜지스터만 로직 트랜지스터로 구현할 경우 기판(100)과 P-웰(106) 사이에 N웰(104)을 형성하지만, N채널 및 P채널 트랜지스터로 로직을 구성할 경우에는 도 2와 같이 기판(100)과 P-웰/N-웰(106, 107) 사이에 N웰(104)을 형성하여 P-웰의 브레이크 다운을 방지한다.In the semiconductor device of the present invention having such a structure, a back bias power supply is applied to the P-well 106 by adding an N well 104 between the P-well 106 and the substrate 100 of the logic transistor region 2. Although applied, the breakdown phenomenon of the P-well 106 is compensated for in the lower N well 104. In the present invention, the N well 104 is formed between the substrate 100 and the P-well 106 when only the N-channel transistor is implemented as a logic transistor. However, when the logic is configured by the N-channel and P-channel transistors, FIG. As such, an N well 104 is formed between the substrate 100 and the P-well / N-wells 106 and 107 to prevent breakdown of the P-well.

한편, 본 발명은 로직 트랜지스터의 P-웰(106) 또는 N웰(107)에 문턱 전압 조절용 불순물 이온 주입을 실시하여 N채널 로직 트랜지스터와 P채널 로직 트랜지스터의 문턱 전압을 안정적으로 조정한다.
Meanwhile, the present invention stably adjusts threshold voltages of the N-channel logic transistor and the P-channel logic transistor by implanting impurity ions for threshold voltage into the P-well 106 or the N well 107 of the logic transistor.

이상 설명한 바와 같이, 본 발명은 로직 트랜지스터의 P-웰 하부와 기판 사이에 반대 도전형 불순물이 주입된 N웰을 추가함으로써 P-웰에 백 바이어스 전원이 인가되더라도 하부의 N웰에서 P-웰의 브레이크 다운 현상을 보상함으로써 로직 트랜지스터의 전기적 특성을 향상시킬 수 있다.As described above, the present invention adds an N well implanted with an opposite conductivity type impurity between the P-well bottom of the logic transistor and the substrate, so that the back-well power of the P-well in the lower N well is applied even though the back bias power is applied to the P-well. By compensating for the breakdown phenomenon, the electrical characteristics of the logic transistor can be improved.

게다가, 본 발명은 로직 트랜지스터의 P-웰에 문턱 전압 조절용 불순물 이온을 주입하여 트랜지스터의 문턱 전압을 안정적으로 조정함으로써 로직 트랜지스터의 전기적 특성을 향상시킬 수 있다.In addition, the present invention can improve the electrical characteristics of the logic transistor by stably adjusting the threshold voltage of the transistor by implanting the impurity ions for adjusting the threshold voltage into the P-well of the logic transistor.

한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (5)

반도체 기판에서 제 1영역에 제 1도전형 불순물이 주입된 제 1웰과, 상기 제 1웰내에서 서로 소정 간격 이격되도록 제 2도전형 불순물이 주입된 제 1드리프트 영역과, 상기 제 1드리프트 영역내에 제 2도전형 불순물이 주입된 소오스/드레인 영역과, 상기 제 1드리프트 영역 사이의 제 1웰 상부면에 게이트 절연막을 개재하여 적층된 게이트 전극을 갖는 고전압 트랜지스터와,A first well in which a first conductive impurity is implanted into a first region in a semiconductor substrate, a first drift region in which a second conductive impurity is implanted so as to be spaced apart from each other in the first well by a predetermined interval, and in the first drift region A high voltage transistor having a source / drain region into which a second conductive impurity is implanted, a gate electrode stacked on the upper surface of the first well between the first drift region via a gate insulating film; 상기 반도체 기판에서 제 2영역에 제 2도전형 불순물이 주입된 제 2웰과 상기 제 2웰내에 제 1도전형 불순물이 주입된 제 3웰과, 상기 제 3웰내에 서로 소정 간격 이격되도록 제 2도전형 불순물이 주입된 소오스/드레인 영역과, 상기 소오스/드레인 영역 사이의 제 3웰 상부면에 게이트 절연막을 개재하여 적층된 게이트 전극을 갖는 로직 트랜지스터를 포함하는 것을 특징으로 하는 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자.A second well in which a second conductive impurity is implanted into a second region of the semiconductor substrate, a third well in which a first conductive impurity is implanted in the second well, and a second well spaced apart from each other in the third well And a logic transistor having a source / drain region into which a conductive type impurity is implanted, and a gate electrode stacked on the upper surface of the third well between the source / drain region with a gate insulating film interposed therebetween. A semiconductor device having a. 제 1항에 있어서, 상기 반도체 기판의 제 2영역과 이웃하는 영역에서 제 2도전형 불순물이 주입된 제 2웰이 연장되어 있으며 상기 제 2웰내에 제 2도전형 불순물이 주입된 제 4웰과, 상기 제 4웰내에 서로 소정 간격 이격되도록 제 1도전형 불순물이 주입된 소오스/드레인 영역과, 상기 소오스/드레인 영역 사이의 제 4웰 상부면에 게이트 절연막을 개재하여 적층된 게이트 전극을 갖는 또 다른 로직 트랜지 스터를 더 포함하는 것을 특징으로 하는 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자.The semiconductor device of claim 1, further comprising: a fourth well in which a second conductive impurity is implanted in a region adjacent to the second region of the semiconductor substrate and in which a second conductive impurity is implanted into the second well; And a source / drain region in which a first conductive impurity is implanted so as to be spaced apart from each other in the fourth well by a predetermined distance, and a gate electrode stacked on the upper surface of the fourth well between the source / drain region through a gate insulating film. A semiconductor device having a high voltage transistor and a logic transistor, further comprising another logic transistor. 제 1항 또는 제 2항에 있어서, 상기 제 1도전형 불순물은 n형 불순물이며 제 2도전형 불순물은 p형 불순물인 것을 특징으로 하는 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자.The semiconductor device according to claim 1 or 2, wherein the first conductive impurity is an n-type impurity and the second conductive impurity is a p-type impurity. 제 1항 또는 제 2항에 있어서, 상기 제 1도전형 불순물은 p형 불순물이며 제 2도전형 불순물은 n형 불순물인 것을 특징으로 하는 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자.The semiconductor device according to claim 1 or 2, wherein the first conductive impurity is a p-type impurity and the second conductive impurity is an n-type impurity. 제 1항 또는 제 2항에 있어서, 상기 제 3웰과 제 4웰에 각각 문턱 전압 조절용 불순물 이온이 주입된 것을 특징으로 하는 고전압 트랜지스터 및 로직 트랜지스터를 갖는 반도체 소자.The semiconductor device according to claim 1 or 2, wherein impurity ions for adjusting a threshold voltage are implanted into the third and fourth wells, respectively.
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JPH10189762A (en) 1996-12-20 1998-07-21 Nec Corp Semiconductor device and its manufacturing method
JP2002100684A (en) 2000-09-25 2002-04-05 Ricoh Co Ltd Semiconductor device

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JPH10189762A (en) 1996-12-20 1998-07-21 Nec Corp Semiconductor device and its manufacturing method
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