TWI804736B - Power device having lateral insulated gate bipolar transistor (ligbt) and manufacturing method thereof - Google Patents

Abstract

The present invention provides a power device which is formed on a semiconductor substrate. The power device is configured to operably drive a motor. The power device includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode, and a clamp diode . The PN diode is connected to the LIGBT in parallel. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a collector and a gate of the LIGBT, to clamp a gate voltage applied to the gate not higher than a predetermined voltage threshold.

Description

Power device with lateral insulated gate bipolar transistor and manufacturing method thereof

The present invention relates to a power device, in particular to a power device with a lateral insulated gate bipolar transistor (LIGBT). The present invention also relates to a method of manufacturing power components.

1A and 1B show a schematic top view and a schematic cross-sectional view of a prior art power device (power device 100 ) with a lateral insulated gate bipolar transistor (LIGBT). The power element 100 is used to control the flywheel current in the flywheel motor; wherein the flywheel current flows through the power element 100 to drive the flywheel motor. Wherein, the flywheel motor is used to control the flywheel (flywheel) to store the rotational kinetic energy during the rotational movement of the flywheel, which is well known to those skilled in the art, and will not be repeated here. Generally speaking, the power device 100 includes a plurality of LIGBTs connected in parallel (represented by a lateral insulated gate bipolar transistor LIGBT1 in FIGS. 1A and 1B ), and a PN diode.

As shown in FIGS. 1A and 1B , a power device 100 is formed on a semiconductor substrate 11 and includes a lateral insulated gate bipolar transistor LIGBT1 and a PN diode PN1 . picture 1B shows a schematic cross-sectional view of line AA' in FIG. 1A. The PN diode PN1 includes a first field oxide region 121, a first N-type region 131, a first N-type extension region 141, a first P-type region 151, a gate 161, a reverse end 171, and a forward end 181; The first N-type region 131 , the first N-type extension region 141 , the first P-type region 151 , the reverse end 171 and the forward end 181 are all formed in an epitaxial layer on the first insulating bottom layer 12 . The first insulating structure ISO1 includes a first insulating bottom layer 12 and a first insulating sidewall 123 , wherein the first insulating bottom layer 12 is formed on the semiconductor substrate 11 and connected to the semiconductor substrate 11 . The first insulating structure ISO1 encloses the PN diode PN1 under the upper surface of the epitaxial layer, so that the PN diode PN1 is electrically isolated from other components under the upper surface of the epitaxial layer.

The lateral insulated gate bipolar transistor LIGBT1 is formed on the semiconductor substrate 11. As shown in FIGS. N-type extension region 142, second P-type region 152, gate 162, drain 172, emitter 182, and P-type contact 184; wherein, the second N-type region 132, the second N-type extension region 142, the second The P-type region 152 , the drain 172 , the emitter 182 and the P-type contact 184 are formed in the epitaxial layer on the second insulating bottom layer 12 ′. The second insulating structure ISO2 includes a second insulating bottom layer 12' and a second insulating sidewall 124, wherein the second insulating structure ISO2 encloses the lateral insulating gate bipolar transistor LIGBT1 under the upper surface of the epitaxial layer, so that the lateral insulating gate bipolar transistor LIGBT1 The insulated gate bipolar transistor LIGBT1 is under the upper surface of the epitaxial layer, electrically isolating other components. As shown in FIG. 1A, the third insulating sidewall 125 forms an annular closed sidewall, enclosing the first insulating sidewall 123 and the second insulating sidewall 124, that is, enclosing the power element 100 in the ring formed by the third insulating sidewall 125. in the closed side wall.

1C and 1D respectively show a circuit symbol and a schematic diagram of an electrical characteristic curve of the power device 100 . The operation mechanism of the lateral insulated gate bipolar transistor LIGBT1 is shown by the circuit symbol of the thick black solid line in FIG. pole E), the base current in the PNP bipolar junction transistor (bipolar junction transistor, BJT) formed by the second N-type extension region 142 and the second P-type region 152, conducts the lateral insulated gate bipolar transistor For LIGBT1, by designing the base width and concentration, the amplification factor of the conduction current IC can be determined to obtain the best conduction voltage and reduce power loss. The base current of the lateral insulated gate bipolar transistor LIGBT1 is controlled by the gate voltage, that is, the voltage applied to the gate 162 . As the gate voltage increases, the base current increases proportionally to the emitter current.

When the lateral insulated gate bipolar transistor LIGBT1 is applied to drive the motor, it needs to pass the short circuit test (short circuits test). The test method is to apply the lateral insulated gate bipolar transistor LIGBT1 to the gate 162 (gate The voltage of G) is increased to the maximum supply voltage (usually 15~20V), and the voltage applied to the emitter 182 (emitter E) is increased to the bulk voltage, such as but not limited to 400V. At this time, the conduction current IC reaches the maximum current due to flowing through the drain 172 (drain C). When the maximum conduction current IC passes through the resistor Re, it is easy to trigger the parasitic NPNBJT composed of the second N-type region 132, the second P-type region 152 and the drain 172 in the lateral insulated gate bipolar transistor LIGBT1 to turn on, triggering the parasitic The PNPN latch-up effect in the lateral insulated gate bipolar transistor LIGBT1 causes damage to the high voltage device 100 . Excessive conduction current IC will increase the risk of damage to the high-voltage element 100 , so the maximum current of conduction current IC can be appropriately limited to reduce the probability of triggering the latch-up effect.

The traditional method of controlling the base current to limit the conduction current IC is to control the voltage applied to the gate 162 to avoid excessive voltage changes applied to the gate 162 . The method is usually to use the voltage stabilizing circuit in another gate drive circuit to suppress the abnormally high voltage source. This method can effectively control the problem of unstable voltage source, but for the gate-emitter capacitance Cge caused by external short circuit If the induced voltage is too large, the effect is limited. As shown in Figure 1C, because when the short circuit test is performed externally, when the high voltage of other phases contacts the phase to be tested, the voltage applied to the emitter 182 will be pulled up to cause a surge (as shown in Figure 1C, the signal waveform next to the emitter E As shown) and sensed through the gate-emitter capacitance Cge, and then as shown in Figure 1D, the voltage applied to the gate G (as shown in the signal waveform next to the gate G in Figure 1C) increases, thereby causing The base current and conduction current IC are greatly increased, which greatly increases the probability of the PNPN latch-up effect being triggered in the lateral insulated gate bipolar transistor LIGBT1.

In view of this, the present invention aims at the deficiencies of the above-mentioned prior art, and proposes a power element with a lateral insulated gate bipolar transistor and a manufacturing method thereof, which can reduce the occurrence probability of the latch-up effect of the power element 100 and improve the power element 100. scope of application.

In terms of one of the viewpoints, the present invention provides a power element formed on a semiconductor substrate for driving a motor, comprising: a lateral insulated gate bipolar transistor (LIGBT); a PN A diode connected in parallel with the lateral insulated gate bipolar transistor; and a clamping diode with a clamping forward end and a clamping inverse end electrically connected to the lateral insulated gate bipolar transistor respectively one of the transistors pole and a gate, so as to limit a gate voltage applied to the gate not to be higher than a preset voltage threshold.

From another point of view, the present invention provides a method of manufacturing a power device, wherein the power device is formed on a semiconductor substrate for driving a motor, and the method of manufacturing the power device includes: forming a lateral insulated gate bipolar transistor (lateral insulated gate bipolar transistor, LIGBT); forming a PN diode in parallel with the lateral insulated gate bipolar transistor; and forming a clamping diode with a clamping forward end and a clamping reverse The opposite ends are respectively electrically connected to a drain and a gate of the lateral insulated gate bipolar transistor, so as to limit a gate voltage applied to the gate not to be higher than a preset voltage threshold.

In a preferred implementation mode, the PN diode includes: a first N-type region formed in an epitaxial layer on the semiconductor substrate; a first P-type region formed in the first N-type region In the type region; a first N-type extension region is formed in the first N-type region, and the first N-type extension region and the first P-type region are separated by the first N-type region; a first a reverse end, with N-type conductivity, formed in the first N-type extension region, used as an electrical contact of the first N-type extension region; and a first forward end, with P-type conductivity , formed in the first P-type region, used as an electrical contact of the first P-type region.

In a preferred implementation form, the lateral insulated gate bipolar transistor includes: a second N-type region formed in the epitaxial layer on the semiconductor substrate; a second P-type region formed in the In the second N-type region; the drain, having N-type conductivity, is formed in the second P-type region; a P-type contact electrode is formed in the second P-type region as the second P-type The electrical contact of the type region; the gate is formed on the epitaxial layer, and part of the gate is connected to the first above the two P-type regions; a second N-type extension region is formed in the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region; and an emitter with P-type conductivity formed in the second N-type extension region.

In a preferred implementation form, the clamping diode system is a Zener diode, which includes: a third P-type region formed in the epitaxial layer on the semiconductor substrate; a second forward end, with P-type conductivity, formed in the third P-type region, used as the electrical contact between the forward end of the clamp and the third P-type region; a third N-type extension region, formed in In the third P-type region; and a second reverse end, having N-type conductivity, formed in the third N-type extension region, used as the clamping reverse end and the third N-type extension region the electrical contacts.

In a preferred implementation form, the Zener diode further includes an N-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the N-type adjustment region is on the upper surface The top is between the third P-type region and the third N-type extension region, and is used for adjusting the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region.

In a preferred implementation form, the Zener diode further includes a P-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the P-type adjustment region is on the upper surface The top is between the third P-type region and the third N-type extension region, and is used for adjusting the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region.

In a preferred implementation form, the zener diode further includes an electrostatic discharge (ESD) protection area, having N-type conductivity, formed under the upper surface of the epitaxial layer and connected to the upper surface , and the electrostatic protection area is between the third N-type extension area and the second forward end on the upper surface, and the electrostatic protection area is used to communicate with the third P-type area and the The third N-type extension region forms an NPN transistor, wherein the electrostatic protection region is electrically connected to the second forward end.

In a preferred embodiment, the first N-type extension region, the second N-type extension region and the third N-type extension region are simultaneously formed by the same lithography process step and ion implantation process step; Wherein the first P-type region and the second P-type region are simultaneously formed by the same lithography process steps and ion implantation process steps; wherein the first reverse end, the drain and the second reverse end are formed by the same The lithography process step and the ion implantation process step are formed simultaneously; wherein the first forward end, the emitter, the P-type contact pole and the second forward end are formed by the same lithography process step and ion implantation The process steps are formed simultaneously.

In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

100,200,400,500: power components

121,221,321,421,521: the first oxidation area

122,222,322,422,522: second field oxidation area

123,223,323,423,523: first insulating side wall

124,224,324,424,524: second insulating side wall

125,225,325,425,525: third insulating side wall

131,231,331,431,531: the first N-type region

132,232,332,432,532: the second N-type region

141,241,341,441,541: first N-type extension

142,242,342,442,542: second N-type extension

151,251,351,451,551: the first P-type region

152,252,352,452,552: the second P-type region

161,261,361,462,562: gate

162,262,362,462,562: gate

171: reverse end

172,272,372,472,572: drain

181: forward end

182,282,382,482,582: Emitter

184,284,384,484,584: P-type contact pole

226,326,426,526: fourth insulating sidewall

227,327,427,527: third field oxidation area

228,328,428,528: the fourth field oxidation area

243,343,443,543: third N-type extension

253,353,453,553: the third P-type region

271,371,471,571: the first reverse end

273,373,473,573: second reverse end

281,381,481,581: the first forward end

285,385,485,585: the second forward end

AA', BB', CC', DD', EE': broken line

C: drain

E: Emitter

F: forward end

G: gate

LIGBT1, LIGBT2, LIGBT3, LIGBT4, LIGBT5: Lateral Insulated Gate Bipolar Transistors

PN1, PN2, PN3, PN4, PN5: PN diodes

R: reverse end

ZD1, ZB2, ZD3, ZD4, ZD5: Zener diodes

1A and 1B show a schematic top view and a schematic cross-sectional view of a prior art power device (power device 100 ) with a lateral insulated gate bipolar transistor (LIGBT).

1C and 1D respectively show a circuit symbol and a schematic diagram of an electrical characteristic curve of the power device 100 .

2A-2B show schematic diagrams of an embodiment of a power device according to the present invention.

3A-3B show schematic diagrams of another embodiment of a power device according to the present invention.

4A-4B show schematic diagrams of another embodiment of a power device according to the present invention.

5A-5B show schematic diagrams of yet another embodiment of a power device according to the present invention.

6A-6H show schematic diagrams of an embodiment of a manufacturing method of a power device according to the present invention.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the relationship between the upper and lower order of each layer, and the shapes, thicknesses and widths are not drawn to scale.

2A-2B show schematic diagrams of an embodiment of a power device according to the present invention. The power element 200 according to the present invention is formed on a semiconductor substrate 21 for driving a motor, including a lateral insulated gate bipolar transistor LIGBT2, a PN diode PN2 and a clamping diode (in this embodiment, aligned with Nanodiode ZD1 acts as a clamping diode). As shown in FIGS. 2A and 2B , a power device 200 is formed on a semiconductor substrate 21 , which includes a lateral insulated gate bipolar transistor LIGBT2 , a PN diode PN2 and a Zener diode ZD1 . Among them, the Zener diode ZD1 is used as a clamping diode to limit the voltage applied to the lateral insulating gate bipolar transistor. The gate voltage of the gate 262 of the body LIGBT2 is not higher than the preset voltage threshold, so as to avoid triggering the latch-up effect and protect the power device 200 .

FIG. 2B shows a schematic cross-sectional view of the section line BB' in FIG. 2A. In the power device 200 , the coupling manner of the lateral insulated gate bipolar transistor LIGBT2 , the PN diode PN2 and the Zener diode ZD1 is shown in the small diagram of the circuit symbol in FIG. 2A . In the small diagram of the circuit symbol, the lateral insulated gate bipolar transistor LIGBT2 has a gate G, an emitter E, and a drain C; the PN diode PN2 has a forward end F1 and a reverse end R1; a Zener diode ZD1 has a forward end F2 and a reverse end R2. The PN diode PN2 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT2; the Zener diode ZD1 is electrically connected between the gate G and the drain C of the lateral insulated gate bipolar transistor LIGBT2. Among them, the drain C and the emitter E of the lateral insulated gate bipolar transistor LIGBT2 are respectively electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN2; the forward end of the Zener diode ZD1 F2 and the reverse terminal R2 are respectively electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT2 .

According to the present invention, the power element 200 is not limited to only having a single lateral insulated gate bipolar transistor LIGBT2 , but can also be composed of two or more lateral insulated gate bipolar transistors connected in parallel. According to the present invention, the power element 200 may also include a plurality of PN diodes. In a preferred embodiment, in the power element 200, the number of PN diodes is less than the number of lateral insulated gate bipolar transistors LIGBT2 .

Wherein, the PN diode PN2 includes a first field oxide region 221, a first N-type region 231, a first N-type extension region 241, a first P-type region 251, a gate 261, a first reverse terminal 271 and a first forward end 281 . The bottom and side surfaces of PN diode PN2 are formed by the first insulating structure ISO3. surrounded. Wherein, the first insulating structure ISO3 includes a first insulating bottom layer 22 and a first insulating sidewall 223 .

Wherein, the first N-type region 231 is formed in the epitaxial layer EPI on the semiconductor substrate 21 . The first P-type region 251 is formed in the first N-type region 231 . The first N-type extension region 241 is formed in the first N-type region 231 , and the first N-type extension region 241 is separated from the first P-type region 251 by the first N-type region 231 . The first reverse end 271 has N-type conductivity and is formed in the first N-type extension region 241 to serve as an electrical contact of the first N-type extension region 241 . The first forward end 281 has a P-type conductivity and is formed in the first P-type region 251 to serve as an electrical contact of the first P-type region 251 .

The lateral insulated gate bipolar transistor LIGBT2 is formed on the semiconductor substrate 21. As shown in FIGS. The N-type extension region 242 , the second P-type region 252 , the gate 262 , the drain 272 , the emitter 282 and the P-type contact 284 . The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT2 are surrounded by the second insulating structure ISO4. Wherein, the second insulating structure ISO4 includes a second insulating bottom layer 22' and a second insulating sidewall 224. When the lateral insulated gate bipolar transistor LIGBT2 is plural, they are electrically connected in parallel with each other, that is, the gate 262, the drain 272, the emitter 282 and the P-type contact of different lateral insulated gate bipolar transistors LIGBT2 The poles 284 are electrically connected to each other correspondingly.

Wherein, the second N-type region 232 is formed in the epitaxial layer EPI on the semiconductor substrate 21 . The second P-type region 252 is formed in the second N-type region 232 . The drain 272 has N-type conductivity and is formed in the second P-type region 252 . The P-type contact electrode 284 is formed in the second P-type region 252 to serve as an electrical contact of the second P-type region 252 . Gate 262 is formed on the epitaxial layer, part of which is The pole is connected to the second P-type region. A second N-type extension region is formed in the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region. The emitter, having P-type conductivity, is formed in the second N-type extension region.

The Zener diode ZD1 is formed on the semiconductor substrate 21. As shown in FIGS. 2A and 2B, the Zener diode ZD1 includes a third field oxide region 227, a fourth field oxide region 228, a third N-type region 233, Three N-type extension regions 243 , a third P-type region 253 , a second reverse end 273 and a second forward end 285 . The bottom and side surfaces of the Zener diode ZD1 are surrounded by the third insulating structure ISO5. Wherein, the third insulating structure ISO5 includes a third insulating bottom layer 22 ″ and a third insulating sidewall 225 .

Wherein, the third P-type region 253 is formed in the epitaxial layer EPI on the semiconductor substrate 21 . The second forward end 285 has a P-type conductivity and is formed in the third P-type region 253 to serve as a clamp forward end and an electrical contact of the third P-type region 253 . The third N-type extension region 243 is formed in the third P-type region 253 . The second reverse end 273 has N-type conductivity and is formed in the third N-type extension region 243 to serve as a clamping reverse end and an electrical contact of the third N-type extension region 243 .

2A and 2B, the fourth insulating sidewall 226 forms an annular closed sidewall, enclosing the first insulating sidewall 223, the second insulating sidewall 224 and the third insulating sidewall 225, that is, enclosing the power element 200 in the first insulating sidewall. The four insulating sidewalls 226 form an annular closed sidewall.

Wherein, the first insulating base layer 22, the second insulating base layer 22' and the second insulating base layer 22" are formed on the semiconductor substrate 21. The semiconductor substrate 21 is, for example but not limited to, a P-type or N-type semiconductor silicon substrate, and can also be other Semiconductor substrate. For example, form on the semiconductor substrate 21 Form a silicon dioxide layer, part of which is used as the first insulating base layer 22, another part as the second insulating base layer 22', and another part as the third insulating base layer 22". On the silicon dioxide layer, for example, an N-type epitaxial layer is formed , a part is used as the first N-type region 231, another part is used as the second N-type region 232, and another part is used as the third N-type region 233. The aforementioned semiconductor substrate 21, silicon dioxide layer and N-type epitaxial layer can use an insulating layer Silicon on insulator (SOI) wafers, which are well known to those skilled in the art, will not be repeated here.

The first insulating sidewall 223, the second insulating sidewall 224, the third insulating sidewall 225, and the fourth insulating sidewall 226 are, for example but not limited to, forming a deep trench at the same time by the same deep trench etching process step; and by the same deposition process step, simultaneously insulating the Material, such as but not limited to silicon dioxide, is deposited in the aforementioned deep trench to form the first insulating sidewall 223 , the second insulating sidewall 224 , the third insulating sidewall 225 and the fourth insulating sidewall 226 . And the first insulating sidewall 223, the second insulating sidewall 224, the third insulating sidewall 225, and the fourth insulating sidewall 226 are connected to the silicon dioxide layer connected to the semiconductor substrate 21 below, so as to form a closed layer in the epitaxial layer, respectively. range. Wherein, in a preferred embodiment, the bottom surface and side surfaces of the PN diode PN2 are surrounded by the first insulating structure ISO3; the bottom surface and the side surfaces of the lateral insulated gate bipolar transistor LIGBT2 are surrounded by the second insulating structure ISO4 ; and the bottom and side surfaces of the Zener diode ZD1 are surrounded by the third insulating structure ISO5.

Please continue to refer to FIGS. 2A and 2B, wherein the first N-type extension region 241, the second N-type extension region 242, and the third N-type extension region 243 are, for example but not limited to, defined by the same lithography process steps while defining the first N type extension region 241, the second N-type extension region 242 and the third N-type extension region 243; In the form of ions, the regions defined by the aforementioned lithography process steps are implanted to form the first N-type extension region 241 , the second N-type extension region 242 and the third N-type extension region 243 . The first N-type extension region 241, the second N-type extension region 242, and the third N-type extension region 243 have N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under the upper surface of the N-type epitaxial layer and attached to the upper surface.

The first field oxidation region 221, the second field oxidation region 222, the third field oxidation region 227 and the fourth field oxidation region 228 are, for example but not limited to, formed simultaneously on the upper surface of the aforementioned N-type epitaxial layer by the same oxidation process steps. and connected to the upper surface. The first field oxidation region 221, the second field oxidation region 222, the third field oxidation region 227 and the fourth field oxidation region 228 are not limited to the local oxidation of silicon (LOCOS) structure as shown in FIG. It is a shallow trench isolation (STI) structure. As shown in FIG. 2A , the first field oxide region 221 , the second field oxide region 222 , the third field oxide region 227 and the fourth field oxide region 228 are, for example, ring-shaped closed structures viewed from the top view. Wherein, the first field oxide region 221 , the second field oxide region 222 and the third field oxide region 227 surround the reverse end 271 , the emitter 282 and the reverse end 273 respectively.

The first P-type region 251 and the second P-type region 252 are, for example but not limited to, defined by the same lithography process steps, while defining the regions of the first P-type region 251 and the second P-type region 252; and by the same ion implantation In the process step, P-type impurities are implanted in the form of accelerated ions into the regions defined by the aforementioned lithography process steps to form the first P-type region 251 and the second P-type region 252 . The first P-type region 251 and the second P-type region 252 have P-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under and connected to the upper surface of the N-type epitaxial layer. As shown in FIG. 2A , the first P-type region 251 and the second P-type region 252 are viewed from a top view, for example, are ring-shaped closed regions, surrounding the first field oxide region 221 and the second field oxide region 222 respectively.

As shown in FIG. 2A , the gate 261 and the gate 262 are viewed from the top view, for example, both are annular closed areas. From the top view of FIG. 2A , the gate electrode 261 is formed and contacts part of the first field oxide region 221 , and surrounds other parts of the first field oxide region 221 . From the top view of FIG. 2A , the gate electrode 262 is formed and contacts part of the second field oxide region 222 and surrounds other parts of the second field oxide region 222 .

The gate 261 and the gate 262 are, for example but not limited to, formed simultaneously by the same gate process steps. Wherein, the gate 261 and the gate 262 include, for example, respective dielectric layers, conductive layers and spacer layers, which are well known to those skilled in the art, and here I won't go into details. Therefore, the gate process steps include process steps such as lithography and oxidation to form a dielectric layer; process steps such as lithography and deposition to form a conductive layer; and process steps such as deposition and etching to form a spacer layer

The first forward end 281, the emitter 282, the P-type contact pole 284, and the second forward end 285 are, for example but not limited to, defined by the same lithography process steps to define the first forward end 281, the emitter 282, the P-type The region of the contact pole 284 and the second forward end 285; and by the same ion implantation process step, simultaneously p-type impurities are implanted into the region defined by the aforementioned lithography process step in the form of accelerated ions, to A first forward end 281 , an emitter 282 , a P-type contact 284 and a second forward end 285 are formed. The first forward end 281, the emitter 282, the P-type contact pole 284, and the second forward end 285 have P-type conductivity, and are respectively formed in the first P-type region 251, the second N-type extension region 242, the second P-type The third P-type region 252 and the third P-type region 253 are located under the upper surface of the N-type epitaxial layer and connected to the upper surface. As shown in Figure 2A, the first forward end 281, the P-type contact pole 284 and the second forward Viewed from the top view, the end 285 is, for example, an annular closed area, surrounding the gate 261 , the drain 272 and the fourth field oxide region 228 respectively.

The first reverse end 271, the drain 272 and the second reverse end 273 are, for example but not limited to, formed by the same lithography process step (including using the gate 262 as a mask), and simultaneously define the first reverse end 271, the drain 272 and the region of the second opposite end 273; and by the same ion implantation process step, the N-type impurity is implanted in the form of accelerated ions into the region defined by the aforementioned lithography process step to form the first An inverting terminal 271 , a drain 272 and a second inverting terminal 273 . The first reverse end 271 , the drain 272 and the second reverse end 273 have N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under and connected to the upper surface of the N-type epitaxial layer. As shown in FIG. 2A , the drain 272 is seen from a top view, for example, is a ring-shaped closed area surrounding the gate 262 .

The present invention is superior to the prior art. In this embodiment, the Zener diode ZD1 can not only limit the voltage applied to the gate, not higher than the preset voltage threshold; it can also prevent the gate-emitter capacitance The induced voltage of Cge is too large, and the resulting voltage applied to the gate is too high, which avoids the increase of the base current and the conduction current IC, thereby preventing the PNPN latch-up effect in the lateral insulated gate bipolar transistor LIGBT1 from being triggered. In addition, the Zener diode ZD1 is formed by using the same lithography process steps and the same ion implantation process steps as the lateral insulated gate bipolar transistor LIGBT2, without additionally increasing the manufacturing cost.

3A-3B show schematic diagrams of another embodiment of a power device according to the present invention. As shown in FIGS. 3A and 3B , a power device 300 is formed on a semiconductor substrate 31 , which includes a lateral insulated gate bipolar transistor LIGBT3 , a PN diode PN3 and a Zener diode ZD2 . Among them, the Zener diode ZD2 is used as a clamping diode to limit the lateral The gate voltage of the gate of the IGBT LIGBT3 is not higher than a preset voltage threshold, so as to avoid triggering the latch-up effect and protect the power device 300 .

FIG. 3B shows a schematic cross-sectional view of line CC' in FIG. 3A. In the power element 300 , the coupling manner of the lateral insulated gate bipolar transistor LIGBT3 , the PN diode PN3 and the Zener diode ZD2 is shown in the small diagram of the circuit symbol in FIG. 3A . In the small diagram of the circuit symbol, the lateral insulated gate bipolar transistor LIGBT3 has a gate G, an emitter E, and a drain C; the PN diode PN3 has a forward end F1 and a reverse end R1; a Zener diode ZD2 has a forward end F2 and a reverse end R2. The PN diode PN3 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT3; the Zener diode ZD2 is electrically connected between the gate G and the drain C of the lateral insulated gate bipolar transistor LIGBT3. Among them, the drain C and the emitter E of the lateral insulated gate bipolar transistor LIGBT3 are respectively electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN3; the forward end of the Zener diode ZD2 F2 and the reverse terminal R2 are electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT3 respectively.

Wherein, the PN diode PN3 includes a first field oxide region 321, a first N-type region 331, a first N-type extension region 341, a first P-type region 351, a gate 361, a first reverse terminal 371 and a first forward end 381 . The bottom and side surfaces of the PN diode PN3 are surrounded by the first insulating structure ISO6. Wherein, the first insulating structure ISO6 includes a first insulating bottom layer 32 and a first insulating sidewall 323 .

The lateral insulated gate bipolar transistor LIGBT3 is formed on the semiconductor substrate 31. As shown in FIGS. The N-type extension region 342, the second P-type region 352, the gate pole 362 , drain pole 372 , emitter pole 382 and P-type contact pole 384 . The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT3 are surrounded by the second insulating structure ISO7. Wherein, the second insulating structure ISO7 includes a second insulating bottom layer 32' and a second insulating sidewall 324. When the lateral insulated gate bipolar transistor LIGBT3 is plural, they are electrically connected in parallel with each other, that is, the gate 362, the drain 372, the emitter 382 and the P-type contact of different lateral insulated gate bipolar transistors LIGBT3 The poles 384 are electrically connected to each other correspondingly.

The Zener diode ZD2 is formed on the semiconductor substrate 31. As shown in FIGS. 3A and 3B, the Zener diode ZD2 includes a third field oxide region 327, a fourth field oxide region 328, a third N-type region 333, Three N-type extension regions 343 , a third P-type region 353 , a second reverse end 373 , an N-type adjustment region 374 and a second forward end 385 . The bottom and side surfaces of the Zener diode ZD2 are surrounded by the third insulating structure ISO8. Wherein, the third insulating structure ISO8 includes a third insulating bottom layer 32 ″ and a third insulating sidewall 325 .

3A and 3B, the fourth insulating sidewall 326 forms an annular closed sidewall, enclosing the first insulating sidewall 323, the second insulating sidewall 324 and the third insulating sidewall 325, that is, enclosing the power element 300 in the first insulating sidewall. The four insulating sidewalls 326 form an annular closed sidewall.

The difference between this embodiment and the embodiment shown in FIGS. 2A-2B is that, in this embodiment, as shown in FIGS. 3A and 3B , compared with the power element 200, in the power element 300, the Zener diode Body ZD2 further includes an N-type adjustment region 374 formed under the upper surface of the epitaxial layer EPI and connected to the upper surface, and the N-type adjustment region 374 is located between the third P-type region 353 and the third N-type region on the upper surface. Type extension region 343 is used to adjust the forward voltage of the PN junction formed by the third P-type region 353 and the third N-type extension region 343 .

4A-4B show schematic diagrams of another embodiment of a power device according to the present invention. As shown in FIGS. 4A and 4B , a power device 400 is formed on a semiconductor substrate 41 , which includes a lateral insulated gate bipolar transistor LIGBT4 , a PN diode PN4 and a Zener diode ZD3 . Among them, the Zener diode ZD3 is used as a clamping diode to limit the gate voltage applied to the gate of the lateral insulated gate bipolar transistor LIGBT4 from being higher than a preset voltage threshold to avoid triggering latch-up effect, while protecting the power element 400.

FIG. 4B shows a schematic cross-sectional view of the section line DD' in FIG. 4A. In the power element 400 , the coupling manner of the lateral insulated gate bipolar transistor LIGBT4 , the PN diode PN4 and the Zener diode ZD3 is shown in the small diagram of the circuit symbol in FIG. 4A . In the small diagram of the circuit symbol, the lateral insulated gate bipolar transistor LIGBT4 has a gate G, an emitter E, and a drain C; the PN diode PN4 has a forward end F1 and a reverse end R1; a Zener diode ZD3 has a forward end F2 and a reverse end R2. The PN diode PN4 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT4; the Zener diode ZD3 is electrically connected between the gate G and the drain C of the lateral insulated gate bipolar transistor LIGBT4. Among them, the drain C and the emitter E of the lateral insulated gate bipolar transistor LIGBT4 are respectively electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN4; the forward end of the Zener diode ZD3 The F2 and the reverse terminal R2 are electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT4 respectively.

Wherein, the PN diode PN4 includes a first field oxide region 421, a first N-type region 431, a first N-type extension region 441, a first P-type region 451, a gate 461, a first reverse terminal 471 and and the first forward end 481 . The bottom and side surfaces of the PN diode PN4 are surrounded by the first insulating structure ISO9. Wherein, the first insulating structure ISO9 includes a first insulating bottom layer 42 and a first insulating sidewall 423 .

The lateral insulated gate bipolar transistor LIGBT4 is formed on the semiconductor substrate 41. As shown in FIGS. The N-type extension region 442 , the second P-type region 452 , the gate 462 , the drain 472 , the emitter 482 and the P-type contact 484 . The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT4 are surrounded by the second insulating structure ISO10. Wherein, the second insulating structure ISO10 includes a second insulating bottom layer 42' and a second insulating sidewall 424. When the lateral insulated gate bipolar transistor LIGBT4 is plural, they are electrically connected in parallel with each other, that is, the gate 462, the drain 472, the emitter 482 and the P-type contact of different lateral insulated gate bipolar transistors LIGBT4 The poles 484 are electrically connected to each other correspondingly.

The Zener diode ZD3 is formed on the semiconductor substrate 41. As shown in FIGS. 4A and 4B, the Zener diode ZD3 includes a third field oxide region 427, a fourth field oxide region 428, a third N-type region 433, Three N-type extension regions 443 , a third P-type region 453 , a second reverse end 473 , a P-type adjustment region 486 and a second forward end 485 . The bottom and side surfaces of the Zener diode ZD3 are surrounded by the third insulating structure ISO11. Wherein, the third insulating structure ISO11 includes a third insulating bottom layer 42 ″ and a third insulating sidewall 425 .

As shown in FIGS. 4A and 4B , the fourth insulating sidewall 426 forms an annular closed sidewall, enclosing the first insulating sidewall 423 , the second insulating sidewall 424 and the third insulating sidewall 425 . Wherein, the power element 400 is surrounded by the ring-shaped closed sidewall formed by the fourth insulating sidewall 426 .

The difference between this embodiment and the embodiment shown in FIGS. 2A-2B is that, in this embodiment, as shown in FIGS. 4A and 4B , compared with the power element 200, in the power element 400, the Zener diode Body ZD3 further includes a P-type adjustment region 486 formed under the upper surface of the epitaxial layer EPI and connected to the upper surface, and the P-type adjustment region 486 is on the upper surface between the third P-type region 453 and the third N-type extension Between the regions 443 , it is used to adjust the forward voltage of the PN junction formed by the third P-type region 353 and the third N-type extension region 343 .

5A-5B show schematic diagrams of another embodiment of a power device according to the present invention. As shown in FIGS. 5A and 5B , a power device 500 is formed on a semiconductor substrate 51 , which includes a lateral insulated gate bipolar transistor LIGBT5 , a PN diode PN5 and a Zener diode ZD4 . Among them, the Zener diode ZD4 is used as a clamping diode to limit the gate voltage applied to the gate of the lateral insulated gate bipolar transistor LIGBT5 from being higher than a preset voltage threshold to avoid triggering latch-up effect, while protecting the power element 500.

FIG. 5B shows a schematic cross-sectional view of line EE' in FIG. 5A. In the power element 500 , the coupling manner of the lateral insulated gate bipolar transistor LIGBT5 , the PN diode PN5 and the Zener diode ZD4 is shown in the small diagram of the circuit symbol in FIG. 5A . In the small diagram of the circuit symbol, the lateral insulated gate bipolar transistor LIGBT53 has a gate G, an emitter E, and a drain C; the PN diode PN5 has a forward end F1 and a reverse end R1; a Zener diode ZD4 has a forward end F2 and a reverse end R2. The PN diode PN5 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT5; the Zener diode ZD4 is electrically connected to the lateral insulated gate bipolar transistor LIGBT5 between the gate G and the drain C. Among them, the drain C and the emitter E of the lateral insulated gate bipolar transistor LIGBT5 are respectively electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN5; the forward end of the Zener diode ZD4 F2 and the reverse terminal R2 are respectively electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT5.

Among them, the PN diode PN5 includes a first field oxide region 521, a first N-type region 531, a first N-type extension region 541, a first P-type region 551, a gate 561, a first reverse terminal 571 and a first forward end 581 . The bottom and side surfaces of the PN diode PN5 are surrounded by the first insulating structure ISO12. Wherein, the first insulating structure ISO12 includes a first insulating bottom layer 52 and a first insulating sidewall 523 .

The lateral insulated gate bipolar transistor LIGBT5 is formed on the semiconductor substrate 51. As shown in FIGS. The N-type extension region 542 , the second P-type region 552 , the gate 562 , the drain 572 , the emitter 582 and the P-type contact 584 . The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT5 are surrounded by the second insulating structure ISO13. Wherein, the second insulating structure ISO13 includes a second insulating bottom layer 52' and a second insulating sidewall 524. When the lateral insulated gate bipolar transistor LIGBT5 is plural, they are electrically connected in parallel with each other, that is, the gate 562, the drain 572, the emitter 582 and the P-type contact of different lateral insulated gate bipolar transistors LIGBT5 The poles 584 are electrically connected to each other correspondingly.

The Zener diode ZD4 is formed on the semiconductor substrate 51. As shown in FIGS. Three N-type regions 533, third N-type extension regions 543, third P-type regions 553, second The reverse end 573 , the N-type adjustment area 574 , the electrostatic discharge (ESD) protection area 575 and the second forward end 585 . The bottom and side surfaces of the Zener diode ZD4 are surrounded by the third insulating structure ISO14. Wherein, the third insulating structure ISO14 includes a third insulating bottom layer 52 ″ and a third insulating sidewall 525 .

5A and 5B, the fourth insulating sidewall 526 forms an annular closed sidewall, enclosing the first insulating sidewall 523, the second insulating sidewall 524 and the third insulating sidewall 525, that is, enclosing the power element 500 in the first insulating sidewall. The four insulating sidewalls 526 form an annular closed sidewall.

The difference between this embodiment and the embodiment shown in FIGS. 3A-3B is that in this embodiment, as shown in FIGS. 5A and 5B , compared with the power element 300, in the power element 500, the Zener diode Body ZD4 further includes an ESD protection region 575 and a fifth field oxide region 529 . The ESD protection area 575 has N-type conductivity, formed under the upper surface of the epitaxial layer EPI and connected to the upper surface, and the electrostatic protection area 575 is on the upper surface between the third N-type extension area 543 and the second forward end. Between 585, the electrostatic protection area 575 is used to form an NPN transistor with the third P-type region 553 and the third N-type extension region 543, wherein the electrostatic protection area 575 is electrically connected to the second forward end 585 for use in the power element 500 When exposed to static voltage, the NPN transistor can be turned on to prevent the static voltage from causing damage to the power element 500 .

6A-6I show schematic diagrams of an embodiment of a manufacturing method of the power device 200 according to the present invention. 6A-6I are schematic cross-sectional views of the manufacturing method of the power device 200 viewed from the line BB' in FIG. 2B . As shown in Figure 6A, first form the first insulating base layer 22, the second insulating base layer 22' and the third insulating base layer 22" on the substrate 21. The substrate 21 is for example but not It is limited to a P-type or N-type semiconductor silicon substrate, and can also be other semiconductor substrates. For example, a silicon dioxide layer is formed on the substrate 21, part of which is used as the first insulating bottom layer 22, another part is used as the second insulating bottom layer 22', and another part is used as the third insulating bottom layer 22". On the silicon dioxide layer, for example, formed The N-type epitaxial layer is partially used as the first N-type region 231, another part is used as the second N-type region 232, and another part is used as the third N-type region 233. The aforementioned substrate 21, silicon dioxide layer and N-type epitaxial layer It can be implemented by using a silicon on insulator (SOI) wafer, which is well known to those skilled in the art, and will not be repeated here.

Next, as shown in FIG. 6B, a first insulating sidewall 223, a second insulating sidewall 224, and a third insulating sidewall 225 are formed, for example, but not limited to, deep trenches are formed simultaneously by the same deep trench etching process steps; and by the same deposition process step, simultaneously deposit insulating material, such as but not limited to silicon dioxide, in the aforementioned deep trench to form the first insulating sidewall 223 , the second insulating sidewall 224 , the third insulating sidewall 225 and the fourth insulating sidewall 226 . And the first insulating sidewall 223, the second insulating sidewall 224, the third insulating sidewall 225, and the fourth insulating sidewall 226 are connected to the silicon dioxide layer connected to the substrate 21 below, so as to form a closed layer in the epitaxial layer EPI, respectively. range. Wherein, in a preferred embodiment, the bottom surface and side surfaces of the PN diode PN2 are surrounded by the first insulating structure ISO3; the bottom surface and the side surfaces of the lateral insulated gate bipolar transistor LIGBT2 are surrounded by the second insulating structure ISO4 ; and the bottom and side surfaces of the Zener diode ZD1 are surrounded by the third insulating structure ISO5.

Next, as shown in FIG. 6C, a first N-type extension region 241, a second N-type extension region 242 and a third N-type extension region 243 are formed, for example but not limited to the same lithography process steps to define the first N-type extension region at the same time. N-type extension region 241 , second N-type extension region 242 and third N-type extension region 243; and by the same ion implantation process step, N-type impurities are implanted in the form of accelerated ions into the region defined by the aforementioned lithography process steps to form the first N-type extension region 241, The second N-type extension region 242 and the third N-type extension region 243 . The first N-type extension region 241, the second N-type extension region 242, and the third N-type extension region 243 have N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under the upper surface of the N-type epitaxial layer and attached to the upper surface.

Next, as shown in FIG. 6D, the first field oxide region 221, the second field oxide region 222, the third field oxide region 227, and the fourth field oxide region 228 are formed, for example but not limited to, by the same oxidation process steps, and at the same time formed on the upper surface of the aforementioned N-type epitaxial layer and connected to the upper surface. The formation of the first field oxidation region 221, the second field oxidation region 222, the third field oxidation region 227 and the fourth field oxidation region 228 is not limited to the local oxidation of silicon (LOCOS) structure as shown in FIG. It may be a shallow trench isolation (STI) structure. Please refer to FIG. 2A at the same time, forming the first field oxidation region 221, the second field oxidation region 222, the third field oxidation region 227 and the fourth field oxidation region 228. From the top view of FIG. 2A, for example, they are ring-shaped closed structures, respectively surrounded Part of the first N-type extension region 241 , part of the second N-type extension region 242 , part of the third N-type extension region 243 and part of the third N-type region 233 .

Next, as shown in FIG. 6E , a first P-type region 251 , a second P-type region 252 and a third P-type region 253 are formed. Among them, for example but not limited to, the same lithography process step is used to simultaneously define the regions of the first P-type region 251 and the second P-type region 252; and the same ion implantation process step is used to simultaneously inject P-type impurities to accelerate In the form of ions, the regions defined by the aforementioned lithography process steps are implanted to form the first P-type region 251 and the second P-type region 252 . For example, the third P-type region 253 can also be formed by the same lithography process steps as the first P-type region 251 and the second P-type region 252. Formed by ion implantation process steps; can also be formed by different lithography process steps and ion implantation process steps. The first P-type region 251, the second P-type region 252, and the third P-type region 253 have P-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under the upper surface of the N-type epitaxial layer and connected to the upper surface. surface. Please refer to FIG. 2A at the same time. The first P-type region 251 and the second P-type region 252 are viewed from the top view of FIG. 2A , for example, are ring-shaped closed regions, surrounding the first field oxide region 221 and the second field oxide region 222 respectively.

Next, as shown in FIG. 6F , the gate 261 and the gate 262 are formed. From the top view of FIG. 2A , the gate 261 and the gate 262 are, for example, ring-shaped enclosed areas. The gate 261 and the gate 262 are, for example but not limited to, formed simultaneously by the same gate process steps. Wherein, the gate 261 and the gate 262 include, for example, respective dielectric layers, conductive layers and spacer layers, which are well known to those skilled in the art, and here I won't go into details. Therefore, the gate process steps include process steps such as lithography and oxidation to form a dielectric layer; process steps such as lithography and deposition to form a conductive layer; and process steps such as deposition and etching to form a spacer layer.

Next, as shown in FIG. 6G, a first forward end 281, an emitter 282, a P-type contact pole 284, and a second forward end 285 are formed. For example, but not limited to, the same lithography process steps are used to simultaneously define the first The region of forward end 281, emitter 282, P-type contact electrode 284, and second forward end 285; and by the same ion implantation process steps, P-type impurities are implanted in the form of accelerated ions by the aforementioned The region defined by the lithography process steps to form the first forward end 281 , the emitter 282 , the P-type contact 284 and the second forward end 285 . The first forward end 281, the emitter 282, the P-type contact electrode 284, and the second forward end 285 have P-type conductivity and are respectively formed on the first forward end 281. A P-type region 251 , a second N-type extension region 242 , a second P-type region 252 and a third P-type region 253 are located under the upper surface of the N-type epitaxial layer and connected to the upper surface. Please refer to the top view FIG. 2A at the same time, the forward end 281, the P-type contact pole 284 and the second forward end 285 are seen from the upper view, for example, they are all annular closed areas, respectively surrounding the gate 261, the drain 272 and the fourth field oxide region 228 .

Next, as shown in FIG. 6H , the first reverse terminal 271 , the drain 272 and the second reverse terminal 273 are formed, for example but not limited to, by the same lithography process steps (including using the gate 262 as a mask), Simultaneously define the regions of the first reverse end 271, the drain electrode 272, and the second reverse end 273; and by the same ion implantation process steps, N-type impurities are implanted in the form of accelerated ions by the aforementioned micro The area defined by the shadow process steps is used to form the first reverse terminal 271 , the drain 272 and the second reverse terminal 273 . The first reverse end 271 , the drain 272 and the second reverse end 273 have N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under and connected to the upper surface of the N-type epitaxial layer. Please also refer to the top view FIG. 2A , the drain 272 is viewed from the top view, for example, it is a ring-shaped closed area surrounding the gate 262 .

The present invention has been described above with reference to preferred embodiments, but the above description is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, without affecting the main characteristics of the device, other process steps or structures, such as deep well regions, etc. can be added; as another example, the lithography process steps are not limited to the photomask process steps, and may also include electron beam lithography process steps. All these can be obtained by analogy according to the teaching of the present invention. In addition, each of the described embodiments is not limited to be used alone, and can also be used in combination, for example but not limited to using the two embodiments together. Therefore, the scope of the present invention shall cover the above-mentioned and All his equivalent changes. In addition, any implementation form of the present invention does not necessarily achieve all purposes or advantages, and therefore, any one of the claims should not be limited thereto.

200: power components

221: The first oxidation zone

222:Second Field Oxidation Area

223: the first insulating side wall

224: second insulating side wall

225: the third insulating side wall

226: The fourth insulating side wall

227: The third oxidation area

228: The fourth field oxidation area

231: The first N-type area

241: The first N-type extension region

242: Second N-type extension region

243: The third N-type extension

251: The first P-type area

252: Second P-type area

253: The third P-type area

261: Gate

262: Gate

271: The first reverse end

272: drain

273: The second reverse end

281: The first forward end

282: emitter

284: P-type contact pole

285: the second forward end

291: metal wire

BB': broken line

C: drain

E: Emitter

F: forward end

G: gate

LIGBT2: Lateral Insulated Gate Bipolar Transistor

PN2: PN diode

R: reverse end

ZD1: Zener diode

Claims (14)

A power element formed on a semiconductor substrate for driving a motor, comprising: a lateral insulated gate bipolar transistor (LIGBT); a PN diode connected to the lateral insulated gate The bipolar transistors are connected in parallel; and a clamping diode has a clamping forward terminal and a clamping reverse terminal, respectively electrically connected to a drain pole and a gate pole of the transverse insulated gate bipolar transistor , to limit a gate voltage applied to the gate not to be higher than a preset voltage threshold; wherein the PN diode includes: a first N-type region formed in an epitaxial layer on the semiconductor substrate; a first P-type region formed in the first N-type region; a first N-type extension region formed in the first N-type region, and the first N-type extension region and the first P-type region separated by the first N-type region; a first reverse end, having N-type conductivity, formed in the first N-type extension region, and used as an electrical contact of the first N-type extension region; And a first forward end, having P-type conductivity, formed in the first P-type region, used as an electrical contact of the first P-type region. The power device as claimed in claim 1, wherein the lateral insulated gate bipolar transistor comprises: a second N-type region formed in the epitaxial layer on the semiconductor substrate; a second P-type region formed In the second N-type region; the drain, having N-type conductivity, is formed in the second P-type region; A P-type contact electrode is formed in the second P-type region as an electrical contact of the second P-type region; the gate is formed on the epitaxial layer, and part of the gate is connected to the Above the second P-type region; a second N-type extension region is formed in the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region and an emitter, with P-type conductivity, formed in the second N-type extension region. The power device as claimed in claim 2, wherein the clamping diode system is a Zener diode, which includes: a third P-type region formed in the epitaxial layer on the semiconductor substrate; a second sequential To the end, with P-type conductivity, formed in the third P-type region, used as the forward end of the clamp, and the electrical contact of the third P-type region; a third N-type extension region, formed in the third P-type region; and a second reverse end, having N-type conductivity, formed in the third N-type extension region, used as the clamping reverse end, and the third N-type The electrical contact of the type extension area. The power device as described in claim 3, wherein the Zener diode further includes an N-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the N-type adjustment region is on the upper surface Between the third P-type region and the third N-type extension region on the surface, it is used to adjust the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region. The power device as described in claim 3, wherein the Zener diode further includes a P-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the P-type adjustment region is on the upper surface Between the third P-type region and the third N-type extension region on the surface, it is used to adjust the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region. The power device according to any one of claims 4 or 5, wherein the zener diode further includes an electrostatic discharge (ESD) protection zone having N-type conductivity formed in the epitaxial layer The upper surface is below and connected to the upper surface, and the electrostatic protection area is on the upper surface between the third N-type extension area and the second forward end, and the electrostatic protection area is used to communicate with the third P-type area And the third N-type extension region forms an NPN transistor, wherein the electrostatic protection region is electrically connected to the second forward end. The power device as claimed in claim 3, wherein the first N-type extension region, the second N-type extension region, and the third N-type extension region are simultaneously formed by the same lithography process step and ion implantation process step; Wherein the first P-type region and the second P-type region are simultaneously formed by the same lithography process steps and ion implantation process steps; wherein the first reverse end, the drain and the second reverse end are formed by the same The lithography process step and the ion implantation process step are formed simultaneously; wherein the first forward end, the emitter, the P-type contact pole and the second forward end are formed by the same lithography process step and ion implantation The process steps are formed simultaneously. A method of manufacturing a power element, wherein the power element is formed on a semiconductor substrate for driving a motor, the method of manufacturing the power element includes: forming a lateral insulated gate bipolar transistor (lateral insulated gate bipolar transistor, LIGBT); forming a PN diode in parallel with the lateral insulated gate bipolar transistor; and A clamping diode is formed, which has a clamping forward end and a clamping reverse end, respectively electrically connected to a drain and a gate of the lateral insulated gate bipolar transistor, so as to limit the A gate voltage of the gate is not higher than a preset voltage threshold; wherein the step of forming the PN diode includes: forming a first N-type region in an epitaxial layer on the semiconductor substrate; forming a first A P-type region is in the first N-type region; a first N-type extension region is formed in the first N-type region, and the first N-type extension region and the first P-type region are formed by the first N-type region type region; forming a first reverse end in the first N-type extension region, the first reverse end has N-type conductivity, and is used as an electrical contact of the first N-type extension region; And forming a first forward end in the first P-type region, the first forward end has P-type conductivity, and is used as an electrical contact of the first P-type region. The power device manufacturing method as described in Claim 8, wherein the step of forming the lateral insulated gate bipolar transistor includes: forming a second N-type region in the epitaxial layer on the semiconductor substrate; forming a first Two P-type regions are in the epitaxial layer; the drain with N-type conductivity is formed in the second P-type region; the drain is formed in the second P-type region, and the drain has N-type conductivity type; form a P-type contact pole in the second P-type region as the electrical contact of the second P-type region; form the gate electrode on the epitaxial layer, wherein part of the gate electrode is connected to the On the second P-type region; forming a second N-type extension region in the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region; And forming an emitter with P-type conductivity in the second N-type extension region. The power device manufacturing method as described in claim 9, wherein the clamping diode is a Zener diode, and the step of forming the clamping diode includes: forming a third P-type region on the semiconductor substrate In the epitaxial layer; form a second forward end in the third P-type region, the second forward end has P-type conductivity, and is used as the clamp forward end, and the third P The electrical contact of the type region; forming a third N-type extension region in the third P-type region; and forming a second reverse end in the third N-type extension region, the second reverse end has The N-type conductive type is used as the electrical contact between the clamping reverse end and the third N-type extension region. According to the power device manufacturing method described in Claim 10, the step of forming the clamping diode further includes: forming an N-type adjustment region under the upper surface of the epitaxial layer and connected to the upper surface, and the N-type The adjustment region is located between the third P-type region and the third N-type extension region on the upper surface, and is used to adjust the PN junction formed by the third P-type region and the third N-type extension region. forward voltage. According to the power device manufacturing method described in Claim 10, the step of forming the clamping diode further includes: forming a P-type adjustment region under the upper surface of the epitaxial layer and connected to the upper surface, and the P-type The adjustment region is located between the third P-type region and the third N-type extension region on the upper surface, and is used to adjust the PN junction formed by the third P-type region and the third N-type extension region. forward voltage. The method for manufacturing a power device as described in any one of claims 11 or 12, wherein the step of forming the clamping diode further includes: forming an electrostatic discharge (ESD) protection zone having an N-type conductivity in the In the epitaxial layer, the upper surface is below and connected to the upper surface, and the electrostatic protection area is on the upper surface between the third N-type extension area and the second forward end, and the electrostatic protection area is used to communicate with the second forward end. The third P-type region and the third N-type extension region form an NPN transistor, wherein the electrostatic protection region is electrically connected to the second forward end. The power device manufacturing method as described in Claim 10, wherein the first N-type extension region, the second N-type extension region, and the third N-type extension region are performed simultaneously by the same lithography process step and ion implantation process step Formed; wherein the first P-type region and the second P-type region are simultaneously formed by the same lithography process step and ion implantation process step; wherein the first reverse end, the drain and the second reverse end Formed simultaneously by the same lithography process steps and ion implantation process steps; wherein the first forward end, the emitter, the P-type contact pole and the second forward end are formed by the same lithography process steps and ion implantation process steps The implant process steps are formed simultaneously.

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