CN107170816B - A kind of landscape insulation bar double-pole-type transistor - Google Patents
A kind of landscape insulation bar double-pole-type transistor Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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Abstract
The invention belongs to semiconductor power device technology fields, particularly relate to a kind of landscape insulation bar double-pole-type transistor.The present invention is by forming three-dimensional structure along orientation etching groove in device surface, forming the landscape insulation bar double-pole-type transistor with three-dimensional structure on the basis of traditional landscape insulation bar double-pole-type transistor；Polycrystalline diode is formed on device three-dimensional drift region surface simultaneously and three-dimensional PMOS and Zener diode are integrated near collector.Structure of the invention has forward conduction voltage drop more lower than traditional LIGBT and negative resistance phenomenon is not present in turn on process, while having higher device electric breakdown strength, faster turn-off speed and lower turn-off power loss.
Description
Technical field
The invention belongs to semiconductor power device technology fields, and it is brilliant to particularly relate to a kind of landscape insulation bar double-pole-type
Body pipe.
Background technique
Insulated gate bipolar transistor (IGBT) is a kind of MOS field-effect and the compound novel electric power electricity of bipolar junction transistor
Sub- device, its existing MOSFET are easy to drive, and control simple advantage, and have power transistor turns pressure drop low, on state current
Greatly, small advantage is lost, it has also become the mainstream device for power switching of middle high power field of power electronics is widely used in such as logical
The every field of the national economy such as letter, the energy, traffic, industry, medicine, household electrical appliance and aerospace.International well-known semiconductor
Company, such as ABB, Infineon (IR), ST, Renesas, Mitsubishi, FuJi etc. put into the research and development and system of IGBT in succession
In making.In recent years, as the hot fields of power electronics, IGBT is more that of obtaining the developed countries such as the U.S., Japan and Europe
With the great attention in area.
In turn on process, electronics enters in N-type drift region by MOS channel IGBT, so as to cause p-type collecting zone to drift
It moves area and injects a large amount of hole.Therefore, it is stored with a large amount of excess electron-hole pair in the drift region IGBT in ON state, this
A little electron-hole pairs form conductivity modulation effect, drift zone resistance are significantly reduced, to reduce forward conduction voltage drop VCE.
In practical application, to reduce ON state loss, it is always desirable to which the lower VCE the better.But VCE is lower to mean that conductivity modulation effect is stronger
Strong, superfluous electron-hole pair is more in drift region, these a large amount of electron-hole pairs needed in IGBT turn off process by
It all extracts and compound, so as to cause turn-off power loss EOFF increase.VCE and EOFF is one group of important tradeoff of IGBT,
It is directly related to the size of ON state loss and turn-off power loss.The change of the every generation product of IGBT, wherein all comprising to the compromise
The optimization of relationship.
Currently, silicon on insulating layer (SOI) technology is widely used in lateral power, to reduce parasitic capacitance, inhibit substrate
Latch-up caused by electric current, elimination substrate etc..Its typical preparation process includes that SIMOX technology, bonding techniques is isolated in note oxygen
And Smart-Cut technology etc..Transversal I GBT (LIGBT) is since grid driving power is small, current handling capability is strong, is easily integrated
Advantage is widely used in power and integrates in IC (PICs) and intelligent power IC, and basic structure is as shown in Figure 1.Due to shutdown
Process needs to extract the excess carriers in drift region, causes its turn-off time longer, and turn-off power loss is larger, limits LIGBT
Application in high frequency field.For the VCE-EOFF tradeoff for improving LIGBT, most efficient method is increased in turn off process
Electronics extracts access, and to reduce the fall time of electric current, typical structure is anode in short circuit (SA-LIGBT) structure, as shown in Figure 2.
However, the structure, in forward conduction, electronics passes through N+ emitter region 5, the surface channel in the area PXing Ti 4, low-doped n type drift region
3, the arrival of the area collector N+ 8 collector forms parasitic MOS structure, generates electronic current access, and it is negative to will lead to conducting curve presentation
Phenomenon is hindered, and weakens the conductivity modulation effect of drift region, increases forward conduction voltage drop, is unfavorable for the practical application of device.
Summary of the invention
The purpose of the present invention is to provide a kind of low-loss landscape insulation bar double-pole-type transistors of high speed.Structure of the invention
By being formed in device surface along orientation etching groove on the basis of traditional landscape insulation bar double-pole-type transistor
Three-dimensional structure forms the landscape insulation bar double-pole-type transistor with three-dimensional structure；It is formed on device three-dimensional drift region surface more
Brilliant diode simultaneously integrates three-dimensional PMOS and Zener diode near collector.In the bar state, pass through device surface three-dimensional
Drift region exhausts the charge of offer under polycrystalline diode reverse-biased and three-dimensional field plate acts on, and is improving the device drift region LIGBT
It can get pressure resistance more higher than traditional LIGBT structure while doping concentration；In device turn off process, with collector voltage
Increase, make to collect using the automatic biasing effect that the variation of collector voltage and surface polycrystalline diode and Zener diode are formed
PMOS near electrode is automatically turned on and is connected, and is formed electronic current access in collector terminal, is accelerated the carrier inside LIGBT
It extracts, while three-dimensional polycrystalline diode drift region exhausts the charge of offer and three-dimensional field plate acts on faster devices drift region depletion layer
In the extension perpendicular to orientation, the carrier for further speeding up LIGBT device inside is extracted, to improve device
Turn-off speed further decreases the turn-off power loss of device；In the on-state, collector voltage is lower, surface polycrystalline diode
The automatic biasing effect formed with Zener diode (or diode string) keeps the PMOS near collector in an off state, electronics electricity
Logical circulation road is truncated, and the presence of additional structure will not influence the forward conduction characteristic of device, and negative resistance is not present in turn on process
Phenomenon, while three-dimensional three grid structures increase the equivalent width of grid structure, further reduce the forward conduction voltage drop of device.Cause
This, structure of the invention has forward conduction voltage drop more lower than traditional LIGBT and negative resistance phenomenon is not present in turn on process, together
When have higher device electric breakdown strength, faster turn-off speed and lower turn-off power loss.Structure of the invention is applicable not only to N
Type LIGBT device is also applied for p-type LIGBT device, it is only necessary to which the doping type of material in structure is carried out to the exchange of N and P.For
Description is convenient following only to be illustrated by taking N-type LIGBT device as an example.
The technical scheme is that as shown in figure 3, a kind of landscape insulation bar double-pole-type transistor, half structure cell
Including the substrate 1, insulating layer 2 and the first N-type doped regions 3 being cascading from bottom to up；It is characterized in that, vertical along device
To direction, first N-type doped regions 3 are that second level is ladder-like, and the vertical height for defining second level ladder is greater than first order rank
Ladder, first N-type doped regions, 3 upper layer two sides are respectively provided with the area PXing Ti 4 and N-type buffer area 7, along device longitudinal direction, institute
The area ShuPXing Ti 4 and N-type buffer area 7 are that second level is ladder-like；In the first N-type doped regions 3 second level ladder and the area PXing Ti 4 and
There are the second N-type doped regions 150 between 7 second level ladder of N-type buffer area；4 upper layer of the area PXing Ti, which has to be mutually juxtaposed, to be set
The contact zone P+ 6 and N+ emitter region 5 set, wherein N+ emitter region 5 is located at close to the side of N-type buffer area 7, the contact zone P+ 6
It is that second level is ladder-like with N+ emitter region 5；The contact zone P+ 6 and 5 upper surface of part N+ emitter region have emitter metal electricity
Pole 130, the emitter metal electrode 130 are that second level is ladder-like；4 upper surface of the area PXing Ti has first grid structure, institute
State first polygate electrodes of the first grid structure by the first gate dielectric layer 110 and positioned at 110 upper surface of the first gate dielectric layer
120 constitute, along device longitudinal direction, the lower surface of first gate dielectric layer 110 successively with the first N-type doped regions 3 first
The upper surface and side contact of the upper surface of ladder and the second N-type doped regions 150, the lower surface of the first gate dielectric layer 110 is also
It is contacted with the upper surface of part N+ emitter region 5, the upper surface of the first polygate electrodes 120 is that horizontal plane or second level are ladder-like；
There is p-type collecting zone 8, the highly doped area N+ 9 and the highly doped area P+ 10, the highly doped area N+ 9 and highly doped P in the N-type buffer area 7
+ area 10 contacts with each other and the highly doped area N+ 9 is located at close to the side in the area PXing Ti 4；The p-type collecting zone 8, highly doped 9 and of the area N+
The highly doped area P+ 10 is that second level is ladder-like；8 upper surface of p-type collecting zone has collector electrode metal far from 4 side of the area PXing Ti
Electrode 131, the collector electrode metal electrode 131 are that second level is ladder-like；The upper table in the highly doped area N+ 9 and the highly doped area P+ 10
Face has metal electrode 132, and the metal electrode 132 is that second level is ladder-like；The upper surface of the N-type buffer area 7 has second
Gate structure, the second grid structure is by the second gate dielectric layer 111 and positioned at more than the second of 111 upper surface of the second gate dielectric layer
Crystal silicon electrode 124 is constituted, and along device longitudinal direction, the lower surface of second gate dielectric layer 111 is successively low-doped with the first N-type
The upper surface of 3 first ladder of area and the upper surface of the second N-type doped regions 150 and side contact, under the second gate dielectric layer 111
Surface is also contacted with the upper surface of part p-type collecting zone 8 and the highly doped area P+ 10, and the upper surface of the second polysilicon electrode 124 is
Horizontal plane or second level are ladder-like；Device upper surface between the area PXing Ti 4 and N-type buffer area 7 has dielectric layer 112, edge
Device longitudinal direction, the lower surface of the dielectric layer 112 successively with the upper surface of 3 first ladder of the first N-type doped regions and
The upper surface of two N-type doped regions 150 contacts, upper surface of the lower surface of the dielectric layer 112 also with part N-type buffer area 7
Contact；112 upper surface of dielectric layer has the area polysilicon P+ 121, p type island region 122 and the area N+ 123, and wherein p type island region 122 is located at
Between the area polysilicon P+ 121 and the area N+ 123 and it is interconnected to form polysilicon diode, the area P+ 121 is located at close to the area PXing Ti 4
Side, the area N+ 123 is located at close to 7 side of N-type buffer area, along device longitudinal direction, the area polysilicon P+ 121, p type island region 122 and N
The upper surface in+area 123 is that horizontal plane or second level are ladder-like；It is electric between the emitter metal electrode 130 and the area polysilicon P+ 121
Gas connection, electrical connection and the area the polysilicon N+ 123 between the area 123 the polysilicon N+ and the second polysilicon electrode 124
Pass through with the second polysilicon electrode 124 and be electrically connected between Zener diode 140 and collector electrode metal 131, wherein two pole of Zener
The cathode of pipe 140 connects collector electrode metal 131, and the anode of Zener diode 140 connects the area 123 polysilicon N+ and the second polysilicon electrode
124。
Above scheme is the total technical solution of the present invention, and device longitudinal direction described in above scheme is corresponding such as institute in figure
Show that the Y direction in three-dimensional cartesian coordinate system, device transverse direction correspond to X-direction, in device top view, X-axis and Y-axis exist
It same level and is mutually perpendicular to, device vertical direction corresponds to Z-direction.
Further, the doping concentration of second N-type doped regions 150 is equal to or more than the first N-type doped regions 3
Doping concentration.
Further, the Zener diode is integrated in close 131 side of collector electrode metal electrode in 112 top of dielectric layer,
Corresponding collector electrode metal electrode 131, which is extended to, contacts simultaneously covering part Zener diode upper surface with 112 side of dielectric layer.
Further, for the Zener diode as replaced multiple concatenated diodes, the anode of diode string connects current collection
Pole metal 131, cathode connects the highly doped area N+ 123 of polysilicon and polysilicon electrode 124, and the cut-in voltage value of diode string is big
In the threshold voltage absolute value of PMOS.
Further, in above scheme, as shown in figure 11, between the area the polysilicon P+ 121 and the area polysilicon N+ 123 also
With capacitor 151.By between polysilicon electrode 124 and emitter metal electrode 130 when the capacitor can pass through surface wiring
The parasitic capacitance of formation is formed, can also be by the low-doped drift region 3 of N-type or the polysilicon layer and/or metal layer of surface wiring
In formed by integrated capacitance.
In the solution of the present invention, polysilicon p area 122 can also use n type material；Gate dielectric layer 110, dielectric layer
111 and the thickness and material of dielectric layer 112 can be the same or different, material used can be silica (SiO2),
It is also possible to aluminum oxide (Al2O3), hafnium oxide (HfO2) or silicon nitride (Si3N4) etc. hafniums；It is partly led used in device
Body material can be used silicon (Si), silicon carbide (SiC), GaAs (GaAs) or gallium nitride (GaN) etc. and be achieved.
The beneficial effects of the present invention are: in the on-state, structure of the invention is pressed with conducting more lower than traditional LIGBT
It drops and negative resistance phenomenon is not present in turn on process；In the bar state, there is higher breakdown voltage；It was turning off simultaneously
Cheng Zhong has faster turn-off speed and lower turn-off power loss.
Detailed description of the invention
Fig. 1 is traditional landscape insulation bar double-pole-type transistor schematic diagram；
Fig. 2 is traditional anode in short circuit landscape insulation bar double-pole-type transistor schematic diagram；
Fig. 3 is the half cellular three dimensional structure diagram of transistor of embodiment 1；
Fig. 4 is diagrammatic cross-section of Fig. 3 structure along AA ' line；
Fig. 5 is diagrammatic cross-section of Fig. 3 structure along BB ' line；
Fig. 6 is diagrammatic cross-section of Fig. 3 structure along CC ' line；
Fig. 7 is that Fig. 3 structure is illustrated along the section of DD ' line；.
Fig. 8 is diagrammatic cross-section of Fig. 3 structure along EE ' line；
Fig. 9 is 2 transistor of embodiment, half cellular three dimensional structure diagram；
Figure 10 is 3 transistor of embodiment, half cellular three dimensional structure diagram；
Figure 11 is 4 transistor of embodiment, half cellular three dimensional structure diagram；
Figure 12 is 5 preparation method of transistor typical process flow figure of embodiment；
It is low that Figure 13 is that a kind of landscape insulation bar double-pole-type transistor production method provided by the invention is epitaxially-formed N-type
Structural schematic diagram after 150 layers of doped region；
Figure 14 is that a kind of landscape insulation bar double-pole-type transistor production method provided by the invention passes through etching technics in device
Part surface forms the structural schematic diagram after groove in X direction；
Figure 15 is that a kind of landscape insulation bar double-pole-type transistor production method provided by the invention is formed with foldable structure
N-type buffer layer 7 after structural schematic diagram；
Figure 16 is that a kind of landscape insulation bar double-pole-type transistor production method provided by the invention forms dielectric layer and polycrystalline
Structural schematic diagram after silicon layer；
Figure 17 is that a kind of landscape insulation bar double-pole-type transistor production method provided by the invention completes each area's ion implanting
With the structural schematic diagram after annealing；
Figure 18 is after a kind of landscape insulation bar double-pole-type transistor production method provided by the invention completes metal interconnection
Structural schematic diagram；
In Fig. 1-Figure 17: 1 be P type substrate, 2 be buries oxide layer, 3 be low-doped n type area, 4 be the area PXing Ti, 5 be N+ transmitting
Area, 6 for the highly doped area P+, 7 be N-type buffer layer, 8 be p-type collecting zone, 9 be the highly doped area N+, 10 be p type island region, 110 be grid be situated between
Matter floor, 111 be first medium floor, 112 be second dielectric layer, 120 be gate electrode, 121 be the area polysilicon P+, 122 be polysilicon P
Type area, 123 be the area polysilicon N+, 124 be polysilicon electrode, 125 areas polysilicon P+, 126 be the area polysilicon N+, 130 be transmitting
Pole metal electrode, 131 be collector electrode metal electrode, 132 be the first metal electrode, 140 be Zener diode, and 150 be low-doped N
Type area, 151 be capacitor.
Specific embodiment
The present invention is described in detail below with reference to the accompanying drawings and embodiments.
Embodiment 1
As shown in figure 3, being the structural schematic diagram of this example, half structure cell includes the lining being cascading from bottom to up
Bottom 1, insulating layer 2 and the first N-type doped regions 3；It is characterized in that, along device longitudinal direction, first N-type doped regions 3
Ladder-like for second level, the vertical height for defining second level ladder is greater than first order ladder, first N-type doped regions, 3 upper layer
Two sides are respectively provided with the area PXing Ti 4 and N-type buffer area 7, and along device longitudinal direction, the area PXing Ti 4 and N-type buffer area 7 are
Second level is ladder-like；Have between 3 second level ladder of the first N-type doped regions and the area PXing Ti 4 and 7 second level ladder of N-type buffer area
There are the second N-type doped regions 150；4 upper layer of the area PXing Ti has the contact zone P+ 6 and N+ emitter region 5 for being mutually juxtaposed setting,
Wherein N+ emitter region 5 is located at close to the side of N-type buffer area 7, and the contact zone P+ 6 and N+ emitter region 5 are that second level is ladder-like；
The contact zone P+ 6 and 5 upper surface of part N+ emitter region have emitter metal electrode 130, the emitter metal electrode 130
It is ladder-like for second level；4 upper surface of the area PXing Ti has first grid structure, and the first grid structure is by the first gate medium
Layer 110 and positioned at 110 upper surface of the first gate dielectric layer the first polygate electrodes 120 constitute, it is described along device longitudinal direction
The lower surface of first gate dielectric layer 110 is successively low-doped with the upper surface of 3 first ladder of the first N-type doped regions and the second N-type
The upper surface in area 150 contacts, and the lower surface of the first gate dielectric layer 110 is also contacted with the upper surface of part N+ emitter region 5, more than first
The upper surface of crystal silicon gate electrode 120 is horizontal plane；There is p-type collecting zone 8, the highly doped area N+ 9 and height in the N-type buffer area 7
The area P+ 10 is adulterated, the highly doped area N+ 9 and the highly doped area P+ 10 contact with each other and the highly doped area N+ 9 is located at one close to the area PXing Ti 4
Side；The p-type collecting zone 8, the highly doped area N+ 9 and the highly doped area P+ 10 are that second level is ladder-like；Table on the p-type collecting zone 8
Face has collector electrode metal electrode 131 far from 4 side of the area PXing Ti, and the collector electrode metal electrode 131 is that second level is ladder-like；Institute
The upper surface for stating the highly doped area N+ 9 and the highly doped area P+ 10 has metal electrode 132, and the metal electrode 132 is second level ladder
Shape；The upper surface of the N-type buffer area 7 has second grid structure, and the second grid structure is by 111 He of the second gate dielectric layer
The second polysilicon electrode 124 positioned at 111 upper surface of the second gate dielectric layer is constituted, and along device longitudinal direction, the second gate is situated between
The lower surface of matter layer 111 is successively upper with the upper surface of 3 first ladder of the first N-type doped regions and the second N-type doped regions 150
Surface contact, the lower surface of the second gate dielectric layer 111 are also contacted with the upper surface of part p-type collecting zone 8 and the highly doped area P+ 10,
The upper surface of second polysilicon electrode 124 is horizontal plane；Device upper surface between the area PXing Ti 4 and N-type buffer area 7
With dielectric layer 112, along device longitudinal direction, the lower surface of the dielectric layer 112 successively with the first N-type doped regions 3 first
The upper surface of the upper surface of ladder and the second N-type doped regions 150 contact, the lower surface of the dielectric layer 112 also with part N-type
The upper surface of buffer area 7 contacts；112 upper surface of dielectric layer has the area polysilicon P+ 121, p type island region 122 and the area N+ 123,
Middle p type island region 122 is located between the area polysilicon P+ 121 and the area N+ 123 and is interconnected to form polysilicon diode, 121, the area P+
In the side close to the area PXing Ti 4, the area N+ 123 is located at close to 7 side of N-type buffer area, along device longitudinal direction, the area polysilicon P+
121, the upper surface in p type island region 122 and the area N+ 123 is horizontal plane；The emitter metal electrode 130 and the area polysilicon P+ 121 it
Between be electrically connected, between the area 123 the polysilicon N+ and the second polysilicon electrode 124 electrical connection and the area the polysilicon N+
123 and second polysilicon electrode 124 by being electrically connected between Zener diode 140 and collector electrode metal 131, wherein Zener two
The cathode of pole pipe 140 connects collector electrode metal 131, and the anode of Zener diode 140 meets the area 123 polysilicon N+ and the second polysilicon electricity
Pole 124.
In this example, the doping concentration of the N-type doped regions 150 is equal to or more than the doping concentration of N-type doped regions 3；
The depth of the groove formed is greater than the width of the groove；The depth of the groove formed is greater than between the groove
Device surface width；The low-doped drift region 3/150 of the N-type and the fully- depleted before device breakdown of polysilicon p area 122；Institute
The spacing in polygate electrodes 120 and the area polysilicon P+ 121 is stated less than 1 micron, the area the polysilicon P+ 121 and the area N+ 123
Width is less than 1 micron, and the spacing of the area the polysilicon N+ 123 and metal electrode 132 is less than 1 micron；By adjusting dielectric layer 111
Thickness and lower 7 surface of N-type buffer layer of material and dielectric layer 111 concentration, the area Shi You N+ 9, the area P+ 10, dielectric layer 111,
The threshold voltage for the PMOS device that polysilicon electrode 124, p-type collecting zone 8 and N-type buffer layer 7 are formed is -2V-0V；It is described neat
Receive diode 140 and structure of the invention other parts it is integrated on the same chip, pass through the parameter for adjusting Zener diode 140
Make the pressure stabilizing value 2V-5V of Zener diode.
The working principle of this example are as follows:
In the bar state, emitter metal electrode 130 and gate electrode 120 are grounded in this example, collector electrode metal electrode 131
Meet high voltage Vc.At this point, in device three-dimensional fold surface by Zener diode 140 and by the area P+ 121, p type island region 122 and the area N+
On the collector to emitter branch that the polycrystalline diode of 123 compositions is formed, Zener diode breakdown is in pressure stabilizing state, Zener
Diode anode side voltage keeps Vc-Vz constant (Vz is Zener diode pressure stabilizing value).Due to the pressure stabilizing value Vz of Zener diode
It is lower, therefore collector voltage is mainly undertaken by polycrystalline diode, the low-doped area P 122 of polycrystalline diode exhaust after for negative electricity
Lotus；Meanwhile under the polycrystalline diode with foldable structure in N-type doped regions 3/150, due to the low-doped area N 3/150 and P
The PN junction that the area Xing Ti 4 is formed is reverse-biased, and since the area PXing Ti 4 and 7 concentration of N-type buffer layer are much higher than the low-doped area N 3/150, because
This pressure resistance is mainly undertaken by the low-doped area N 3/150, the low-doped area N 3/150 exhaust after for positive charge；At this point, the low-doped area P 122
Positive charge after negative electrical charge after exhausting exhausts the low-doped area N 3/150 forms charge compensation, therefore low with foldable structure
The doping area P 122 is that the low-doped area N 3/150 provides additional charge, three-dimensional multi-field plate and the effect for reducing surface field.Pass through
Make polysilicon p area 122, the low-doped area N 3 and the low-doped fully- depleted before device breakdown of the area N 150, this hair can be greatly improved
The breakdown voltage of bright LIGBT and the doping concentration for improving the low-doped area N 3 and the low-doped area N 150.Further, since polysilicon electrode
124 are connected with Zener diode 140, by the area N+ 9, p type island region 10, dielectric layer 111, polysilicon electrode 124, p-type collecting zone 8 and
The gate source voltage for the PMOS that N-type buffer layer 7 is formed keeps Vz value, and the threshold voltage by adjusting PMOS makes the steady of Zener diode
Pressure value is greater than the threshold voltage absolute value of PMOS, and PMOS is opened at this time, and the area heavy doping N+ 9 passes through metal electrode 132 and PMOS and P
Type collecting zone 8 is connected, and passes through the conversion of metal electrode 132 electronic current and hole current between the area N+ 9 and p type island region 10, shape
At anode in short circuit structure, the triode that 8/ low-doped n type drift region 3 of p-type collecting zone and the area 150/P Xing Ti 4 are formed is reduced
Gain, to further improve the breakdown voltage of device；
In the on-state, emitter metal electrode 130 is grounded in this example, gate electrode 120 and collector electrode metal electrode 131
High level is connect, 4 surface transoid MOS channel of the area PXing Ti is opened at this time, and N+ emitter region 5 injects electronics into low-doped drift region 3,
P-type collecting zone 8 injects hole, insulated gate bipolar transistor conducting into low-doped drift region 3 simultaneously.At this point, in device table
Face passes through on the collector to emitter branch that Zener diode 140 and polycrystalline diode are formed, polycrystalline diode and Zener two
Pole pipe is respectively formed reverse-biased, simultaneously because collector voltage is lower, Zener diode 140 cannot puncture, 124 sum aggregate of polysilicon electrode
The PMOS gate source voltage formed between electrode metal electrode 131 is lower than PMOS threshold voltage, and PMOS is in an off state, the area N+ 9
It is in an off state with p-type collecting zone 8, the presence of additional structure will not influence the forward conduction characteristic of device, i.e., horizontal with tradition
Negative resistance phenomenon is equally not present to insulated gate bipolar transistor.The introducing of three-dimensional three grid structures simultaneously increase grid structure etc.
Width is imitated, the forward conduction voltage drop of device is further reduced.Therefore, structure of the invention have it is more lower than traditional LIGBT just
Negative resistance phenomenon is not present to conduction voltage drop and in turn on process.
In turn off process, emitter metal electrode 130 is grounded in this example, and 120 voltage of gate electrode is gradually dropped by high level
Low, 4 surface MOS channel cutoff of the area PXing Ti, 131 voltage of collector electrode metal electrode gradually increases.With collector electrode metal electrode
The increase of 131 voltages passes through Zener diode in device surface when collector voltage is lower than zener diode breakdown voltage Vz
140 and polycrystalline diode formed collector to emitter branch on, Zener diode does not puncture, at this point, PMOS gate source voltage
Lower than its threshold voltage, PMOS is in an off state.After collector voltage is higher than zener diode breakdown voltage Vz, Zener two
Pole pipe breakdown, polycrystalline diode starts to undertake voltage, and PMOS gate source voltage stabilizes to that Vz is constant at this time, passes through and adjusts PMOS's
Threshold voltage makes the pressure stabilizing value of Zener diode be greater than the threshold voltage absolute value of PMOS, and PMOS is opened and is connected at this time, heavily doped
The miscellaneous area N+ 9 is connected by metal electrode 132 and PMOS with p-type collecting zone 8, by metal electrode 132 in the area N+ 9 and p type island region 10
Between electronic current and hole current conversion, formed anode in short circuit structure, at this point, the electronics in drift region is by the highly doped area N+
9 extract and are converted to transoid of the hole current through PMOS drain electrode p type island region 10,111 lower section of gate dielectric layer by metal electrode 132
Floor, the area pmos source P+ 8 finally reach collector electrode metal 131.The process completes electronics in low-doped n type drift region 3/150
Extraction reduce turn-off power loss to substantially increase the turn-off speed of LIGBT.Meanwhile in turn off process, work as current collection
After pole tension is higher than zener diode breakdown voltage Vz, Zener diode breakdown, polycrystalline diode starts to undertake voltage, polycrystalline two
Pole pipe drift region 122 starts to exhaust, and polycrystalline diode drift region exhausts the charge of offer and field plate effect accelerates device drift
Area's depletion layer is along X-axis in the Longitudinal Extension of YZ plane, and the carrier for further speeding up LIGBT device inside extracts, to improve
The turn-off speed of device further decreases the turn-off power loss of device.In addition, high 3/150 doping concentration of low-doped drift region
Using the concentration for the excess carriers that need to be extracted is further reduced, the turn-off speed of device is further improved, device is reduced
The turn-off power loss of part.
Embodiment 2
As shown in figure 9, unlike embodiment 1,
Zener diode is directly formed in the polysilicon layer above dielectric layer 112, the Zener diode is formed in ditch
On device surface between slot, the area P+ 125 is the anode of Zener diode, and the area N+ 126 is the cathode of Zener diode.It is described neat
Receiving the type of diode, location and shape can be adjusted as needed.
Embodiment 3
As shown in Figure 10, it unlike embodiment 1, is directly formed in the polysilicon layer above dielectric layer 111 neat
Receive diode, the Zener diode is formed on the device surface between groove, and the area P+ 125 is the anode of Zener diode, N
+ area 126 is the cathode of Zener diode.Type, the location and shape of the Zener diode can be adjusted as needed.
Embodiment 4
On the basis of the above embodiments, Zener diode is as replaced multiple concatenated diodes, the sun of diode string
Pole connects collector electrode metal 131, and cathode connects the highly doped area N+ 123 of polysilicon and polysilicon electrode 124, and the unlatching of diode string
Voltage value is greater than the threshold voltage absolute value of PMOS.
Embodiment 5
As shown in figure 11, as different from Example 3, in the area the polysilicon P+ 121 and the area polysilicon N+ 123 in this example
Between also have capacitor 151；The capacitance of the capacitor 151 is less than by the area N+ 9, the area P+ 10, dielectric layer 111, polysilicon electrode
124, the gate capacitance value for the PMOS that p-type collecting zone 8 and N-type buffer layer 7 are formed.When the capacitor can pass through surface wiring
It is formed by the parasitic capacitance formed between polysilicon electrode 124 and emitter metal electrode 130, it can also be by low-doped in N-type
It is formed in drift region 3 or in the metal layer and/or polycrystal layer of surface wiring by integrated capacitance.It improves compared with Example 3 pair
The control of 124 voltage of polysilicon electrode, further improves the performance of device.
The present invention also provides a kind of landscape insulation bar double-pole-type transistor production method, typical process flow such as Figure 12 institute
Show, by taking 200V N-type landscape insulation bar double-pole-type transistor structure as an example, illustrates its specific process step.It is characterized in that, main
Want the following steps are included:
Step 1: choosing suitable SOI material, material includes with a thickness of 300~500 microns, and concentration is 10~100 Ω
The p-type semiconductor material substrate 1 of cm, with a thickness of 0.5~1 micron of buries oxide layer 2, with a thickness of 5~10um, resistivity be 5~
The low-doped silicon layer 3 of the N-type of 10 Ω cm；
Step 2: passing through the N-type doped regions for being epitaxially-formed 5~10 microns of thickness, resistivity is 3~10 Ω cm
150 layers, as shown in figure 13；
Step 3: forming groove in X direction in device surface by etching technics, the depth of groove is 5~10 microns, wide
Degree is 1~2 micron, and the width between groove is 1~2 micron, and the lower surface of groove is contacted in X/Y plane and N-type doped regions 3,
The side of groove is contacted in XZ plane with the low-doped drift region 3 of N-type and N-type doped regions 150, as shown in figure 14；
Step 4: forming the N-type with foldable structure in device surface side by photoetching, ion implanting and annealing process
Buffer layer 7, N-type buffer layer 7 with a thickness of 1~3um, as shown in figure 15；
Step 5: growth gate oxide, progress polycrystalline silicon deposit and photoetching, etching form gate oxide 110, the grid of device
Polycrystal layer on electrode 120, dielectric layer 111, polysilicon electrode 124, dielectric layer 112 and dielectric layer 112, polycrystalline silicon deposit mistake
(for obtaining the doping in polysilicon p area 122) is adulterated using p-type in situ in journey, oxide layer with a thickness of 50~100 nanometers,
Polycrystal layer with a thickness of 0.5~1um, polycrystal layer is p-type doping, doping concentration 1015~1016cm-3, as shown in figure 16；
Step 6: carrying out the photoetching of the area PXing Ti and P-type ion injection, annealing, the area PXing Ti 4, the thickness in the area PXing Ti 4 are formed
For 1~3um；
Step 7: progress N+ photoetching and N-type ion are injected to form N+ emitter region 5, the area heavy doping N+ 9, polysilicon diode N
+ area 123；
Step 8: carrying out P+ photoetching and P-type ion injection, the highly doped area P+ 6, p type island region 10, polysilicon diode P+ are formed
Area 121；
Step 9: carrying out the photoetching of p-type collecting zone and ion implanting, p-type collecting zone 8 is formed, as shown in figure 17；
Step 10: carrying out BPSG deposit, hole photoetching, simultaneously photoetching, etching form metal interconnection to Metal deposition, that is, prepare
Landscape insulation bar double-pole-type transistor as shown in figure 18.
Further, in the preparation process of dielectric layer can in two steps or three steps formed different-thickness and material gate medium
Layer 110, dielectric layer 111 and dielectric layer 112；
Further, the doping of polysilicon diode p type island region 122 can not use doping in situ, but in p-type collecting zone light
It carves and is obtained in ion implanting step by adjusting reticle graphics proportion.
Claims (5)
1. a kind of landscape insulation bar double-pole-type transistor, half structure cell includes the substrate being cascading from bottom to up
(1), insulating layer (2) and the first N-type doped regions (3)；It is characterized in that, first N-type is low-doped along device longitudinal direction
Area (3) is that second level is ladder-like, and the vertical height for defining second level ladder is greater than first order ladder, first N-type doped regions
(3) upper layer two sides are respectively provided with the area PXing Ti (4) and N-type buffer area (7), along device longitudinal direction, the area PXing Ti (4) and N
Type buffer area (7) is that second level is ladder-like；It is buffered in the first N-type doped regions (3) second level ladder and the area PXing Ti (4) and N-type
There are the second N-type doped regions (150) between the ladder of area (7) second level；The area PXing Ti (4) upper layer, which has to be mutually juxtaposed, to be set
The contact zone P+ (6) and N+ emitter region (5) set, wherein N+ emitter region (5) is located at close to the side of N-type buffer area (7), the P+
Contact zone (6) and N+ emitter region (5) are that second level is ladder-like；The contact zone P+ (6) and part N+ emitter region (5) upper surface tool
Have emitter metal electrode (130), the emitter metal electrode (130) is that second level is ladder-like；Table on the area PXing Ti (4)
Face has first grid structure, and the first grid structure is by the first gate dielectric layer (110) and is located at the first gate dielectric layer (110)
The first polygate electrodes (120) of upper surface are constituted, along device longitudinal direction, the following table of first gate dielectric layer (110)
Face is successively contacted with the upper surface of the upper surface of (3) first ladder of the first N-type doped regions and the second N-type doped regions (150),
The lower surface of first gate dielectric layer (110) is also contacted with the upper surface of part N+ emitter region (5), the first polygate electrodes
(120) upper surface is horizontal plane；There is p-type collecting zone (8), the highly doped area N+ (9) and highly doped in the N-type buffer area (7)
The miscellaneous area P+ (10), the highly doped area N+ (9) and the highly doped area P+ (10) contact with each other and the highly doped area N+ (9) is located at close to p-type body
The side in area (4)；The p-type collecting zone (8), the highly doped area N+ (9) and the highly doped area P+ (10) are that second level is ladder-like；It is described
P-type collecting zone (8) upper surface has collector electrode metal electrode (131) far from the area PXing Ti (4) side, the collector electrode metal electricity
Pole (131) is that second level is ladder-like；The upper surface in the highly doped area N+ (9) and the highly doped area P+ (10) has metal electrode
(132), the metal electrode (132) is that second level is ladder-like；The upper surface of the N-type buffer area (7) has second grid structure,
The second grid structure is by the second gate dielectric layer (111) and positioned at second polysilicon of the second gate dielectric layer (111) upper surface
Electrode (124) is constituted, and along device longitudinal direction, the lower surface of second gate dielectric layer (111) is successively low-doped with the first N-type
The upper surface of the upper surface of (3) first ladder of area and the second N-type doped regions (150) contacts, under the second gate dielectric layer (111)
Surface is also contacted with the upper surface of part p-type collecting zone (8) and the highly doped area P+ (10), the second polysilicon electrode (124) it is upper
Surface is horizontal plane；Device upper surface between the area PXing Ti (4) and N-type buffer area (7) has dielectric layer (112), edge
Device longitudinal direction, the lower surface of the dielectric layer (112) the successively upper surface with (3) first ladder of the first N-type doped regions
Contacted with the upper surfaces of the second N-type doped regions (150), the lower surface of the dielectric layer (112) also with part N-type buffer area
(7) upper surface contact；Dielectric layer (112) upper surface has the area polysilicon P+ (121), p type island region (122) and the area N+
(123), wherein p type island region (122) are located between the area polysilicon P+ (121) and the area N+ (123) and are interconnected to form polysilicon two
Pole pipe, the area P+ (121) are located at close to the side of the area PXing Ti (4), and the area N+ (123) are located at close to N-type buffer area (7) side, along device
The upper surface of part longitudinal direction, the area polysilicon P+ (121), p type island region (122) and the area N+ (123) is horizontal plane；The emitter gold
Belong to and being electrically connected between electrode (130) and the area polysilicon P+ (121), the area N+ (123) and the second polysilicon electrode (124) it
Between be electrically connected and the area N+ (123) and the second polysilicon electrode (124) pass through Zener diode (140) and collector gold
Belong to and being electrically connected between (131), wherein the cathode of Zener diode (140) connects collector electrode metal (131), Zener diode
(140) anode connects the area N+ (123) and the second polysilicon electrode (124).
2. a kind of landscape insulation bar double-pole-type transistor according to claim 1, which is characterized in that second N-type is low
The doping concentration of doped region (150) is equal to or more than the doping concentration of the first N-type doped regions (3).
3. a kind of landscape insulation bar double-pole-type transistor according to claim 1 or 2, which is characterized in that the Zener two
Pole pipe is integrated in above dielectric layer (112) close to collector electrode metal electrode (131) side, corresponding collector electrode metal electrode
(131) it extends to and contacts simultaneously covering part Zener diode upper surface with dielectric layer (112) side.
4. a kind of landscape insulation bar double-pole-type transistor according to claim 1 or 2, which is characterized in that the Zener two
As replaced multiple concatenated diodes, the anode of diode string connects collector electrode metal (131) pole pipe, and cathode connects the area N+ (123)
With polysilicon electrode (124), and the cut-in voltage value of diode string be greater than PMOS threshold voltage absolute value.
5. a kind of landscape insulation bar double-pole-type transistor according to claim 1 or 2, which is characterized in that the polysilicon P
Also there are capacitor (151) between+area (121) and the area N+ (123).
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| CN110459606B (en) * | 2019-08-29 | 2023-03-24 | 电子科技大学 | Transverse groove type IGBT with self-bias PMOS and preparation method thereof |
| CN111276537A (en) * | 2020-02-14 | 2020-06-12 | 电子科技大学 | Reverse conducting RC-LIGBT device with polycrystalline silicon voltage-resistant layer |
| TWI804736B (en) * | 2020-03-25 | 2023-06-11 | 立錡科技股份有限公司 | Power device having lateral insulated gate bipolar transistor (ligbt) and manufacturing method thereof |
| CN113935268B (en) * | 2021-11-22 | 2024-06-11 | 电子科技大学 | Anode short-circuit transverse insulated gate bipolar transistor equivalent circuit model and simulation method |
| CN114937689B (en) * | 2022-06-06 | 2023-04-28 | 电子科技大学 | Planar SiC IGBT and manufacturing method thereof |
| CN117457732B (en) * | 2023-12-22 | 2024-05-28 | 深圳天狼芯半导体有限公司 | SiC LIGBT with P-type space layer below grid electrode and preparation method |
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