CN105742346A - Double split trench gate charge storage-type RC-IGBT and manufacturing method thereof - Google Patents
Double split trench gate charge storage-type RC-IGBT and manufacturing method thereof Download PDFInfo
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- 230000003071 parasitic effect Effects 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
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- 230000003647 oxidation Effects 0.000 description 2
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- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
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- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
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- 238000005538 encapsulation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000009527 percussion Methods 0.000 description 1
- 230000003389 potentiating effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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Abstract
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a reverse trench gate charge storage-type insulated gate bipolar transistor. Double split electrodes which are equal to an emitter in potential and dielectric layers between the double split electrodes and a gate electrode are introduced into the bottom part and the side surface of the gate electrode in a trench of an RC-IGBT device, so that the switching speed of the device in the IGBT working mode is improved; the carrier concentration distribution of the whole N-type drift region is improved; the switching loss of the device is reduced; the saturated current density of the device is reduced; the short-circuit safe operation area of the device is improved; the reliability is improved; a reverse free-wheeling diode has a low diode conduction voltage drop in a reverse free-wheeling diode working mode; the reverse recovery characteristics of the free-wheeling diode are improved; and meanwhile, the manufacturing method of the double split trench gate charge storage-type IGBT does not need to increase an extra processing step and is compatible with a traditional RC-IGBT manufacturing method.
Description
Technical field
The invention belongs to power semiconductor device technology field, relate to insulated gate bipolar transistor (IGBT), be specifically related to inverse
Conductivity type trench gate charge storage type insulated gate bipolar transistor (RC-CSTBT).
Background technology
Insulated gate bipolar transistor (IGBT) is the novel electric power electric that a kind of MOS field effect and bipolar transistor are compound
Device.Its existing MOSFET is prone to drive, and controls simple advantage, has again power transistor turns pressure drop low, on state current
Greatly, little advantage is lost, it has also become one of core electron components and parts in modern power electronic circuit, is widely used in such as
The every field of the national economy such as communication, the energy, traffic, industry, medical science, household electrical appliance and Aero-Space.The application of IGBT
Lifting to power electronic system performance serves particularly important effect.Since IGBT invents, people are devoted to change always
The performance of kind IGBT.Through the development of twenties years, in succession propose 6 generation IGBT device structure, make device performance obtain
Steady lifting.Trench gate charge storage type insulated gate bipolar transistor (CSTBT) in the 6th generation is higher owing to have employed
Doping content and certain thickness N-type charge storage layer structure, make IGBT device near the carrier concentration profile of emitter terminal
Being greatly improved, improve the conductance modulation of N-type drift region, the carrier concentration improving whole N-type drift region is divided
Cloth, makes IGBT obtain low forward conduction voltage drop and the forward conduction voltage drop of improvement and the compromise of turn-off power loss.
In power electronic system, IGBT typically requires collocation fly-wheel diode (Free Wheeling Diode, FWD) and uses
To guarantee the safety and stability of system.Therefore in tradition IGBT module or single tube device, it will usually have FWD and its reverse parallel connection,
The program not only increases the number of device, the volume of module and production cost, and in encapsulation process, the increase of solder joint number can shadow
The reliability of Chinese percussion instrument part, ghost effect produced by metal connecting line has an effect on the overall performance of device.Real in order to solve this problem
The integration of existing product, in conjunction with CSTBT device architecture, industry proposes inverse conductivity type trench gate charge storage type insulated gate bipolar
Transistor (RC-CSTBT), is successfully integrated in inside CSTBT by fly-wheel diode, and its structure is as shown in Figure 1.Compare
In traditional CSTBT without afterflow ability, this structure has made at its back and metal collector 13 and N-type electric field trapping layer 10
The N-type collecting zone 12 connected, this region defines with p-type base 7, N-type charge storage layer 8 and N-drift region 9 in device
Parasitic diode structure, under freewheeling mode, the conducting of this parasitic diode provides current path.
But, for traditional RC-CSTBT device architecture, when forward IGBT mode of operation, due to higher-doped concentration
With the existence of certain thickness N-type charge storage layer, the breakdown voltage of device significantly reduces, and deposits to effectively shield N-type electric charge
It is pressure that the adverse effect of reservoir obtains certain device, needs to use: 1) the deep trench gate degree of depth, make the degree of depth of trench gate be more than
The junction depth of N-type charge storage layer, but the deep trench gate degree of depth not only increases gate-emitter electric capacity, also increases grid-current collection
Electrode capacitance, thus, reduce the switching speed of device, increase the switching loss of device, have impact on the conduction voltage drop of device and open
Close the compromise characteristic of loss；2) little cellular width, makes the spacing between trench gate reduce as far as possible, but, highdensity ditch
Groove MOS structure not only increases the grid capacitance of device, reduces the switching speed of device, increases the switching loss of device,
Have impact on the conduction voltage drop of device and the compromise characteristic of switching loss, and, add the saturation current density of device, make device
Short-circuit safety operation area be deteriorated.When backward diode afterflow mode of operation, due to p-type base 7 and N-type charge storage layer
The existence of the built-in potential of the PN junction that 8/N-drift region 9 is formed, forward conduction voltage drop is relatively big, simultaneously because turn at fly-wheel diode
Shi great Liang carrier is injected into N-drift region 9, and the existence of excessive carrier makes the reverse recovery characteristic of fly-wheel diode relatively
Difference is as big in length reverse recovery time, QRR etc..
Summary of the invention
The invention aims to optimize the forward IGBT characteristic of tradition RC-CSTBT, improve backward diode characteristic simultaneously,
Improving the reliability of device, on the basis of tradition RC-CSTBT device architecture (as shown in Figure 1), the present invention provides a kind of
Double divisions trench gate charge storage type RC-IGBT (as shown in Figure 2) and preparation method thereof, described RC-IGBT device is just
When IGBT mode of operation, in the case of certain device trench depth and trench MOS structure density, by device ditch
The bottom of gate electrode and lateral leadin and equipotential pair of Split Electrode of emitter stage in groove, by double Split Electrodes and double division electricity
Between pole and gate electrode, the shielding action of thick dielectric layer, reduces the grid capacitance of device, and particularly grid-collector capacitance, carries
The high switching speed of device, reduces switching loss, further improves the compromise of forward conduction voltage drop and switching loss, with
Time, the introducing of side Split Electrode reduces the density of MOS raceway groove, improves the short-circuit safety operation area of IGBT, improves
The Performance And Reliability of device；Additionally, the carrier that the wide bottom Split Electrode of channel bottom further enhancing emitter terminal increases
Potent should, further improve the carrier concentration profile of whole N-type drift region, further improve forward conduction voltage drop and opening
Close the compromise of loss, improve the performance of device；Meanwhile, existed by dielectric layer thick around the Split Electrode of bottom and wide width
The most effectively shield in the case of certain device trench depth and trench MOS structure density N-type charge storage layer with
And the impact that at gate electrode and side Split Electrode, thin dielectric layer is pressure on device, improve the breakdown voltage of device, improve
The concentration of channel bottom electric field, further increases the reliability of device.When backward diode afterflow mode of operation, by with
The effect of the side Split Electrode that emitter stage is connected, makes the MOS raceway groove at the Split Electrode of side open, makes reverse afterflow two pole
Pipe works in how sub-device model, has low backward diode conduction voltage drop and excellent reverse recovery characteristic.The present invention provides
Manufacture method need not increase extra processing step, with traditional trench gate charge storage type RC-IGBT manufacture method hold concurrently
Hold.
The technical scheme is that double division trench gate charge storage type RC-IGBT, including being cascading from bottom to up
Collector electrode metal 13, p-type collector area 11, N-type electric field trapping layer 10, N-type drift region 9 and emitter metal 1；Also
Including the N-type collector area 12 being set up in parallel with p-type collector area 11；Described N-type drift region 9 has N+ launch site 5,
P+ launch site 6, p-type base 7, N-type charge storage layer 8 and trench gate structure；Described trench gate structure is the most successively
Extend in N-type drift region after running through N+ launch site 5, p-type base 7 and N-type charge storage layer 8；Described p-type base 7
Being positioned at N-type charge storage layer 8 upper surface, launch site 6, N+ launch site 5 and P+ is positioned at p-type base 7 upper surface side by side；N+
The upper surface of launch site 6, launch site 5 and P+ is connected with emitter metal 1；It is characterized in that, described trench gate structure includes the end
Portion's Split Electrode 31, gate electrode 32, side Split Electrode 33, gate dielectric layer 41, second dielectric layer the 42, the 3rd dielectric layer 43,
4th dielectric layer 44 and the 5th dielectric layer 45；By the 3rd dielectric layer 43 between described gate electrode 32 and side Split Electrode 33
Connect；Described gate electrode 32 is connected with N+ launch site 5 and the p-type base 7 of trench gate structure side by gate dielectric layer 41；
Described side Split Electrode 33 is by second dielectric layer 42 and the N+ launch site 5 of trench gate structure opposite side and p-type base 7
Connect；Described bottom Split Electrode 31 is positioned at the lower section of gate electrode 32 and side Split Electrode 33, and bottom Split Electrode 31
The upper surface degree of depth be more than N-type electric charge less than the junction depth of N-type charge storage layer 8, the lower surface degree of depth of bottom Split Electrode 31
The junction depth of accumulation layer 8；The upper surface of described bottom Split Electrode 31 and gate electrode 32, side Split Electrode 33 lower surface it
Between connected by the 4th dielectric layer 44；The lower surface of described bottom Split Electrode 31 and side are electric with N-type drift region 9 and N-type
Connected by the 5th dielectric layer 45 between lotus accumulation layer 8；The width of described bottom Split Electrode 31 more than second dielectric layer 42,
Side Split Electrode the 33, the 3rd dielectric layer 43, gate electrode 32 and the width sum of gate dielectric layer 41, make trench gate structure in falling
" T " font；Described second dielectric layer 42, side Split Electrode 33 and the upper surface of part the 3rd dielectric layer 43 and emitter stage
Metal 1 connects；The upper surface of described gate dielectric layer 41, gate electrode 32 and part the 3rd dielectric layer 43 has first medium layer 2；
Described bottom Split Electrode 31, side Split Electrode 33 and emitter metal 1 isoelectric level.
Further, described 3rd dielectric layer 43, the thickness of the 4th dielectric layer 44 and the 5th dielectric layer 45 is more than gate dielectric layer
41 and the thickness of second dielectric layer 42.
Further, the thickness of described gate dielectric layer 41 is more than the thickness of second dielectric layer 42.
Further, the bottom of described side Split Electrode 33 extends to be connected with the upper surface of bottom Split Electrode 31.
Further, the both sides of described trench gate structure also have N+ layer 14, and the side of described N+ layer 14 is deposited with N-type electric charge
Reservoir 8 connects, and opposite side and the bottom of N+ layer 14 are connected with trench gate structure, the upper surface of N+ layer 14 and p-type base 7
Lower surface connect.
Further, described drift region structure is NPT structure or FS structure；Described IGBT device employing semi-conducting material Si,
SiC, GaAs or GaN make.
The manufacture method of double division trench gate charge storage type RC-IGBT, it is characterised in that comprise the following steps:
The first step: choosing N-type and monocrystalline silicon piece N-type drift region 9 as device is lightly doped, the silicon wafer thickness chosen is
300～600um, doping content is 1013～1014Individual/cm3；At silicon chip back side by ion implanting N-type impurity maker of annealing
The N-type field stop layer 10 of part, the thickness of the N-type field stop layer of formation is 15～30 microns, and ion implantation energy is
1500keV～2000keV, implantation dosage is 1013～1014Individual/cm2, annealing temperature is 1200-1250 DEG C, and annealing time is
300～600 minutes；
Second step: upset thinning silicon chip, to required thickness, form groove at silicon chip surface by photoetching, etching；
3rd step: at 1050 DEG C～1150 DEG C, O2Atmosphere under around groove formed oxide layer；Then at 750 DEG C～950 DEG C
Under in groove deposit fill polysilicon；Reoxidation also etches away unnecessary oxide layer；Split Electrode 31 and the 5th bottom formation
Dielectric layer 45, described bottom classification electrode 31 is positioned in the 5th dielectric layer 45；
4th step: form 2～6 microns of thick n-type doping layers at silicon chip surface by extension；
5th step: at silicon chip surface one layer of thin pad oxide of deposit and silicon nitride layer, after making window by lithography, again carry out groove
Silicon etching, etches groove above bottom electrode 31, and the oxide layer that in the 3rd step, polysilicon surface oxidation is formed can be as this step
The stop layer of silicon etching；After etching groove completes, by solution by the silicon nitride on surface and pad oxide rinsed clean；This step
The groove formed in the groove of middle formation and second step constitutes inverted " t " font groove；
6th step: grow oxide layer at trench wall by thermal oxide, the oxidated layer thickness of formation is less than 120nm；
7th step: use photoetching process, the oxide layer that in etching the 6th step, in groove, left side wall is formed；In groove right sidewall shape
Become gate dielectric layer 41；The 4th dielectric layer 44 is formed at channel bottom；
8th step: regrow oxide layer at trench wall by thermal oxide, the oxidated layer thickness of formation is less than 40nm；At groove
Left side sidewall forms second gate dielectric layer 42
9th step: polysilicon is filled in deposit in groove at 750 DEG C～950 DEG C；
Tenth step: use photoetching process, the partial polysilicon filled in groove in etching the 9th step, formed respectively in groove both sides
Gate electrode 32 and side Split Electrode 33；Described gate electrode 32 is connected with gate dielectric layer 41, side Split Electrode 33 and
Second medium layer 42 connects；
11st step: deposit, fills in the groove between the gate electrode 32 and the side Split Electrode 33 that are formed and be situated between in the tenth step
Matter forms the 3rd dielectric layer 43；
12nd step: use photoetching process, first pass through the N-type charge storage layer 8 of ion implanting N-type impurity making devices, institute
State N-type charge storage layer 8 and be positioned at groove both sides；The energy of ion implanting is 200～500keV, and implantation dosage is 1013～1014
Individual/cm2；Then by ion implanting p type impurity making p-type base 7 of annealing, the energy of ion implanting is 60～120keV,
Implantation dosage is 1013～1014Individual/cm2, annealing temperature is 1100-1150 DEG C, and annealing time is 10～30 minutes；Described p-type
Base 7 is positioned at N-type charge storage layer 8 upper surface；The junction depth of the N-type charge storage layer 8 formed is deep more than gate electrode 32
Spending and be less than the degree of depth of bottom Split Electrode 31, the junction depth of the p-type base 7 of formation is less than the degree of depth of gate electrode 32；
13rd step: use photoetching process, by the N+ launch site 5 of ion implanting N-type impurity making devices, ion implanting
Energy is 30～60keV, and implantation dosage is 1015～1016Individual/cm2；Described N+ launch site 5 is positioned at p-type base 7 upper surface
And be connected with groove；
14th step: use photoetching process, by the P+ launch site 6 of ion implanting p type impurity making devices of annealing, ion
The energy injected is 60～80keV, and implantation dosage is 1015～1016Individual/cm2, annealing temperature is 900 DEG C, and the time is 20～30 points
Clock；Described P+ launch site 6 is positioned at p-type base 7 upper surface side by side with N+ launch site 5；
15th step: in device surface dielectric layer deposited, and photoetching, etching formation first medium layer 2；Described first medium layer 2
It is positioned at part the 3rd dielectric layer 43, gate electrode 32 and the upper surface of gate dielectric layer 41；
16th step: deposit metal, and photoetching, it is etched in N+ launch site 5 and P+ launch site 6 upper surface and second medium
The upper surface of layer 42, side Split Electrode 33 and part the 3rd dielectric layer 43 forms collector electrode metal 1；
17th step: upset silicon chip, thinning silicon wafer thickness, forms p-type collecting zone 11, institute at silicon chip back side implanting p-type impurity
Stating p-type collecting zone 11 and be positioned at N-type electric field trapping layer 10 lower surface, Implantation Energy is 40～60keV, and implantation dosage is 1012～1013
Individual/cm2；Photoetching again, by the N-type collecting zone 12 of ion implanting N-type impurity making devices, the energy of ion implanting is
40～60keV, implantation dosage is 1014～1015Individual/cm2；Then at H2With N2Back side annealing, temperature is carried out under the atmosphere of mixing
Being 400～450 DEG C, the time is 20～30 minutes；Described N-type collecting zone 12 is set up in parallel with p-type collecting zone 11；
18th step: back side deposit metal forms collector electrode metal 13.
Further, in described 3rd step, p-type base 7 can be formed the most respectively by increasing lithography step, make near grid
The concentration of the p-type base 7 of electrode 32 side and junction depth are more than the concentration of the p-type base 7 near Split Electrode 33 side, side
And junction depth.
The operation principle of the present invention is:
For traditional RC-CSTBT device as shown in Figure 1, when forward IGBT mode of operation, in order to improve IGBT
The performance of device, improves its reliability, needs reduce the switching loss of device under certain blocking voltage ability and reduce forward
Conduction voltage drop, improve the short-circuit safety operation area of device simultaneously.Grid capacitance is rushed, is discharged by the switching process of IGBT exactly
Process, grid capacitance more favourable opposition, discharge time are the longest.Thus, in the switching process of IGBT, grid capacitance, especially
It is that grid-collector capacitance has important impact to the switching loss of device.In traditional trench gate electric charge storage as shown in Figure 1
Deposit in type RC-IGBT structure, in order to effectively shield higher-doped concentration and certain thickness N-type charge storage layer to breakdown potential
It is pressure that the adverse effect of pressure obtains certain device, needs to use: 1) the deep trench gate degree of depth, make the degree of depth of trench gate more than N
The junction depth of type charge storage layer；2) little cellular width, highdensity trench MOS structure makes the spacing between trench gate to the greatest extent may be used
Can reduce.But, the deep trench gate degree of depth and highdensity trench MOS structure both of which not only increase grid-transmitting
Electrode capacitance, also increases grid-collector capacitance.Additionally, for traditional trench gate electric charge memory type IGBT structure, grid oxygen
Changing layer is to be formed in the trench by a thermal oxide, the least in order to ensure the thickness of the whole gate oxide of certain threshold voltage,
Owing to the thickness of mos capacitance size with oxide layer is inversely proportional to, the gate oxidation that conventional trench gate electric charge memory type IGBT structure is medium and small
Layer thickness greatly increases the grid capacitance of device.The most highdensity trench MOS structure adds the saturation current of device
Density, makes the short-circuit safety operation area of device be deteriorated；It addition, the electric field that little gate oxide thickness makes channel bottom is concentrated, make
The reliability of device is poor.
Such as Fig. 2, shown in 3 and 4, the present invention is by the bottom of gate electrode in device trenches and lateral leadin and emitter stage isoelectric level
Double Split Electrodes and double Split Electrode and gate electrode between thick dielectric layer, do not affecting IGBT device threshold voltage and opening
In the case of Tong: 1) reduce the degree of depth of gate electrode in groove, substantially reduce and include grid-collector capacitance, gate-emitter
Electric capacity is in interior grid capacitance；2) by the shielding action of double Split Electrodes, the coupling of grid and colelctor electrode is shielded, by grid
-collector capacitance is converted to gate-emitter electric capacity, substantially reduces grid-collector capacitance, simultaneously by thick dielectric layer 43 He
The effect of 44 makes the gate-emitter electric capacity increased from grid-collector capacitance conversion be far smaller than due to side Split Electrode 33
The gate-emitter electric capacity introduced and reduce, thus substantially reduce and include that grid-collector capacitance, gate-emitter electric capacity exist
Interior grid capacitance.Therefore, present configuration substantially reduces the grid capacitance of device, and particularly grid-collector capacitance, carries
The high switching speed of device, reduces the switching loss of device.Additionally, divide in certain trench MOS structure density downside
The introducing splitting electrode 33 reduces the density of MOS raceway groove, reduces the saturation current density of device, improves the short circuit of device
Safety operation area, improves reliability；Additionally, the wide bottom Split Electrode of channel bottom further enhancing the load of emitter terminal
Flow sub-concentration enhancement effect, further improve the carrier concentration profile of whole N-type drift region, further improve positive guide
Logical pressure drop and the compromise of switching loss, improve the performance of device；Additionally, due to side Split Electrode 33 and bottom Split Electrode
31 with emitter stage isoelectric level, open in dynamic process in IGBT device, divided with side Split Electrode 33 and bottom by dielectric layer
The semiconductor surface splitting electrode 31 contact will not form transoid (floating p-type base 72) and electron accumulation (N-type electric charge storage
Layer 8 and N-type drift region 9), thus without forming negative differential capacity effect, it is to avoid open the electric current in dynamic process, voltage
Vibration and EMI problem, improve reliability；Meanwhile, by the thick dielectric layer around the Split Electrode of bottom and wide width one
The most effectively shield in the case of fixed device trench depth and trench MOS structure density N-type charge storage layer and
The impact that dielectric layer thin at gate electrode and side Split Electrode is pressure on device, the most effectively shields to obtain little
Parasitic MOS structure threshold voltage and impact that at the very thin side Split Electrode that arranges, dielectric layer is pressure on device, improve
The breakdown voltage of device, improves the concentration of channel bottom electric field, further increases the reliability of device.The present invention provides
Composite Double division groove structure, the degree of depth of trench gate electrode 32 is more than the degree of depth of p-type base 7 and the deep of trench gate electrode 32
Degree is less than the degree of depth of N-type charge storage layer 8, and on the one hand this reduce as far as possible not affecting in the case of IGBT device is opened
Grid capacitance, particularly grid-collector capacitance, the existence of the most certain thickness high concentration N-type charge storage layer 8
Compensate for owing to the introducing of bottom equipotential with emitter stage Split Electrode makes near the Split Electrode of bottom under carrier concentration
Fall, it is to avoid the poor device properties that causes owing to the introducing of bottom Split Electrode makes the forward conduction voltage drop of device be increased dramatically.
When backward diode afterflow mode of operation, by adjusting the concentration of p-type base 7 and thickness and the thickness of dielectric layer 42 and material
Material, is made the threshold voltage of MOS structure parasitic at the Split Electrode of side less than 0.1V, is divided by the side being connected with emitter stage
Split the effect of electrode, make the MOS raceway groove at the Split Electrode of side open less than 0.1V, make reverse fly-wheel diode work in
MOS controls the how sub-device model of diode, shields by p-type base 7 and N-type charge storage layer 8/N-drift region 9 shape
The impact of the PN junction built-in potential become, makes reverse fly-wheel diode have low N；Simultaneously because be that many sons are led
Electricity, it is not necessary in reversely restoring process, the excess carriers in N-drift region 9 are extracted, improve fly-wheel diode
Reverse recovery characteristic, as short in reverse recovery time, QRR is little.Additionally, the manufacture method that the present invention provides is not required to
Increase extra processing step, compatible with traditional trench gate charge storage type RC-IGBT manufacture method.
Beneficial effects of the present invention is, is greatly reduced the grid including grid-collector capacitance, gate-emitter electric capacity
Electrode capacitance；Improve the carrier concentration profile of whole N-type drift region；Improve the switching speed of device, reduce opening of device
Close loss, reduce the saturation current density of device, improve the short-circuit safety operation area of device, improve reliability, improve
The concentration of channel bottom electric field, it is to avoid owing to the introducing of bottom Split Electrode makes the forward conduction voltage drop of device be increased dramatically
The poor device properties caused, makes reverse fly-wheel diode have low N, improves the anti-of fly-wheel diode
To recovery characteristics, as short in reverse recovery time, QRR is little；Additionally, the manufacture method that the present invention provides need not
Increase extra processing step, compatible with traditional trench gate charge storage type RC-IGBT manufacture method.
Accompanying drawing explanation
Fig. 1 is traditional RC-CSTBT device cellular structural representation；
In Fig. 1,1 is emitter metal, and 2 is dielectric layer, and 3 is gate electrode, and 4 is gate dielectric layer, and 5 is N+ launch site, 6
For P+ launch site, 7 is p-type base, and 8 is N-type charge storage layer, and 9 is N-drift region, and 10 is N-type electric field trapping layer,
11 is p-type collecting zone, and 12 is N-type collecting zone, and 13 is collector electrode metal；
Fig. 2 is double division trench gate charge storage type RC-IGBT device cellular structural representations of embodiment 1；
Fig. 3 is double division trench gate charge storage type RC-IGBT device cellular structural representations of embodiment 2；
Fig. 4 is double division trench gate charge storage type RC-IGBT device cellular structural representations of embodiment 3；
In Fig. 2 to Fig. 3,1 is emitter metal, and 2 is dielectric layer, and 31 is bottom Split Electrode, and 32 is gate electrode, and 33 are
Side Split Electrode, 41 is gate dielectric layer, and 42 is dielectric layer, and 43 is dielectric layer, and 44 is dielectric layer, and 45 is dielectric layer, 5
For N+ launch site, 6 is P+ launch site, and 7 is p-type base, and 8 is N-type charge storage layer, and 9 is N-drift region, and 10 is N
Type electric field trapping layer, 11 is p-type collecting zone, and 12 is N-type collecting zone, and 13 is collector electrode metal, and 14 is N+ layer；
Fig. 5 be the present invention manufacture method in device architecture schematic diagram after for the first time etching forms groove；
Fig. 6 be the present invention manufacture method in formed bottom device architecture schematic diagram after Split Electrode；
Fig. 7 be the present invention manufacture method in device architecture schematic diagram after extension N-layer；
Fig. 8 be the present invention manufacture method in second time etching form the device architecture schematic diagram after groove；
Fig. 9 be the present invention manufacture method in form the device architecture schematic diagram after gate dielectric layer；
Figure 10 be the present invention manufacture method in form the device architecture schematic diagram after gate electrode and side Split Electrode；
Figure 11 be the present invention manufacture method in complete device architecture schematic diagram after Overall Steps.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, technical scheme is described in detail:
Embodiment 1
A kind of double division trench gate charge storage type RC-IGBT of this example, its structure cell is as in figure 2 it is shown, include: back collection
Electrode metal 13, be positioned on back collector electrode metal 13 and coupled p-type collecting zone 11 and N-type collecting zone 12,
Be positioned on p-type collecting zone 11 and N-type collecting zone 12 and coupled N-type field stop layer 10, be positioned at N-type field stop
On layer 10 and coupled N-drift region 9；It is positioned in the middle of top, N-drift region 9 and coupled Composite Double division ditch
Groove structure；It is positioned at both sides, top, N-drift region 9 coupled N-type charge storage layer 8, described N-type charge storage layer 8
The sidewall of sidewall and Composite Double division groove structure be connected, be positioned at N-type charge storage layer 8 top and in its connected p-type base
District 7, the sidewall of described p-type base 7 is connected with the sidewall of Composite Double division groove structure；Be positioned at top, p-type base 7 and with
Its N+ launch site independent of each other being connected and P+ launch site, the sidewall of described N+ launch site and Composite Double division groove structure
Sidewall is connected；It is positioned at N+ launch site and the emitter metal 1 of P+ launch site upper surface；It is positioned on Composite Double division groove structure
The dielectric layer 2 in portion；It is characterized in that: described Composite Double division groove structure includes understructure and superstructure；Described lower floor
Structure includes thick dielectric layer 45 and the bottom Split Electrode 31 being arranged in thick dielectric layer 45；Described superstructure includes trench gate
Electrode 32, side Split Electrode 33, dielectric layer 41, dielectric layer 42, dielectric layer 43 and dielectric layer 44, described gate electrode 32
And be dielectric layer 43 between side Split Electrode 33, described gate electrode 32 and side Split Electrode 33 and bottom Split Electrode 31
Between be dielectric layer 44, described trench gate electrode 32 is connected with N+ launch site 5 and p-type base 7 by dielectric layer 41, institute
State side Split Electrode 33 to be connected with N+ launch site 5 and p-type base 7 by dielectric layer 42；The width of described understructure
Width more than described superstructure；The degree of depth of described trench gate electrode 32 is more than the junction depth of p-type base 7, described trench gate electricity
The degree of depth of pole 32 is less than the junction depth of N-type charge storage layer 8, described trench gate electrode 32 and the width of side Split Electrode 33
More than dielectric layer 45 and the thickness of dielectric layer 44；The degree of depth of described side Split Electrode 33 is more than the junction depth of p-type base 7, institute
State the degree of depth degree of depth not less than trench gate electrode 32 of side Split Electrode 33；The degree of depth of described bottom Split Electrode 31 upper surface
Less than the junction depth of N-type charge storage layer 8, the degree of depth of described bottom Split Electrode 31 lower surface is more than N-type charge storage layer 8
Junction depth；The thickness of described dielectric layer 45,43 and 44 is more than the thickness of dielectric layer 41 and 42, the thickness of described dielectric layer 42
Thickness less than dielectric layer 41；Described side Split Electrode 33 is connected on surface with emitter metal 1, described bottom division electricity
Pole 31 and emitter metal 1 isoelectric level.The degree of depth of the described trench gate electrode 32 formed is more than the junction depth 0.1～0.2 of p-type base 7
Micron, the thickness of the described N-type charge storage layer 8 of formation is 1～2 micron；Table on the described bottom Split Electrode 31 formed
The degree of depth in face is less than the junction depth 0.5 of N-type charge storage layer 8～1.5 microns, and the degree of depth of lower surface is more than N-type charge storage layer 8
Junction depth 0.5～1 micron；The thickness of the described dielectric layer 41 formed is less than 120 nanometers, the thickness of the described dielectric layer 42 of formation
Degree is less than 40 nanometers, and the width of the described dielectric layer 43 of formation is 0.5～1 micron, the described dielectric layer 44 and 45 of formation
Thickness is 0.2～0.5 micron, and the understructure of the described Composite Double division groove structure of formation is each wider at the right and left than superstructure
0.2～1 micron；By adjusting the concentration of p-type base 7 and thickness and the thickness of dielectric layer 42 and material, make side division electricity
The threshold voltage of MOS structure parasitic at pole is less than 0.1V.
Embodiment 2
A kind of double division trench gate charge storage type RC-IGBT of this example, its structure cell is not as it is shown on figure 3, with embodiment 1
With, the bottom of side Split Electrode 33 extends directly into the upper surface of bottom Split Electrode 31, makes side Split Electrode 33
The grid capacitance reducing device further it is joined directly together with bottom Split Electrode 31.
Embodiment 3
A kind of double division trench gate charge storage type RC-IGBT of this example, its structure cell is not as it is shown on figure 3, with embodiment 1
With, the subregion between the understructure and p-type base 7 of described composite trench structure also has one layer of N+ layer 14,
The concentration of described N+ layer 14 is connected with composite trench structure more than concentration and its sidewall of N-type charge storage layer 8, formation
Described N+ layer 14 further reduces the resistance in region between described composite trench structure bottom structure and p-type base 7, enters one
Step improves the carrier of emitter terminal and injects enhancement effect, can obtain more preferable device forward conduction voltage drop and the folding of switching loss
In.
The specific embodiments of present invention process manufacture method is with double division trench gate charge storage type of 600V electric pressure
Being illustrated as a example by RC-IGBT, concrete technology manufacture method is as follows:
The first step: choosing doping content is 2 × 1014Individual/cm3, thickness be 300～600 microns FZ silicon chip is lightly doped in order to shape
Become the N-drift region 9 of device；At silicon chip back side by ion implanting N-type impurity the N-type field stop layer of making devices of annealing
10, the thickness of the N-type field stop layer of formation is 15～20 microns, and ion implantation energy is 1500keV～2000keV, injectant
Amount is 5 × 1013Individual/cm2, annealing temperature is 1200 DEG C, and annealing time is 400 minutes；
Second step: upset the thickness of thinning silicon chip to 90～95 microns, forms uniform point at silicon chip surface by photoetching, etching
The groove of cloth, gash depth is 0.5～2 micron, and width is 2～3 microns, and the spacing between groove is 0.5～1.5 micron；
3rd step: at 1050 DEG C～1150 DEG C, O2Atmosphere under to form thickness around groove be the thick oxide layer of 0.2～0.5 micron；
Then at 850 DEG C, in groove, accumulation fills polysilicon；Reoxidation also etches away unnecessary oxide layer, at polysilicon surface
Form the thick oxide layer of 0.2～0.3 micron；
4th step: forming thickness by extension at silicon chip surface is 3～5 microns, and doping content is 2 × 1014Individual/cm3N-type
Doped layer；
5th step: at silicon chip surface one layer of thin pad oxide of deposit and silicon nitride layer, after making window by lithography, again carry out groove
(trench) silicon etching, etches groove, and the oxide layer that the 3rd step polysilicon surface oxidation is formed can be as the end of this step silicon etching
Only layer；After etching groove completes, by solution by the silicon nitride on surface and pad oxide rinsed clean；In the groove that this step is formed
The groove center line that line is formed with second step overlaps, and the groove width of formation is 0.6～1.5 micron；
6th step: grow high-quality thin oxide layer at trench wall by thermal oxide, the oxidated layer thickness of formation is less than 60nm；
7th step: photoetching, the oxide layer that in etching the 6th step, in groove, left side wall is formed；
8th step: regrow high-quality thin oxide layer at trench wall by thermal oxide, the oxidated layer thickness of formation is less than
20nm；
9th step: polysilicon is filled in deposit in groove at 850 DEG C；
Tenth step: photoetching, the partial polysilicon filled in groove in etching the 9th step, form gate electrode 32 and side Split Electrode
33；
11st step: deposit, filled media shape in groove between gate electrode 32 and the side Split Electrode 33 that the tenth step is formed
Become dielectric layer 43；
12nd step: photoetching, first passes through the N-type charge storage layer 8 of ion implanting N-type impurity making devices, ion implanting
Energy is 500keV, and implantation dosage is 5 × 1013Individual/cm2；Then by ion implanting p type impurity the p of making devices of annealing
Type base 7, the energy of ion implanting is 120keV, and implantation dosage is 1 × 1014Individual/cm2, annealing temperature is 1100-1150 DEG C,
Annealing time is 15～30 minutes；The junction depth of the p-type base 7 formed, than the depth as shallow 0.1 of gate electrode 32～0.2 micron, is formed
The junction depth of described N-type charge storage layer 8 more than the degree of depth of gate electrode 32 and less than the degree of depth of bottom Split Electrode 31, formation
The thickness of N-type charge storage layer 8 be 1～2 micron；
13rd step: photoetching, by the N+ launch site of ion implanting N-type impurity making devices, the energy of ion implanting is
40keV, implantation dosage is 1 × 1015Individual/cm2；
14th step: photoetching, by the P+ launch site of ion implanting p type impurity making devices of annealing, the energy of ion implanting
For 60keV, implantation dosage is 5 × 1015Individual/cm2, annealing temperature is 900 DEG C, and the time is 30 minutes；
15th step: dielectric layer deposited, and photoetching, etching formation dielectric layer 2；
16th step: deposit metal, and photoetching, etching formation metal collector 1；
17th step: upset silicon chip, thinning silicon wafer thickness, photoetching the p-type in silicon chip back side implanting p-type impurity making devices
Collecting zone 11, Implantation Energy is 60keV, and implantation dosage is 5 × 1012Individual/cm2；Photoetching again, miscellaneous by ion implanting N-type
The N-type collecting zone 12 of matter making devices, the energy of ion implanting is 60keV, and implantation dosage is 2 × 1014Individual/cm2；Then exist
H2With N2Carrying out back side annealing under the atmosphere of mixing, temperature is 450 DEG C, and the time is 30 minutes；
18th step: back side deposit metal forms metal collector 13.
I.e. it is prepared into double division trench gate charge storage type RC-IGBT.
Further, in described processing step, the preparation of first step N-type field stop layer 10 can have been prepared at the Facad structure of device
Carry out afterwards；Or can directly select the two-layer epitaxial material with N-type field stop layer 10 and N-drift region 9 to initiate as technique
Silicon sheet material；
Further, in described processing step, the preparation of first step N-type field stop layer 10 can be omitted；
Further, can increase by a step etching technics before the 9th step polysilicon deposit, etching removes the oxygen under side Split Electrode 33
Change layer, i.e. form device architecture as shown in Figure 3；
Further, before the 6th step oxidation technology, high-dopant concentration is formed by the ion implanting N-type impurity of band angle
N+ layer 14 or in the forming process of the 12nd step N-type charge storage layer 8, by increasing by step photoetching and an ion implantation technology
Form the N+ layer 14 of high-dopant concentration, i.e. form device architecture as shown in Figure 4；
Further, the 12nd step in described processing step, p can be formed respectively in groove both sides at twice by increasing lithography step
Type base 7, makes the concentration of the p-type base 7 near gate electrode 32 side and junction depth be more than near Split Electrode 33 side, side
The concentration of p-type base 7 and junction depth；
Further, the material of described dielectric layer 41,42,43,44 and 45 can be the same or different.
Claims (6)
1. couple division trench gate charge storage type RC-IGBT, including the collector electrode metal (13) being cascading from bottom to up,
P-type collector area (11), N-type electric field trapping layer (10), N-type drift region (9) and emitter metal (1)；Also include with
The N-type collector area (12) that p-type collector area (11) is set up in parallel；Described N-type drift region (9) has N+ launch
District (5), P+ launch site (6), p-type base (7), N-type charge storage layer (8) and trench gate structure；Described trench gate is tied
Structure extends to N after vertically sequentially passing through N+ launch site (5), p-type base (7) and N-type charge storage layer (8)
In type drift region；Described p-type base (7) is positioned at N-type charge storage layer (8) upper surface, and N+ launch site (5) and P+ send out
Penetrate district (6) and be positioned at p-type base (7) upper surface side by side；The upper surface of N+ launch site (5) and P+ launch site (6) with send out
Emitter-base bandgap grading metal (1) connects；It is characterized in that, described trench gate structure include bottom Split Electrode (31), gate electrode (32),
Side Split Electrode (33), gate dielectric layer (41), second dielectric layer (42), the 3rd dielectric layer (43), the 4th dielectric layer (44)
With the 5th dielectric layer (45)；Between described gate electrode (32) and side Split Electrode (33) by the 3rd dielectric layer (43) even
Connect；Described gate electrode (32) is by gate dielectric layer (41) and the N+ launch site (5) of trench gate structure side and p-type base
(7) connect；Described side Split Electrode (33) is launched by the N+ of second dielectric layer (42) with trench gate structure opposite side
District (5) and p-type base (7) connect；Described bottom Split Electrode (31) is positioned at gate electrode (32) and side Split Electrode
(33) lower section, and the upper surface degree of depth of bottom Split Electrode (31) is less than the junction depth of N-type charge storage layer (8), the end
The lower surface degree of depth of portion's Split Electrode (31) is more than the junction depth of N-type charge storage layer (8)；Described bottom Split Electrode (31)
Upper surface and gate electrode (32), side Split Electrode (33) lower surface between be connected by the 4th dielectric layer (44)；Institute
State and pass through between lower surface and side and N-type drift region (9) and the N-type charge storage layer (8) of bottom Split Electrode (31)
5th dielectric layer (45) connects；The width of described bottom Split Electrode (31) is more than second dielectric layer (42), side division electricity
Pole (33), the 3rd dielectric layer (43), gate electrode (32) and the width sum of gate dielectric layer (41), make trench gate structure in
Inverted " t " font；Described second dielectric layer (42), side Split Electrode (33) and the upper table of part the 3rd dielectric layer (43)
Face is connected with emitter metal (1)；Described gate dielectric layer (41), gate electrode (31) and part the 3rd dielectric layer (43)
Upper surface has first medium layer (2)；Described bottom Split Electrode (31), side Split Electrode (33) and emitter metal (1)
Isoelectric level.
Double division trench gate charge storage type RC-IGBT the most according to claim 1, it is characterised in that the described 3rd
The thickness of dielectric layer (43), the 4th dielectric layer (44) and the 5th dielectric layer (45) is all higher than the thickness of gate dielectric layer (41)；
The thickness of described 3rd dielectric layer (43), the 4th dielectric layer (44) and the 5th dielectric layer (45) is all higher than second dielectric layer (42)
Thickness；The thickness of described gate dielectric layer (41) is more than the thickness of second dielectric layer (42).
Double division trench gate charge storage type RC-IGBT the most according to claim 1, it is characterised in that described side
The bottom of Split Electrode (33) extends to be connected with the upper surface of bottom Split Electrode (31).
Double division trench gate charge storage type RC-IGBT the most according to claim 1, it is characterised in that described groove
The both sides of grid structure also have N+ layer (14), and the side of described N+ layer (14) is connected with N-type charge storage layer (8), N+
Opposite side and the bottom of layer (14) are connected with trench gate structure, the upper surface of N+ layer (14) and the following table of p-type base (7)
Face connects.
5. the manufacture method of couple division trench gate charge storage type RC-IGBT, it is characterised in that comprise the following steps:
The first step: choosing N-type and monocrystalline silicon piece N-type drift region (9) as device is lightly doped, the silicon wafer thickness chosen is
300～600um, doping content is 1013～1014Individual/cm3；At silicon chip back side by ion implanting N-type impurity maker of annealing
The N-type field stop layer (10) of part, the thickness of the N-type field stop layer of formation is 15～30 microns, and ion implantation energy is
1500keV～2000keV, implantation dosage is 1013～1014Individual/cm2, annealing temperature is 1200-1250 DEG C, and annealing time is
300～600 minutes；
Second step: upset thinning silicon chip, to required thickness, form groove at silicon chip surface by photoetching, etching；
3rd step: at 1050 DEG C～1150 DEG C, O2Atmosphere under around groove formed oxide layer；Then at 750 DEG C～950 DEG C
Under in groove deposit fill polysilicon；Reoxidation also etches away unnecessary oxide layer；Bottom formation Split Electrode (31) and
5th dielectric layer (45), described bottom classification electrode (31) is positioned in the 5th dielectric layer (45)；
4th step: form 2～6 microns of thick n-type doping layers at silicon chip surface by extension；
5th step: at silicon chip surface one layer of thin pad oxide of deposit and silicon nitride layer, after making window by lithography, again carry out groove
Silicon etching, etches groove in bottom electrode (31) top, and the oxide layer that in the 3rd step, polysilicon surface oxidation is formed can conduct
The stop layer of this step silicon etching；After etching groove completes, by solution by the silicon nitride on surface and pad oxide rinsed clean；Should
The groove formed in the groove formed in step and second step constitutes inverted " t " font groove；
6th step: grow oxide layer at trench wall by thermal oxide, the oxidated layer thickness of formation is less than 120nm；
7th step: use photoetching process, the oxide layer that in etching the 6th step, in groove, left side wall is formed；In groove right sidewall shape
Become gate dielectric layer (41)；The 4th dielectric layer (44) is formed at channel bottom；
8th step: regrow oxide layer at trench wall by thermal oxide, the oxidated layer thickness of formation is less than 40nm；At groove
Left side sidewall forms second gate dielectric layer (42)
9th step: polysilicon is filled in deposit in groove at 750 DEG C～950 DEG C；
Tenth step: use photoetching process, the partial polysilicon filled in groove in etching the 9th step, formed respectively in groove both sides
Gate electrode (32) and side Split Electrode (33)；Described gate electrode (32) is connected with gate dielectric layer (41), and side divides
Electrode (33) is connected with second dielectric layer (42)；
11st step: deposit, in the groove between the gate electrode (32) and the side Split Electrode (33) that are formed in the tenth step
Filled media forms the 3rd dielectric layer (43)；
12nd step: use photoetching process, first pass through the N-type charge storage layer (8) of ion implanting N-type impurity making devices,
Described N-type charge storage layer (8) is positioned at groove both sides；The energy of ion implanting is 200～500keV, and implantation dosage is 1013～1014
Individual/cm2；Then by ion implanting p type impurity making p-type base (7) of annealing, the energy of ion implanting is 60～120keV,
Implantation dosage is 1013～1014Individual/cm2, annealing temperature is 1100-1150 DEG C, and annealing time is 10～30 minutes；Described p-type
Base (7) is positioned at N-type charge storage layer (8) upper surface；The junction depth of the N-type charge storage layer (8) formed is more than grid electricity
The degree of depth of pole (32) the degree of depth less than bottom Split Electrode (31), the junction depth of the p-type base (7) of formation is less than gate electrode
(32) the degree of depth；
13rd step: use photoetching process, by the N+ launch site (5) of ion implanting N-type impurity making devices, ion is noted
The energy entered is 30～60keV, and implantation dosage is 1015～1016/cm2；Described N+ launch site (5) is positioned at p-type base
(7) upper surface being connected with groove；
14th step: use photoetching process, by the P+ launch site (6) of ion implanting p type impurity making devices of annealing, from
The energy that son injects is 60～80keV, and implantation dosage is 1015～1016/cm2, and annealing temperature is 900 DEG C, and the time is 20～30
Minute；Described P+ launch site (6) and N+ launch site (5) are positioned at p-type base (7) upper surface side by side；
15th step: in device surface dielectric layer deposited, and photoetching, etching formation first medium layer (2)；Described first medium
Layer (2) is positioned at part the 3rd dielectric layer (43), gate electrode (32) and the upper surface of gate dielectric layer (41)；
16th step: deposit metal, and photoetching, it is etched in N+ launch site (5) and P+ launch site (6) upper surface and the
The upper surface of second medium layer (42), side Split Electrode (33) and part the 3rd dielectric layer (43) forms collector electrode metal (1)；
17th step: upset silicon chip, thinning silicon wafer thickness, forms p-type collecting zone (11) at silicon chip back side implanting p-type impurity,
Described p-type collecting zone (11) is positioned at N-type electric field trapping layer (10) lower surface, and Implantation Energy is 40～60keV, injectant
Amount is 1012～1013/cm2；Photoetching again, by the N-type collecting zone (12) of ion implanting N-type impurity making devices,
The energy of ion implanting is 40～60keV, and implantation dosage is 1014～1015Individual/cm2；Then at H2With N2Enter under the atmosphere of mixing
Annealing in the row back side, temperature is 400～450 DEG C, and the time is 20～30 minutes；Described N-type collecting zone (12) and p-type collecting zone
(11) it is set up in parallel；
18th step: back side deposit metal forms collector electrode metal (13).
The manufacture method of double division trench gate charge storage type RC-IGBT the most according to claim 5, it is characterised in that
In described 3rd step, p-type base (7) can be formed the most respectively by increasing lithography step, make near gate electrode (32)
The concentration of the p-type base (7) of side and junction depth are more than the concentration of the p-type base (7) near Split Electrode (33) side, side
And junction depth.
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| WO2019219071A1 (en) * | 2018-05-17 | 2019-11-21 | 上海先进半导体制造股份有限公司 | Insulated gate bipolar transistor and fabrication method therefor |
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| CN111697068A (en) * | 2019-03-14 | 2020-09-22 | 株式会社东芝 | Semiconductor device with a plurality of semiconductor chips |
| CN112331716A (en) * | 2020-09-27 | 2021-02-05 | 广东美的白色家电技术创新中心有限公司 | Semiconductor device, manufacturing method thereof and household appliance |
| CN113451400A (en) * | 2021-06-28 | 2021-09-28 | 宁波达新半导体有限公司 | Trench gate reverse conducting type IGBT device |
| CN113838916A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof |
| EP4343855A1 (en) * | 2022-09-21 | 2024-03-27 | Kabushiki Kaisha Toshiba | Semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840919A (en) * | 2008-12-23 | 2010-09-22 | 电力集成公司 | Vts insulated gate bipolar transistor |
| US20120104555A1 (en) * | 2010-10-31 | 2012-05-03 | Alpha And Omega Semiconductor Incorporated | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances |
| US20130134505A1 (en) * | 2011-11-29 | 2013-05-30 | Kabushiki Kaisha Toshiba | Semiconductor device for power and method of manufacture thereof |
| US20140027845A1 (en) * | 2012-07-27 | 2014-01-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20140077293A1 (en) * | 2012-09-19 | 2014-03-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN103972287A (en) * | 2013-01-28 | 2014-08-06 | 株式会社东芝 | Semiconductor device |
-
2016
- 2016-04-26 CN CN201610263838.9A patent/CN105742346B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840919A (en) * | 2008-12-23 | 2010-09-22 | 电力集成公司 | Vts insulated gate bipolar transistor |
| US20120104555A1 (en) * | 2010-10-31 | 2012-05-03 | Alpha And Omega Semiconductor Incorporated | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances |
| US20130134505A1 (en) * | 2011-11-29 | 2013-05-30 | Kabushiki Kaisha Toshiba | Semiconductor device for power and method of manufacture thereof |
| US20140027845A1 (en) * | 2012-07-27 | 2014-01-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20140077293A1 (en) * | 2012-09-19 | 2014-03-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN103972287A (en) * | 2013-01-28 | 2014-08-06 | 株式会社东芝 | Semiconductor device |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106356400A (en) * | 2016-07-18 | 2017-01-25 | 电子科技大学 | Carrier storage type grooved-gate IGBT (insulated gate bipolar transistor) |
| CN107731897B (en) * | 2017-10-20 | 2020-10-02 | 电子科技大学 | Trench gate charge storage type IGBT and manufacturing method thereof |
| CN107731897A (en) * | 2017-10-20 | 2018-02-23 | 电子科技大学 | A kind of trench gate charge storage type IGBT and its manufacture method |
| CN109755304B (en) * | 2017-11-01 | 2020-10-16 | 苏州东微半导体有限公司 | Split-gate IGBT power device |
| CN109755304A (en) * | 2017-11-01 | 2019-05-14 | 苏州东微半导体有限公司 | One kind dividing grid IGBT power device |
| WO2019219071A1 (en) * | 2018-05-17 | 2019-11-21 | 上海先进半导体制造股份有限公司 | Insulated gate bipolar transistor and fabrication method therefor |
| US11605725B2 (en) | 2018-05-17 | 2023-03-14 | Advanced Semiconductor Manufacturing Corporation., Ltd. | Insulated gate bipolar transistor and fabrication method therefor |
| CN109103186A (en) * | 2018-08-14 | 2018-12-28 | 电子科技大学 | A kind of integrated hetero-junctions freewheeling diode silicon carbide tank gate MOSFET |
| CN109103186B (en) * | 2018-08-14 | 2022-10-11 | 电子科技大学 | Integrated heterojunction freewheeling diode carborundum grooved gate MOSFET |
| CN111697068A (en) * | 2019-03-14 | 2020-09-22 | 株式会社东芝 | Semiconductor device with a plurality of semiconductor chips |
| CN111697068B (en) * | 2019-03-14 | 2023-06-06 | 株式会社东芝 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
| CN110504260A (en) * | 2019-08-29 | 2019-11-26 | 电子科技大学 | A kind of lateral trench type IGBT and preparation method thereof with automatic biasing PMOS |
| CN110504260B (en) * | 2019-08-29 | 2022-11-04 | 电子科技大学 | Transverse groove type IGBT with self-bias PMOS and preparation method thereof |
| CN112331716A (en) * | 2020-09-27 | 2021-02-05 | 广东美的白色家电技术创新中心有限公司 | Semiconductor device, manufacturing method thereof and household appliance |
| CN113451400A (en) * | 2021-06-28 | 2021-09-28 | 宁波达新半导体有限公司 | Trench gate reverse conducting type IGBT device |
| CN113838916A (en) * | 2021-09-23 | 2021-12-24 | 电子科技大学 | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof |
| CN113838916B (en) * | 2021-09-23 | 2023-05-26 | 电子科技大学 | Separation gate CSTBT with PMOS current clamping function and manufacturing method thereof |
| EP4343855A1 (en) * | 2022-09-21 | 2024-03-27 | Kabushiki Kaisha Toshiba | Semiconductor device |
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