CN102184944B - Junction terminal structure of lateral power device - Google Patents

Junction terminal structure of lateral power device Download PDF

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CN102184944B
CN102184944B CN2011101124008A CN201110112400A CN102184944B CN 102184944 B CN102184944 B CN 102184944B CN 2011101124008 A CN2011101124008 A CN 2011101124008A CN 201110112400 A CN201110112400 A CN 201110112400A CN 102184944 B CN102184944 B CN 102184944B
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field plate
region
power device
lateral
semiconductor region
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CN102184944A (en
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郭宇锋
钟大伟
夏晓娟
张长春
张瑛
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南京邮电大学
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/404Multiple field plate structures
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

一种横向功率器件结终端结构至少包含依次相连的三个半导体掺杂区、一个侧壁氧化区和两端的侧壁场板区。 A widthwise power device junction termination structure comprising at least three sequentially connected to the doped semiconductor region, a sidewall region of the field plate region and at both ends of the side wall oxide. 其中位于一端的掺杂区为第一类导电类型,构成器件的沟道区(或阳极),另一端的掺杂区为第二类导电类型,构成器件的漏极区(或阴极),夹在中间的半导体区为第二类导电类型,构成器件的漂移区。 Wherein the doped region is located at one end of first conductivity type, a channel region (or an anode) constituting the device, the other end of the second doped region type conductivity type, a drain region (or cathode) composed of the device, clamp in the middle region of the second semiconductor type conductivity type, a drift region of the device configuration. 漂移区的下部与外延层相接,上部与场氧层相接,边侧与氧化区相接,在源区和漏区的侧壁氧化区内刻蚀淀积多晶硅形成斜坡形或多阶梯形3D场板,分别与栅极和漏极电学接触,同时侧壁场板需要垂直延伸超过衬底表面进入衬底内部。 A lower portion of the drift region in contact with the epitaxial layer, the field oxide layer in contact with the upper, side of the oxidation zone in contact with the polysilicon formed in the tapered or stepped sidewall oxide etch-deposition source region and a drain region 3D field plates, each electrical contact with the gate and the drain, and vertical sidewalls of field plate needs to extend beyond the substrate surface into the interior of the substrate. 采用该结构制造横向PN二极管、横向扩散场效应晶体管LDMOS、或横向绝缘栅双极型晶体管LIGBT,具有击穿电压高、导通电阻小、工艺简单、成本低廉等优点。 With this structure fabrication lateral PN diode, a lateral diffusion of the LDMOS field-effect transistor, or lateral insulated gate bipolar transistor the LIGBT, having a high breakdown voltage, low on-resistance, simplicity, low cost and the like.

Description

一种横向功率器件的结终端结构技术领域 Junction termination structure transverse to the technical field of power device

[0001] 本发明属于半导体功率器件技术和半导体工艺领域,尤其涉及大功率和高压应用的横向功率器件结终端技术,如横向扩散场效应晶体管LDM0S、横向高压二极管、横向绝缘栅双极型晶体管LIGBT等。 [0001] The present invention relates to semiconductor power device technology and semiconductor technology, and in particular the lateral power device junction termination technique involves high power and high voltage applications, such as lateral diffusion of the field effect transistor LDM0S, lateral high voltage diode, a lateral insulated gate bipolar transistor LIGBT Wait.

背景技术 Background technique

[0002] 众所周知,在横向功率器件的设计过程中,必须综合考虑击穿电压、导通电阻、工艺复杂度以及可靠性等因素的相互影响,使其达到一个较为合理的折中。 [0002] It is well known in the design process in a lateral power device, we must consider factors mutually breakdown voltage, on-resistance, reliability and complexity of the process, to reach a reasonable compromise. 通常某一方面性能的提高往往会导致其它方面性能的退化,击穿电压和导通电阻即存在着这样的矛盾关系。 Generally improve some aspect of performance often cause degradation of other aspects of performance, breakdown voltage and on-resistance such that there is a contradictory relationship. 如何在提高击穿电压的同时能够保持导通电阻的不变或者能够尽量地减小导通电阻一直是研究的热点。 How can be kept constant in the on-resistance while improving the breakdown voltage can be as much as possible or to reduce the on-resistance has been a research focus. [0003] 对于常规横向功率器件,由于受结边缘曲率效应影响,击穿电压较之理论值会大打折扣,特别是在浅结扩散和小曲率的情况下表现尤为明显。 [0003] For a conventional lateral power devices, due to the impact effect of curvature of the junction edge, the breakdown voltage will be greatly reduced compared to the theoretical value, especially in the case of a shallow junction diffusion and especially the performance a small curvature. 为解决这个问题,AS Grove等人在1967年3月发表的文章“表面电场对平面PN结击穿电压的影响”(IEEETransElectron Devices, vol. ED-14, pp. 157-162)中最先提出了场板技术,起初它被用于降低PN结电场峰值,因其结构简单、工艺和集成电路工艺完全兼容、并且效果明显,故而迅速在高压分立结器件、功率MOS器件、高压功率集成电路中得到了广泛的应用。 To solve this problem, AS Grove et al., Published in March 1967 article "Influence of surface electric field breakdown voltage of the PN junction plane" (IEEETransElectron Devices, vol. ED-14, pp. 157-162) was first proposed a field plate technique, at first it is used to reduce the peak electric field the PN junction, because of its simple structure, and the process is fully compatible with integrated circuit technology, and the effect is obvious, therefore rapidly discrete high voltage junction device, the power MOS device, a high voltage power integrated circuit It has been widely used. 场板的基本结构如图I所示,在半导体衬底100上分别进行两次掺杂形成第一类导电类型半导体区域102和第二类导电类型半导体区域104,即构成PN结,在该PN结上方二氧化硅层120上覆盖一层金属层110,我们称该金属层为金属场板,如果在场板上偏置适当的电压,将在硅的上表面感应出界面电荷,这些界面电荷产生的电场可以大大削弱PN结的峰值电场,从而提闻击穿电压。 The basic structure of the field plate shown in FIG. I, the two forming a first doping type conductivity type semiconductor region 102 and the second type of conductivity type semiconductor region 104 constitute a PN junction on the semiconductor substrate 100, respectively, the PN over the silicon dioxide layer covering the junction 120 a metal layer 110, we call this metal layer is a metal field plate, the field plate if a suitable bias voltage, the induced charge on the surface of the silicon interface, which interfaces charge-generating the electric field may be greatly reduced peak electric field of the PN junction, thereby improving the breakdown voltage smell.

[0004] 美国专利6468837将场板技术运用到RESURF (reduced surface field)器件中,并给出了工艺上的实现步骤,其结构如图2所示。 [0004] U.S. Patent No. 6,468,837 technology to the field plate RESURF (reduced surface field) devices, given the realization step of the process, the structure shown in FIG. 它主要由轻掺杂的第一类导电类型外延层半导体区域100,第一类导电类型的半导体区域102,重掺杂的第一类导电类型的半导体区域101、第二类导电类型的半导体区域103、105,较轻掺杂的第二类导电类型半导体区域104 (Resurf植入区),覆盖在半导体区域104上的场氧区120,延伸长度超过场氧一半长度以上的栅场板110等组成。 It mainly consists of a lightly doped epitaxial layer of first conductivity type semiconductor region 100, a first conductivity type semiconductor region 102, a heavily doped first conductivity type semiconductor region 101, the second conductive type semiconductor region 103, 105, the lighter doped region of a second conductivity type semiconductor type 104 (Resurf implant regions), overlying a semiconductor region 104 of the field oxide regions 120, extending more than half the length of the gate length of field oxide over the field plate 110 and the like composition. 这种结构与普通Resurf LDMOS器件区别主要在于栅极延伸了一段场板,使结边缘表面峰场得到抑制,从而提高了击穿电压。 This general configuration Resurf LDMOS devices differ primarily in the gate field plate extends a period of the edge surface of the junction-field peak is suppressed, thereby improving the breakdown voltage. 然而对于这种普通的平面场板,存在的一个突出问题是场板边界处将会形成高电场峰值,从而限制了击穿电压的进一步提闻。 However, for such a conventional planar field plate, a prominent problem is at the boundary of the field plate will form a high peak electric field, thus limiting the breakdown voltage is further improved smell.

[0005] 为了解决场板边缘高电场峰值的问题,K. Brieger等人在1988年5月发表的文章“最优化场板轮廓的一种解析近似”(IEEE TransElectron Devices, Vol. 35, pp. 684-688)中最早通过理论计算表明当场板下方的氧化层厚度以一定的梯度连续增加时,可以完全消除场板下方的电场峰值,于是提出了斜场板的概念。 [0005] In order to solve the problem of high peak electric field plate edge, K. Brieger et al, published in the May 1988 article, "board outline an optimized field of analytic approximation" (IEEE TransElectron Devices, Vol. 35, pp. when 684-688) by theoretical calculation shows that the earliest oxide layer under the plate on the spot at a constant gradient continuously increases, the peak electric field can be completely eliminated under the field plate, then put forward the concept slant field plate. 然而斜场板虽然可以实现完全均匀的表面电场,但是却难以制造,尤其是和集成电路工艺不兼容。 However, although slant field plate may be completely uniform surface electric field, but it is difficult to manufacture, and especially not compatible with integrated circuit technology. 美国专利753930给出了多阶梯场板构造的LDMOS结构,如图3所示。 U.S. Patent No. 753,930 shows the structure of a multi-stage LDMOS field plate configuration, as shown in FIG. 与常规LDMOS不同的是,在靠近漏端增加了阶梯状的氧化层120和多晶硅场板110,最低一阶的场板又与源端进行电学连接。 Different from the conventional LDMOS is increased near the end of the drain and polysilicon field oxide layer 120 stepped plate 110, a lowest-order field plate electrically connected to the source for another terminal. 该结构下表面漂移区的电场分布更为均匀,耐压特性在一定程度上得到了提升。 Field in the surface of the drift region is more evenly distributed configuration, the withstand voltage characteristic has been improved to some extent. 然而该方法的缺点是需要多个附加掩模版和多步附加工艺来制造多阶梯场板,增加了工艺复杂性,提高了成本。 However, a disadvantage of this method is the need for an additional mask and a plurality of additional multi-step processes for producing multi-step field plate, increases the complexity of the process, increases the costs.

[0006] 美国专利7230313中提出了一种分段场板的横向功率器件结构,如图4所示。 [0006] U.S. Patent No. 7,230,313 proposes a lateral power device structure a segmented field plate, as shown in FIG. 该结构的显著特点是在表面氧化层120上有多段分开一定距离的场板110、112、114、116。 A distinctive feature of the structure is a plurality of segments separated by a distance field plates 110, 112 on the surface of the oxide layer 120. 各场板通过由多电阻连接构成的分压网络被偏置不同的电压,可以使各场板边缘的电场峰值趋于相同,即临界击穿电场,从而使击穿电压得以提高。 Each field plate by being connected to different bias voltages by a plurality of resistor divider network configuration, each of the peak electric field can tend to the same edge of the field plate, i.e. the critical breakdown field, so that the breakdown voltage is improved. 但对这种结构的横向功率器件,分压网络比较复杂且不易于调节。 However, the lateral power device of such a structure, divider network is complex and not easy to adjust.

[0007] 上述的各种结构均是在功率器件表面制备场板来达到调节表面电场的作用,但是像表面多阶梯状、倾斜状场板的制备工艺十分复杂,效果不是非常理想。 [0007] The above-described various structures are prepared in the power field plate surface of the device to achieve regulation of the surface electric field, but as a multi-stepped surface, inclined preparation process is very complicated field plate, the effect is not very satisfactory.

发明内容[0008] 技术问题:本发明的目的是提供另一种横向功率器件中的结终端结构,采用该结构,不仅可以在侧壁实现任意几何尺寸和任意阶梯数的多阶梯场板和任意形状的斜场板的制备,从而充分地发挥场板的降场作用,最大程度地提高击穿特性,同时还可以抑制体内电场,使漂移区浓度的优化值得以提高,从而降低导通电阻,增大工作电流。 [0008] Technical Problem: The purpose of the present invention is to provide a junction termination structure of another lateral power devices, this structure can not only achieve a multi-step field plate of any geometry and any arbitrary number of steps and the side wall preparation slant field plate shape, thereby substantially reducing field play field plate effect, the breakdown characteristics improved maximally, while an electric field can be suppressed in vivo the concentration of the drift region optimized to increase worth, thereby reducing the on-resistance, increased operating current. 此外,该结构制作工艺只需增加一块掩膜版即可实现常规平面场板中很难实现的多阶梯场板和斜场板的制备,其工艺与标准CMOS工艺基本完全兼容,从而降低制造成本。 In addition, the structure prepared by conventional fabrication process by simply adding the field plate plane difficult to achieve a multi-step field plate and the swash plate is a mask field can be realized, which is the basic process and the process is fully compatible with standard CMOS, thereby reducing manufacturing costs .

[0009] 技术方案:本发明的横向功率器件的结终端结构包括衬底区域、一个具有第一类导电类型的半导体区域、一个具有高掺杂浓度的第二类导电类型的半导体区域,二者之间通过一个具有低掺杂浓度的第二类导电类型的半导体区域和一个边侧并列的侧壁氧化层隔开,半导体区域构成了功率器件的漂移区,侧壁氧化层靠近两端光刻淀积第一斜坡形多晶硅场板、第二斜坡形多晶硅场板,该两斜坡形多晶硅场板分别与栅极、漏极电学连接。 [0009] Technical Solution: junction termination structure of the lateral power device of the present invention includes a substrate region, a first conductivity type semiconductor region having a high dopant having a second conductivity type semiconductor region type concentration, both sidewall oxide separated by the second type of conductivity type having a low dopant concentration semiconductor region and a side in parallel between the semiconductor region constitutes the drift region of the power device, close to both ends of the sidewall oxide lithography depositing a first polysilicon field plate ramp-shaped, ramp-shaped second polysilicon field plate, the polysilicon field two ramp-shaped plates are respectively connected to the gate, and a drain electrically.

[0010] 半导体区域作为漂移区的具有低掺杂浓度的第二类导电类型的半导体区域,其浓度为均匀的。 [0010] a second semiconductor region of a conductivity type semiconductor region type having a low doping concentration of the drift region, the concentration thereof uniform.

[0011] 侧壁氧化层位于作为漂移区的半导体区域边侧,其垂直深度超过漂移区厚度,进入衬底区域内部。 [0011] sidewall oxide layer is a semiconductor region side of the drift region, the vertical depth greater than the thickness of the drift region into the interior region of the substrate.

[0012] 第一斜坡形多晶硅场板、第二斜坡形多晶硅场板的垂直深度需要超过作为漂移区的半导体区域的厚度,进入衬底区域内部。 [0012] The first ramp-shaped polysilicon field plate, the vertical depth of the second ramp-shaped polysilicon field plate could be more than the thickness of the semiconductor region of the drift region into the interior region of the substrate.

[0013] 衬底区域为半导体材料,或者为二氧化硅氧化层SOI。 [0013] substrate region of a semiconductor material, or a silica oxide layer SOI.

[0014] 第一斜坡形多晶硅场板、第二斜坡形多晶硅场板还可以为多阶梯状或者多段分开状的分段场板,分段场板是浮空的,或被分压网络偏置不同的电压。 [0014] The first ramp-shaped polysilicon field plate, the second ramp-shaped polysilicon field plate may also be a multi-stage or multistage separate segment-shaped field plate, field plate segment is floating, or the bias voltage divider network different voltages.

[0015] 侧壁氧化层是二氧化硅。 [0015] The sidewall oxide layer is silicon dioxide.

[0016] 所述的横向功率器件的具体形式是横向扩散场效应晶体管LDM0S、横向PN 二极管、横向绝缘栅双极型晶体管LIGBT、或横向晶闸管。 [0016] The particular form of the lateral power device is a lateral field-effect transistor diffusion LDM0S, lateral PN diode, a lateral insulated gate bipolar transistor the LIGBT, or a lateral thyristor.

[0017] 有益效果:本发明所述的侧壁场板结构可采用如下工艺制备。 [0017] Advantageous Effects: Preparation of the following process sidewall field plate structure according to the present invention may be employed. 首先刻蚀并填充侧壁氧化层,这一步可以利用介质隔离工序完成,不需要任何附加掩模版和附加工序,其次光刻场板图形,图形的形状由数值仿真的结果来确定,其深度应当略大于顶层硅的厚度,而后进行多晶硅淀积,形成场板,随后即可按照标准CMOS工艺完成LDMOS的加工。 And etching the first sidewall oxide is filled, this step may be utilized to complete dielectric isolation step, without any additional mask and additional process, followed by lithography field plate pattern, the pattern shape determined by the numerical simulation results, the depth should be slightly larger than the thickness of the top silicon, polycrystalline silicon is deposited and then, forming a field plate, according to the standard CMOS process can then be completed LDMOS processing. 由此可见该工艺是一个和标准CMOS工艺完全兼容的工艺方案,只需增加一次光刻,通过调整掩模版图形,即可完成侧向任意形状的斜场板、任意阶梯的阶梯场板或者各种类型的浮空场板的制作。 This shows that the process is a process, and is fully compatible with standard CMOS process scheme, only one photolithography increases, by adjusting the mask pattern, to complete the field plate laterally obliquely any shape, any step or step plates each field making floating field plate types. 通过该方法制备的器件不仅可调节表面电场,同时可以调节体内电场,达到大幅提高击穿电压的效果,而且漂移区浓度优值也得到了较大提升,ι-v特性更好。 Devices prepared by this method can only adjust the surface electric field, while the electric field may be adjusted in vivo, to achieve a substantial effect of improving the breakdown voltage, and the concentration of the drift region merit has also been greatly improved, ι-v characteristic better.

附图说明 BRIEF DESCRIPTION

[0018] 图I是平面PN结场板结构示意图。 [0018] Figure I is a plan schematic view of PN junction field plate structure.

[0019] 图2是RESURF LDMOS平面场板结构示意图。 [0019] FIG. 2 is a schematic planar structure of a field plate RESURF LDMOS.

[0020] 图3是平面多阶梯场板结构LDMOS示意图。 [0020] FIG. 3 is a plan multi-step field plate structure LDMOS FIG. [0021] 图4是一种改进的分段场板结构横向功率器件结构示意图。 [0021] FIG. 4 is a schematic view of an improved power device structure transversely segmented field plate structure.

[0022] 图5是本发明的具有侧壁斜场板结构LDMOS结构三维视图。 [0022] FIG. 5 is a slant field plate structure LDMOS side wall structure having a three-dimensional view of the present invention. 具有高掺杂浓度的第一类导电类型的半导体区域101构成LDMOS的沟道区,具有高掺杂浓度的第二类导电类型的半导体区域103构成LDMOS的漏端,源端与漏端之间用具有较轻掺杂浓度的第二类导电类型的半导体区域102和侧壁氧化层120并列连接,半导体区域102用作漂移区,侧壁氧化层120内靠近源极和漏极两端光刻淀积多晶硅形成斜坡形场板110、112,场板110与栅极131电学连接,场板112与漏极132电学连接。 Having a high doping concentration of the first conductivity type semiconductor region 101 constituting the channel region of the LDMOS, having a high dopant concentration of the second type conductive type semiconductor region 103 constituting the LDMOS drain terminal, a source terminal and the drain terminal between 120 are connected in parallel with a second type conductivity type having a lighter doped semiconductor region 102 and the concentration of the side wall oxide layer, a semiconductor region 102 serves as a drift region, near the source and drain ends photolithography inner sidewall oxide 120 depositing a polysilicon field plate 110, 112 is formed tapered, field plate 110 is electrically connected to the gate 131, field plate 112 is electrically connected to the drain 132.

[0023] 图6a是本发明的具有侧壁斜场板结构LDMOS的俯视图。 [0023] FIG. 6a is a side wall having a slant field plate structure LDMOS plan view of the present invention.

[0024] 图6b是本发明的具有侧壁斜场板结构LDMOS沿图6a中AB线的截面图。 [0024] FIG 6b is a side wall having a slant field plate structure LDMOS sectional view along the line AB in Figure 6a of the present invention.

[0025] 图6c是本发明的具有侧壁斜场板结构LDMOS沿图6a中CD线的截面图。 [0025] Figure 6c is a side wall having a slant field plate structure LDMOS sectional view taken along line CD in Figure 6a of the present invention.

[0026] 图7a是本发明的具有侧壁斜场板结构横向PN结的俯视图。 [0026] FIG 7a is a plan view of a side wall having a slant field plate laterally PN junction structure of the present invention.

[0027] 图7b是本发明的具有侧壁斜场板结构横向PN结沿图7a中AB线的截面图。 [0027] Figure 7b is a cross-sectional view of a sidewall inclined lateral PN junction field plate structure along line AB of FIG. 7a present invention.

[0028] 图8a是本发明的具有侧壁多阶梯场板结构LDMOS的俯视图。 [0028] Figure 8a is a side wall having a multi-step field plate structure LDMOS plan view of the present invention. 与图6不同的是,两端的侧壁场板分别做成了对称多阶梯状。 FIG 6 is different from the side walls across the field plates are made of a symmetric multi-stepped.

[0029] 图8b是本发明的具有侧壁多阶梯场板结构LDMOS沿图8a中AB线的截面图。 [0029] FIG 8b is a sectional view taken along line AB of FIG. 8a sidewall having a multi-step LDMOS field plate structure according to the present invention.

[0030] 图9a是本发明的具有侧壁浮空场板结构LDMOS的一种形式。 [0030] FIG. 9a form an LDMOS having sidewall floating field plate structure according to the present invention. 与图6不同的是,侧壁场板被做成分段的浮空状,场板间距由源端开始逐渐缩小至漂移区中间,再往漏端逐渐增大形成对称状,各段场板长度和宽度一致。 FIG 6 is different from the sidewall field plate is made of floating-shaped segment, starting from the source field plate spacing to an intermediate tapered end of the drift region, the drain terminal is gradually increased and then further forming a symmetrical shape, each plate segment field same length and width.

[0031] 图9b是图9a沿AB线的截面图。 [0031] 9a 9b is a cross-sectional view taken along line AB of FIG.

[0032] 图IOa是本发明的具有侧壁浮空场板结构LDMOS的另一种形式。 [0032] FIG IOa LDMOS is another form of sidewall having a floating field plate structure according to the present invention. 与图9 一样,边侧场板被做成分段的浮空状,但是各段场板宽度从源端开始渐次减小至漂移区中部,再往漏端方向逐渐增大形成对称状,场板间距不发生变化。 As with FIG. 9, the field side is made floating plate-shaped segments, but each segment field plate width gradually decreases from the beginning to the middle of the source end of the drift region, a drain terminal direction gradually increases and then further forming a symmetrical shape, the field plate spacing does not change.

[0033] 图IOb是图IOa沿AB线的截面图。 [0033] FIG. IOb IOa is a sectional view along the line AB in FIG.

[0034] 图Ila是本发明的具有侧壁斜场板结构LIGBT俯视图。 [0034] FIG Ila sidewall having a slant field plate structure LIGBT a top view of the invention.

[0035] 图Ilb是图Ila沿AB线的截面图。 [0035] FIG Ila Ilb is a sectional view along the line AB.

[0036] 图12是常规Resurf结构和本发明的侧壁斜场板Resurf结构横向功率器件等势线分布、纵向电场分布和击穿电压对比图。 [0036] FIG. 12 is a conventional structure and the sidewall Resurf slant field plate structure Resurf lateral power devices according to the present invention, the distribution of equipotential lines, the longitudinal electric field distribution and breakdown voltage contrast FIG.

[0037] 图13是常规Resurf结构和本发明的侧壁斜场板Resurf结构横向功率器件I_V输出特性曲线图。 [0037] FIG. 13 is a lateral power device I_V output characteristic view of a conventional side wall structure and the swash Resurf Resurf field plate structure of the present invention. 具体实施方式 Detailed ways

[0038] 本发明提供了一种横向功率器件中的结终端结构。 [0038] The present invention provides a terminal structure of a junction of a lateral power device. 图5是该结构的3D视图,图6a是该结构的俯视图,图6b是该结构沿图6a中AB线的截面图,图6c是该结构沿图6a中CD线的截面图。 FIG 5 is a 3D view of the structure, Figure 6a is a top view of the structure of Figure 6b is a sectional view of the structure taken along line AB in Figure 6a, Figure 6c is a sectional view of the structure taken along line 6a of the CD. 可以看出,它是在第一类导电类型的衬底区域100上的硅基中,通过两次高掺杂形成高掺杂浓度的第一类导电类型的半导体区域101,高掺杂浓度的第二类导电类型的半导体区域103,二者通过轻掺杂浓度的第二类导电类型的半导体区域102相连,半导体区域102用做漂移区,同时半导体区域102的侧壁用场氧填充形成与之并列的侧壁氧化层120,侧壁氧化层120垂直延伸到衬底区域100中。 As can be seen, it is the silicon on the first conductivity type in the 100 region of the substrate, it is formed by two highly doped high doping concentration of the first conductivity type semiconductor region 101, heavily doped a second electrical type semiconductor region 103, both by the concentration of the second type of lightly doped conductivity type semiconductor region 102 is connected to the semiconductor region 102 is used as the drift region, while semiconductor region 102 side walls handy oxygen filling formed therewith parallel sidewall oxide layer 120, 120 extend perpendicular to the sidewall oxide regions 100 in the substrate. 在靠近侧壁氧化层120的两端光刻淀积多晶娃形成第一斜坡形多晶娃场板110、第二斜坡形多晶娃场板112,第一斜坡形多晶娃场板110与栅极131电学连接,第二斜坡形多晶硅场板112与漏极132电学连接,第一斜坡形多晶硅场板110、第二斜坡形多晶硅场板112也要垂直延伸到超过衬底区域100的上表面进入衬底区域100内。 Near both ends of the lithographic sidewall oxide layer 120 is deposited forming a first polycrystalline baby doll tapered poly field plate 110, the second ramp-shaped polycrystalline baby field plate 112, a first ramp-shaped polycrystalline baby field plate 110 electrically connected to the gate 131, a second ramp-shaped polysilicon field plate 112 electrically connected to the drain 132, a first ramp-shaped polysilicon field plate 110, the second ramp-shaped polysilicon field plate 112 also extends vertically beyond the area 100 of the substrate enters the area on the surface of the substrate 100. [0039] 横向功率器件的结终端结构包括衬底区域100、一个具有第一类导电类型的半导体区域101、一个具有高掺杂浓度的第二类导电类型的半导体区域103,二者之间通过一个具有低掺杂浓度的第二类导电类型的半导体区域102和一个边侧并列的侧壁氧化层120隔开,半导体区域102构成了功率器件的漂移区,侧壁氧化层120靠近两端光刻淀积第一斜坡形多晶硅场板110、第二斜坡形多晶硅场板112,该两斜坡形多晶硅场板分别与栅极131、漏极132电学连接。 [0039] lateral power device junction termination structure includes a substrate region 100, having a first conductivity type semiconductor region 101, a high dopant concentration having a second electrical type semiconductor region 103, passes between the two 102 and one side of the parallel sidewall oxide layer 120 of a second type conductivity type having a low dopant concentration semiconductor region spaced apart from the semiconductor region 102 constituting a drift region of the power device, the side wall oxide layer 120 close to the light ends depositing a first engraved tapered polysilicon field plate 110, the second ramp-shaped polysilicon field plate 112, the two tapered gate polysilicon field plate 131 respectively, and a drain 132 electrically connected.

[0040] 需要说明的是 [0040] It should be noted

[0041] (I)所述的具有低掺杂浓度的第二类导电类型的半导体区域102的浓度分布是均匀的。 [0041] (I) the concentration distribution of the second electrical type semiconductor region having a low doping concentration of the 102 is uniform.

[0042] (2)所述的侧壁氧化层120的材料为二氧化硅。 Materials [0042] The side wall oxide layer (2) 120 is silica.

[0043] (3)所述的侧壁氧化层120、第一斜坡形多晶硅场板110、第二斜坡形多晶硅场板(112)均需要垂直延伸进入衬底区域100内部,以起到抑制体内电场的作用。 [0043] The sidewall oxide layer according to (3) 120, a first ramp-shaped polysilicon field plate 10, second polysilicon field plate-shaped ramp (112) extending vertically are required into the interior of the substrate region 100 to act to inhibit in vivo the electric field.

[0044] (4)所述的衬底区域100可以是轻掺杂的半导体(体硅),也可以是二氧化硅氧化层(SOI)。 [0044] (4) the substrate region 100 may be lightly doped semiconductor (bulk silicon), silicon dioxide may be an oxide layer (SOI).

[0045] (5)所述的侧壁场板区即第一斜坡形多晶硅场板110、第二斜坡形多晶硅场板112既可以做成侧壁斜坡形,也可以做成侧壁多阶梯形(如图8),还可以做成多种侧壁分段场板类型(如图9、10),分段场板可以为浮空状,也可以被偏置不同的电压。 [0045] a field plate region of the side wall (5) that is ramp-shaped first polysilicon field plate 110, the second ramp-shaped polysilicon field plate 112 may be made of a ramp-shaped side wall, the side walls can also be made multi-stepped (FIG. 8), the side walls can also be made more segment type field plate (9 and 10), the segmented field plate may be in a floating state, it may be different bias voltages.

[0046] (6)所述的侧壁场板结构可以与普通平面场板结合使用,以达到更好的降场效果。 [0046] The structure of the sidewall field plate (6) can be used with generally planar field plate, in order to achieve a better effect of reducing field.

[0047] (7)所述的场板结构还可以用于横向PN 二极管(如图7)、LIGBT(如图11)、横向晶闸管等功率器件,以同时改善器件的击穿特性和导通特性。 [0047] (7) of the field plate structure can also be used for lateral PN diode (FIG. 7), the LIGBT (11), a lateral thyristor power devices, to simultaneously improve the breakdown characteristics and conductive characteristics of the device .

[0048] 本发明的工作原理: [0048] The working principle of the invention:

[0049] 图12是根据初步仿真结果勾勒的常规RESURF结构与侧壁3D斜场板Resurf结构的等势线分布、纵向电场分布和击穿电压对比图。 [0049] FIG. 12 is a conventional RESURF structure equipotential lines with the side wall of the preliminary simulation results outline 3D slant field plate Resurf distribution structure, the longitudinal electric field distribution and breakdown voltage contrast FIG. 两种结构的结构参数相同,而漂移区浓度分布则进行了优化。 Two structures identical structural parameters, the concentration distribution of the drift region is optimized. 由图12a可以看出,对于常规RESURF结构,在漂移区两端的表面等势线密集,中间稀疏,从而导致两端出现非常高的电场峰值,降低了击穿电压。 As can be seen from Figure 12a, for a conventional RESURF structure, the surface of the equipotential lines in the drift region across the dense, intermediate sparse, resulting in very high electric field appearing across the peak, the breakdown voltage is reduced. 而对于图12b中的3D斜场板结构,漂移区等势线分布近乎均匀,表面电场近似为常数,从而使击穿电压得到了大幅度提高。 As for the potential lines in FIG. 12b 3D slant field plate structure, nearly uniform distribution of the drift region and the like, the surface electric field is approximately constant, so that the breakdown voltage has been greatly improved. 图12c为相同的外加偏置条件下漏端下方的纵向电场分布,可以看出,由于场板的屏蔽作用,3D斜场板的纵向电场分布也比常规RESURF结构更为均匀,其顶层硅/埋氧层界面上的峰值电场也较低,这说明3D场板也有改善纵向耐压的效果。 Figure 12c is a longitudinal electric field under the drain terminal of the bias applied under the same conditions of distribution, it can be seen, due to the shielding effect of the field plate, the longitudinal electric field distribution 3D slant field plate is also more uniform than the conventional RESURF structure, which top silicon / peak electric field in the buried oxide layer interface is also low, indicating that 3D field plate breakdown voltage also improved longitudinal effect. 从图12d中可以看出3D斜场板结构较之常规RESURF结构的击穿电压有大幅提升,且漂移区浓度优值也更高。 As can be seen from Figure 12d 3D slant field plate structure than the breakdown voltage of a conventional RESURF structure has increased dramatically, and the concentration of the drift region is also higher merit.

[0050] 图13比较了以上二种结构的IV特性曲线。 [0050] FIG 13 compares the IV characteristics of two or more kinds of structure. 可以看出,3D斜场板结构的线性区电阻远远小于常规RESURF结构,同时其饱和电流也远远高于常规RESURF结构。 As can be seen, the linear region of the resistance 3D slant field plate RESURF structure is much smaller than a conventional structure, while it is much higher than the conventional saturation current RESURF structure. 其原因可以归结于3D场板结构的最优漂移区浓度较之常规RESURF结构得到大幅提升。 The reason for this can be attributed to the optimum concentration of the drift region 3D field plate structure than conventional RESURF structure has been increased dramatically.

[0051] 根据本发明提供的横向功率器件结构,可以制作出特性优良的侧壁斜场板、多阶梯场板、分段场板结构横向功率器件,举例如下: [0051] The structure of the lateral power device of the present invention provided excellent properties can be produced sidewall slant field plate, multi-step field plate, the field plate structure segment lateral power devices, for example as follows:

[0052] I)具有侧壁斜场板的LDM0S,如图5、图6。 [0052] I) having a sidewall inclined LDM0S field plates, as shown in FIG. 6. 它包括第一类导电类型的衬底区域100, 通过两次高掺杂形成高掺杂浓度的第一类导电类型的半导体区域101,高掺杂浓度的第二类导电类型的半导体区域103,分别作为源区和漏区。 It comprises a first conductivity type substrate region 100, a first type of highly doped conductivity type high impurity concentration is formed by two semiconductor region 101, highly-doped second conductivity type semiconductor region concentration type 103, respectively as the source and drain regions. 二者通过轻掺杂浓度的第二类导电类型的半导体区域102相连,半导体区域102用做漂移区,其浓度分布式为均匀的,同时半导体区域102的边侧用场氧进行填充形成与之并列的侧壁氧化层120,侧壁氧化层120与半导体区域101、103相连,并垂直延伸到衬底区域100中。 Both by lightly doping concentration of the second electrical type semiconductor region 102 is connected to the semiconductor region 102 is used as the drift region, which concentration is distributed evenly, while the use-side MOS region 102 is formed to fill in parallel therewith the sidewall oxide layer 120, the side wall oxide layer 120 is connected to the semiconductor regions 101, 103, 100 and extending perpendicular to the substrate region. 在侧壁氧化层120靠近两侧光刻淀积多晶娃形成第一斜坡形多晶娃场板110、第二斜坡形多晶娃场板112,第一斜坡形多晶娃场板110与栅极131电学连接,第二斜坡形多晶娃场板112与漏极132电学连接,第一斜坡形多晶硅场板110、第二斜坡形多晶硅场板112也要延伸到超过衬底区域100的上表面进入衬底区域100内。 Close to the sidewall oxide layer 120 is deposited on both sides of photolithography to form a first polycrystalline baby doll tapered poly field plate 110, the second ramp-shaped polycrystalline baby field plate 112, a first ramp-shaped poly field plate 110 and the baby the gate 131 is electrically connected, the second ramp-shaped polycrystalline baby field plate 112 electrically connected to the drain 132, a first ramp-shaped polysilicon field plate 110, the second ramp-shaped polysilicon field plates 112 also extend into the substrate region exceeding 100 enters the area on the surface of the substrate 100.

[0053] 2)具有侧壁多阶梯场板的LDM0S,如图8所示。 [0053] 2) having a multi-step LDM0S sidewall field plate, as shown in FIG. 它包括第一类导电类型的衬底区域100,通过两次高掺杂形成高掺杂浓度的第一类导电类型的半导体区域101,高掺杂浓度的第二类导电类型的半导体区域103,分别作为源端和漏端。 It comprises a first conductivity type substrate region 100, a first type of highly doped conductivity type high impurity concentration is formed by two semiconductor region 101, highly-doped second conductivity type semiconductor region concentration type 103, respectively as the source and drain ends. 二者通过轻掺杂浓度的第二类导电类型的半导体区域102相连,半导体区域102用做漂移区,其浓度分布式为均匀的,同时半导体区域102的边侧用场氧进行填充形成与之并列的侧壁氧化层120,侧壁氧化层120与半导体区域101、103相连,并垂直延伸到半导体区域100中。 Both by lightly doping concentration of the second electrical type semiconductor region 102 is connected to the semiconductor region 102 is used as the drift region, which concentration is distributed evenly, while the use-side MOS region 102 is formed to fill in parallel therewith the sidewall oxide layer 120, the side wall oxide layer 120 is connected to the semiconductor regions 101, 103, 100 and extends vertically into the semiconductor region. 在侧壁氧化层120的靠近两侧光刻淀积多晶硅形成背靠背多阶梯状的第一阶梯形多晶硅场板110、第二阶梯形多晶硅场板112,第一阶梯形多晶硅场板110与栅极131电学连接,第二阶梯形多晶硅场板112与漏极132电学连接,第一阶梯形多晶硅场板110、第二阶梯形多晶硅场板112也要延伸到超过衬底区域100的上表面进入衬底区域100内。 And the gate polysilicon field plate 110 adjacent to both sides of the sidewall oxide layer 120 is deposited lithographic polysilicon is formed a first back-multi-stepped stepped polysilicon field plate 110, a stepped second polysilicon field plate 112, a first stepped 131 electrically connected to the second stepped polysilicon field plate 112 electrically connected to the drain 132, a first stepped polysilicon field plate 110, a stepped second polysilicon field plate 112 also extends over the upper surface of the substrate 100 into the substrate region 100 insole region.

[0054] 3)具有侧壁分段场板的LDM0S,如图9所示。 [0054] 3) having a side wall segment LDM0S field plate, as shown in FIG. 它包括第一类导电类型的衬底区域100,通过两次高掺杂形成高掺杂浓度的第一类导电类型的半导体区域101,高掺杂浓度的第二类导电类型的半导体区域103,分别作为源端和漏端。 It comprises a first conductivity type substrate region 100, a first type of highly doped conductivity type high impurity concentration is formed by two semiconductor region 101, highly-doped second conductivity type semiconductor region concentration type 103, respectively as the source and drain ends. 二者通过轻掺杂浓度的第二类导电类型的半导体区域102相连,半导体区域102用做漂移区,其浓度分布式为均匀的,同时半导体区域102的边侧用场氧进行填充形成与之并列的侧壁氧化层120,侧壁氧化层120与第一类导电类型的半导体区域101、第二类导电类型的半导体区域103相连,并垂直延伸到半导体区域100中。 Both by lightly doping concentration of the second electrical type semiconductor region 102 is connected to the semiconductor region 102 is used as the drift region, which concentration is distributed evenly, while the use-side MOS region 102 is formed to fill in parallel therewith the sidewall oxide layers 120, 120 and the sidewall oxide layer of the first conductivity type semiconductor region 101, the second conductive type semiconductor region 103 is connected to, and extends vertically into the semiconductor region 100. 在侧壁氧化层120从源端到漏端光刻淀积分段的第一矩形多晶硅场板110、第二矩形形多晶硅场板112、第三矩形多晶硅场板114、第四矩形多晶硅场板116、第五矩形多晶娃场板118、第六矩形多晶娃场板117、第七矩形多晶娃场板115、第八矩形多晶娃场板113、第九矩形多晶硅场板111,分段场板分布呈对称状,场板间间距从源端逐渐缩小到侧壁氧化层120中部,再往漏端方向逐渐增大。 The sidewall oxide layer 120 from the deposition source to the first rectangular segment lithographic polysilicon field plate drain terminal 110, a second polysilicon field plate 112 is rectangular shape, a rectangular third polysilicon field plate 114, fourth plate 116 is a rectangular polysilicon field fifth rectangular field plate 118 polymorph baby, baby polycrystalline sixth rectangular field plate 117, a seventh field baby polycrystalline rectangular plate 115, the eighth rectangular polycrystalline baby field plate 113, a ninth rectangular polysilicon field plate 111, points segment field distribution plate symmetrical shape, spacing gradually decreases from the central source to the sidewall oxide layer is a field plate 120, and then further drain terminal direction gradually increases. 第一矩形多晶硅场板110与栅极131电学连接,第九矩形多晶硅场板111与漏极132电学连接,各段场板均要垂直延伸到超过衬底区域100的上表面进入衬底区域100内。 Rectangular first polysilicon field plate 110 is electrically connected to the gate 131, a ninth rectangular polysilicon field plate 111 electrically connected to the drain 132, field plate segments are to extend vertically beyond the upper surface of the substrate to the region 100 into the substrate region 100 Inside.

[0055] 4)具有另一种形式侧壁分段场板的LDM0S,如图10所示。 [0055] 4) having a side wall segment LDM0S another form field plates, as shown in FIG. 它包括第一类导电类型的衬底区域100,通过两次高掺杂形成高掺杂浓度的第一类导电类型的半导体区域101,高掺杂浓度的第二类导电类型的半导体区域103,分别作为源端和漏端。 It comprises a first conductivity type substrate region 100, a first type of highly doped conductivity type high impurity concentration is formed by two semiconductor region 101, highly-doped second conductivity type semiconductor region concentration type 103, respectively as the source and drain ends. 二者通过轻掺杂浓度的第二类导电类型的半导体区域102相连,半导体区域102用做漂移区,其浓度分布式为均匀的,同时半导体区域102的边侧用场氧进行填充形成与之并列的侧壁氧化层120,侧壁氧化层120与半导体区域101、103相连,并垂直延伸到半导体区域100中。 Both by lightly doping concentration of the second electrical type semiconductor region 102 is connected to the semiconductor region 102 is used as the drift region, which concentration is distributed evenly, while the use-side MOS region 102 is formed to fill in parallel therewith the sidewall oxide layer 120, the side wall oxide layer 120 is connected to the semiconductor regions 101, 103, 100 and extends vertically into the semiconductor region. 在侧壁氧化层120内从源端到漏端光刻淀积分段的第一矩形多晶硅场板110、第二矩形多晶硅场板112、第三矩形多晶娃场板114、第四矩形多晶娃场板116、第五矩形多晶娃场板115、第六矩形多晶娃场板113、第七矩形多晶硅场板111,分段场板分布呈对称状,场板间间距不变,场板自身宽度从源端逐渐缩小至侧壁氧化层120中部,再往漏端方向逐渐增大。 In the side wall oxide layer 120 from the source to the drain terminal of the first polysilicon field plate lithography rectangular segment 110 is deposited, a second polysilicon field plate 112 is rectangular, the rectangular third polycrystalline baby field plate 114, a fourth polycrystalline rectangular baby field plate 116, the fifth field baby polycrystalline rectangular plate 115, a sixth field baby polycrystalline rectangular plate 113, a seventh rectangular polysilicon field plate 111, distribution plate segment field symmetrical shape, changing the spacing between the field plate, field plate itself width tapers from the source to the middle of the sidewall oxide layer 120, and then further drain terminal direction gradually increases. 第一矩形多晶硅场板110与栅极131电学连接,第七矩形多晶硅场板111与漏极132电学连接,各段场板均要垂直延伸到超过衬底区域100的上表面进入衬底区域100内。 Rectangular first polysilicon field plate 110 is electrically connected to the gate 131, a seventh rectangular polysilicon field plate 111 electrically connected to the drain 132, field plate segments are to extend vertically beyond the upper surface of the substrate to the region 100 into the substrate region 100 Inside.

[0056] 需要说明的是,本发明提出的横向功率晶体管结构除了可以应用于上面的LDMOS器件外,还可用于横向扩散PN结、横向晶闸管等其它未列出的横向功率器件,侧壁场板类型可以根据实际需要进行调整,或者与平面场板进行配合使用,以达到更佳的电场调制效果O [0056] Incidentally, the lateral power transistor structure proposed by the present invention may be applied in addition to the above LDMOS device, the PN junction can be used for lateral diffusion, lateral thyristor and other lateral power device is not listed, the sidewall field plate type can be adjusted according to actual needs, or for use with planar field plate, the field in order to achieve a better modulation effect O

Claims (8)

1. 一种横向功率器件的结终端结构,其特征是:它包括衬底区域(100)、一个具有第一类导电类型的半导体区域(101)、一个具有高掺杂浓度的第二类导电类型的半导体区域(103),二者之间通过一个具有低掺杂浓度的第二类导电类型的半导体区域(102)和一个侧壁氧化层(120)隔开,第二类导电类型的半导体区域(102)构成了功率器件的漂移区,侧壁氧化层(120)靠近两端光刻淀积第一斜坡形多晶硅场板(110)、第二斜坡形多晶硅场板(112),该两斜坡形多晶硅场板分别与栅极(131)、漏极(132)电学连接。 A junction termination structure of the lateral power device, characterized in that: it comprises a substrate region (100), a first conductivity type semiconductor region (101) having a high dopant concentration of the second conductivity type a second electrical type semiconductor region (102) and a side wall oxide layer (120) of the semiconductor region (103) type, having therebetween through a low dopant concentration spaced apart from, the second conductive type semiconductor region (102) constitutes the drift region of the power device, the side wall oxide layer (120) near a first tapered ends photolithography deposited polysilicon field plate (110), a second ramp-shaped polysilicon field plate (112), the two ramp-shaped polysilicon field plate, the drain electrode (132) electrically connected to the gate (131), respectively.
2.根据权利要求I所述的横向功率器件的结终端结构,其特征是:第二类导电类型的半导体区域(102)作为漂移区的具有低掺杂浓度的第二类导电类型的半导体区域,其浓度为均匀的。 2. A termination structure according to claim I of the junction of the lateral power device, characterized in that: a second electrical type semiconductor region (102) as the second electrical type semiconductor region having a low doping concentration of the drift region concentration uniform.
3.根据权利要求I所述的横向功率器件的结终端结构,其特征是:侧壁氧化层(120)位于作为漂移区的第二类导电类型的半导体区域(102)边侧,其垂直深度超过漂移区厚度,进入衬底区域(100)内部。 The junction termination structure I according to claim lateral power device, characterized in that: the side wall oxide layer (120) located on a second side based semiconductor region (102) of a conductivity type drift region, the vertical depth thickness than the drift region into the substrate region (100) inside.
4.根据权利要求I或2所述的横向功率器件的结终端结构,其特征是:第一斜坡形多晶硅场板(110)、第二斜坡形多晶硅场板(112)的垂直深度需要超过作为漂移区的第二类导电类型的半导体区域(102)的厚度,进入衬底区域(100)内部。 The junction termination structure I or lateral power device according to claim 2, characterized in that: a first tapered polysilicon field plate (110), a second ramp-shaped polysilicon field plate (112) exceeds a required vertical depth the thickness of the second type semiconductor region (102) of the conductivity type of the drift region into the substrate region (100) inside.
5.根据权利要求4所述的横向功率器件,其特征是:衬底区域(100)为半导体材料,或者为二氧化硅氧化层SOI。 5. A lateral power device according to claim 4, characterized in that: a substrate region (100) of a semiconductor material, or a silica oxide layer SOI.
6.根据权利要求4所述的横向功率器件的结终端结构,其特征是:第一斜坡形多晶硅场板(110)、第二斜坡形多晶硅场板(112)还可以为多阶梯状或者多段分开状的分段场板,分段场板是浮空的,或被分压网络偏置不同的电压。 The junction termination structure of the lateral power device as claimed in claim 4, characterized in that: a first tapered polysilicon field plate (110), a second ramp-shaped polysilicon field plate (112) may also be a multi-stage or multistage separate segment-shaped field plate segmented field plate is floating, or the partial pressure of different network bias voltage.
7.根据权利要求I所述的横横向功率器件的结终端结构,其特征是:侧壁氧化层(120)是二氧化硅。 According to claim I of the cross-junction termination structure of the lateral power device, characterized in that: the side wall oxide layer (120) is silica.
8.根据权利要求I所述的横向功率器件的结终端结构,其特征是:所述的横向功率器件的具体形式是横向扩散场效应晶体管LDM0S、横向PN 二极管、横向绝缘栅双极型晶体管LIGBT、或横向晶闸管。 8. A junction termination structure according to claim I of the lateral power device, characterized in that: the specific form of the lateral power device is a lateral field-effect transistor diffusion LDM0S, lateral PN diode, a lateral insulated gate bipolar transistor LIGBT or a lateral thyristor.
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