TW202137334A - Power device having lateral insulated gate bipolar transistor (ligbt) and manufacturing method thereof - Google Patents

Abstract

The present invention provides a power device which is formed on a semiconductor substrate. The power device is configured to operably drive a motor. The power device includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode, and a clamp diode . The PN diode is connected to the LIGBT in parallel. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a collector and a gate of the LIGBT, to clamp a gate voltage applied to the gate not higher than a predetermined voltage threshold.

Description

Power element with laterally insulated gate bipolar transistor and its manufacturing method

The present invention relates to a power device, in particular to a power device with a lateral insulated gate bipolar transistor (LIGBT). The present invention also relates to the manufacturing method of the power device.

1A and 1B show a schematic top view and a schematic cross-sectional view of a power device (power device 100) with a lateral insulated gate bipolar transistor (LIGBT) in the prior art. The power element 100 is used to control the flywheel current in the flywheel motor; wherein the flywheel current flows through the power element 100 to drive the flywheel motor. Among them, the flywheel motor is used to control a flywheel to store rotational kinetic energy in the rotation of the flywheel, which is well known to those with ordinary knowledge in the art, and will not be repeated here. Generally speaking, the power device 100 includes a plurality of LIGBTs (represented by a lateral insulated gate bipolar transistor LIGBT1 in FIGS. 1A and 1B) connected in parallel with each other, and a PN diode.

As shown in FIGS. 1A and 1B, the power device 100 is formed on a semiconductor substrate 11, which includes a lateral insulated gate bipolar transistor LIGBT1 and a PN diode PN1. Fig. 1B shows a schematic cross-sectional view of the section line AA' in Fig. 1A. The PN diode PN1 includes a first field oxide region 121, a first N-type region 131, a first N-type extension region 141, a first P-type region 151, a gate electrode 161, a reverse end 171, and a forward end 181; The first N-type region 131, the first N-type extension region 141, the first P-type region 151, the reverse end 171 and the forward end 181 are all formed in an epitaxial layer on the first insulating underlayer 12. The first insulating structure ISO1 includes a first insulating underlayer 12 and a first insulating sidewall 123, wherein the first insulating underlayer 12 is formed on the semiconductor substrate 11 and connected to the semiconductor substrate 11. The first insulating structure ISO1 is under the upper surface of the epitaxial layer, and encloses the PN diode PN1 in a closed manner, so that the PN diode PN1 is under the upper surface of the epitaxial layer to electrically isolate other components.

The lateral insulated gate bipolar transistor LIGBT1 is formed on the semiconductor substrate 11. As shown in FIGS. 1A and 1B, the lateral insulated gate bipolar transistor LIGBT1 includes a second field oxide region 122, a second N-type region 132, and a second The N-type extension region 142, the second P-type region 152, the gate 162, the drain electrode 172, the emitter 182, and the P-type contact electrode 184; wherein, the second N-type region 132, the second N-type extension region 142, and the second The P-type region 152, the drain electrode 172, the emitter electrode 182, and the P-type contact electrode 184 are formed in the epitaxial layer on the second insulating bottom layer 12'. The second insulating structure ISO2 includes a second insulating bottom layer 12' and a second insulating sidewall 124, wherein the second insulating structure ISO2 is under the upper surface of the epitaxial layer, and encloses the lateral insulated gate bipolar transistor LIGBT1 in a closed manner, so that the lateral The insulated gate bipolar transistor LIGBT1 is under the upper surface of the epitaxial layer to electrically isolate other components. As shown in FIG. 1A, the third insulating side wall 125 forms a ring-shaped closed side wall, which encloses the first insulating side wall 123 and the second insulating side wall 124, that is, the ring formed by enclosing the power element 100 in the third insulating side wall 125形closed in the side wall.

1C and 1D respectively show schematic diagrams of circuit symbols and electrical characteristic curves of the power device 100. The operating mechanism of the laterally insulated gate bipolar transistor LIGBT1 is shown by the circuit symbol of the thick black solid line in Figure 1B, and refer to Figures 1C and 1D. The gate 162 (gate G) is used to control the emitter 182 (radiation). E), the base current in the PNP bipolar junction transistor (BJT) formed by the second N-type extension region 142 and the second P-type region 152 conducts the lateral insulated gate bipolar transistor LIGBT1, by designing the base width and concentration, can determine the magnification of the on-current IC to obtain the best on-voltage and reduce power loss. The base current of the lateral insulated gate bipolar transistor LIGBT1 is controlled by the gate voltage, that is, the voltage applied to the gate 162. As the gate voltage increases, the base current increases proportionally to the emitter current.

When the laterally insulated gate bipolar transistor LIGBT1 is used in motor drive, it needs to pass the short circuits test. The test method is to apply the lateral insulated gate bipolar transistor LIGBT1 to the gate 162 (gate The voltage of G) is increased to the maximum supply voltage (usually 15-20V), and the voltage applied to the emitter 182 (emitter E) is applied to the bulk voltage, such as but not limited to 400V. At this time, IC reaches the maximum current because of the conduction current flowing through the drain 172 (drain C). When the maximum on-current IC passes through the resistor Re, it is easy to trigger the parasitic NPNBJT composed of the second N-type region 132, the second P-type region 152 and the drain 172 in the lateral insulated gate bipolar transistor LIGBT1 to turn on, triggering the parasitic The PNPN latch-up effect in the laterally insulated gate bipolar transistor LIGBT1 causes damage to the high-voltage component 100. An excessively high on-current IC will increase the risk of damage to the high-voltage component 100. Therefore, the maximum current of the on-current IC is appropriately limited to reduce the probability of triggering the latch-up effect.

The traditional method of controlling the base current to limit the on-current IC is to control the voltage applied to the gate 162 to avoid excessive voltage changes applied to the gate 162. The method is usually to use the voltage stabilizing circuit in another gate drive circuit to suppress the abnormally increased voltage source. This method can effectively control the unstable problem from the voltage source, but for the gate-emitter capacitance Cge caused by an external short circuit If the induced voltage is too large, the effect is limited. As shown in Figure 1C, because when the short circuit test is performed from the outside, the voltage applied to the emitter 182 will be raised when the high voltage of other phases contact the phase to be tested, causing a surge (as shown in Figure 1C, the signal waveform next to the emitter E) As shown in Fig. 1D, the voltage applied to the gate G (as shown in Fig. 1C, the signal waveform next to the gate G) rises as shown in Fig. 1D through the induction of the gate-emitter capacitance Cge. The base current and the on-current IC greatly increase, and the probability that the PNPN latch-up effect in the laterally insulated gate bipolar transistor LIGBT1 is triggered is greatly increased.

In view of this, the present invention addresses the above-mentioned shortcomings of the prior art, and proposes a power device with a laterally insulated gate bipolar transistor and a manufacturing method thereof, which can reduce the probability of the latch-up effect of the power device 100 and improve the power device 100 The scope of application.

From one point of view, the present invention provides a power device formed on a semiconductor substrate for driving a motor, including: a lateral insulated gate bipolar transistor (LIGBT); a PN A diode is connected in parallel with the horizontal insulated gate bipolar transistor; and a clamping diode has a clamp forward end and a clamp reverse end, which are respectively electrically connected to the horizontal insulated gate bipolar transistor A drain and a gate of the transistor are used to limit the voltage of a gate applied to the gate not to be higher than a predetermined voltage threshold.

From another point of view, the present invention provides a power device manufacturing method, wherein the power device is formed on a semiconductor substrate for driving a motor, and the power device manufacturing method includes: forming a laterally insulated gate bipolar transistor (lateral insulated gate bipolar transistor, LIGBT); forming a PN diode, which is connected in parallel with the lateral insulated gate bipolar transistor; and forming a clamping diode with a clamping forward end and a clamping reverse The forward ends are respectively electrically connected to a drain and a gate of the horizontal insulated gate bipolar transistor to limit the gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

In a preferred embodiment, the PN diode includes: a first N-type region formed in an epitaxial layer on the semiconductor substrate; a first P-type region formed in the first N-type region A first N-type extension region formed in the first N-type region, and the first N-type extension region and the first P-type region are separated by the first N-type region; a first The reverse end, which has an N-type conductivity type, is formed in the first N-type extension region to serve as an electrical contact for the first N-type extension region; and a first forward end has a P-type conductivity type , Formed in the first P-type region, used as an electrical contact of the first P-type region.

In a preferred embodiment, the laterally insulated gate bipolar transistor includes: a second N-type region formed in the epitaxial layer on the semiconductor substrate; and a second P-type region formed in the epitaxial layer on the semiconductor substrate The second N-type region; the drain, which has an N-type conductivity type, is formed in the second P-type region; a P-type contact is formed in the second P-type region to serve as the second P Electrical contacts of the type region; the gate is formed on the epitaxial layer, and part of the gate is connected to the second P-type region; a second N-type extension region is formed on the second N In the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region; and an emitter having a P-type conductivity type formed in the second N-type extension region .

In a preferred embodiment, the clamping diode system-Zener diode includes: a third P-type region formed in the epitaxial layer on the semiconductor substrate; and a second forward direction The terminal has a P-type conductivity type and is formed in the third P-type region to serve as an electrical contact between the clamping forward terminal and the third P-type region; a third N-type extension region is formed in the In the third P-type region; and a second reverse end, having an N-type conductivity, formed in the third N-type extension region, used as the clamp reverse end and the third N-type extension region The electrical contacts.

In a preferred embodiment, the Zener diode further includes an N-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the N-type adjustment region is on the upper surface The upper part is between the third P-type region and the third N-type extension region for adjusting the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region.

In a preferred embodiment, the Zener diode further includes a P-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the P-type adjustment region is on the upper surface The upper part is between the third P-type region and the third N-type extension region for adjusting the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region.

In a preferred embodiment, the Zener diode further includes an electrostatic discharge (ESD) protection zone, which has an N-type conductivity and is formed under the upper surface of the epitaxial layer and connected to the upper surface , And the static electricity protection area is between the third N-type extension area and the second forward end on the upper surface, and the static electricity protection area is used to interact with the third P-type area and the third N-type extension The area forms an NPN transistor, wherein the static electricity protection area is electrically connected to the second forward end.

In a preferred embodiment, the first N-type extension region, the second N-type extension region, and the third N-type extension region are formed simultaneously by the same lithography process step and the ion implantation process step; Wherein the first P-type region and the second P-type region are formed by the same lithography process step and ion implantation process step simultaneously; wherein the first reverse end, the drain and the second reverse end are formed by the same The lithography process steps are formed at the same time as the ion implantation process steps; wherein the first forward end, the emitter, the P-type contact pole, and the second forward end are formed by the same lithography process step and ion implantation process. The process steps are formed at the same time.

Detailed descriptions are given below by specific embodiments, so that it will be easier to understand the purpose, technical content, features, and effects of the present invention.

The foregoing and other technical content, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiment with reference to the drawings. The drawings in the present invention are all schematic, and are mainly intended to show the process steps and the upper and lower order relationships between the layers. As for the shape, thickness, and width, they are not drawn according to scale.

2A-2B show schematic diagrams of an embodiment of the power device according to the present invention. The power device 200 according to the present invention is formed on the semiconductor substrate 21 for driving a motor, and includes a laterally insulated gate bipolar transistor LIGBT2, a PN diode PN2, and a clamp diode (in this embodiment, the same Nano diode ZD1 is used as a clamping diode). As shown in FIGS. 2A and 2B, the power device 200 is formed on the semiconductor substrate 21, which includes a laterally insulated gate bipolar transistor LIGBT2, a PN diode PN2, and a Zener diode ZD1. Among them, the Zener diode ZD1 is used as a clamping diode to limit the gate voltage applied to the gate 262 of the laterally insulated gate bipolar transistor LIGBT2 not to be higher than the preset voltage threshold to avoid triggering the bolt Locking effect, while protecting the power element 200.

FIG. 2B shows a schematic cross-sectional view of the section line BB' in FIG. 2A. In the power element 200, the coupling manner of the lateral insulated gate bipolar transistor LIGBT2, the PN diode PN2, and the Zener diode ZD1 is as shown in the small diagram of the circuit symbol in FIG. 2A. In the small diagram of the circuit symbol, the horizontal insulated gate bipolar transistor LIGBT2 has gate G, emitter E and drain C; PN diode PN2 has forward end F1 and reverse end R1; Zener diode ZD1 has a forward end F2 and a reverse end R2. The PN diode PN2 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT2; the Zener diode ZD1 is electrically connected between the gate G and the drain C of the lateral insulated gate bipolar transistor LIGBT2. Among them, the drain C and emitter E of the laterally insulated gate bipolar transistor LIGBT2 are respectively electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN2; the forward end of the Zener diode ZD1 F2 and the reverse terminal R2 are respectively electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT2.

According to the present invention, the power element 200 is not limited to only having a single lateral insulated gate bipolar transistor LIGBT2, and can also be composed of two or more lateral insulated gate bipolar transistors in parallel. According to the present invention, the power device 200 may also include a plurality of PN diodes. In a preferred embodiment, the number of PN diodes in the power device 200 is less than the number of the lateral insulated gate bipolar transistor LIGBT2. .

Wherein, the PN diode PN2 includes a first field oxide region 221, a first N-type region 231, a first N-type extension region 241, a first P-type region 251, a gate 261, a first reverse end 271, and a first顺向端281。 The forward end 281. The bottom and side surfaces of the PN diode PN2 are surrounded by the first insulating structure ISO3. The first insulating structure ISO3 includes a first insulating bottom layer 22 and a first insulating sidewall 223.

Wherein, the first N-type region 231 is formed in the epitaxial layer EPI on the semiconductor substrate 21. The first P-type region 251 is formed in the first N-type region 231. The first N-type extension region 241 is formed in the first N-type region 231, and the first N-type extension region 241 and the first P-type region 251 are separated by the first N-type region 231. The first reverse end 271 has an N-type conductivity type and is formed in the first N-type extension region 241 to serve as an electrical contact of the first N-type extension region 241. The first forward end 281 has a P-type conductivity type and is formed in the first P-type region 251 to serve as an electrical contact of the first P-type region 251.

The lateral insulated gate bipolar transistor LIGBT2 is formed on the semiconductor substrate 21. As shown in FIGS. 2A and 2B, the lateral insulated gate bipolar transistor LIGBT2 includes a second field oxide region 222, a second N-type region 232, and a second The N-type extension region 242, the second P-type region 252, the gate 262, the drain 272, the emitter 282, and the P-type contact 284. The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT2 are surrounded by the second insulating structure ISO4. The second insulating structure ISO4 includes a second insulating bottom layer 22' and a second insulating sidewall 224. When the horizontal insulated gate bipolar transistors LIGBT2 are plural, they are electrically connected in parallel with each other, that is, the gate 262, drain 272, emitter 282 and P-type contacts in different horizontal insulated gate bipolar transistors LIGBT2 The poles 284 are electrically connected to each other correspondingly, respectively.

Wherein, the second N-type region 232 is formed in the epitaxial layer EPI on the semiconductor substrate 21. The second P-type region 252 is formed in the second N-type region 232. The drain 272 has an N-type conductivity type and is formed in the second P-type region 252. The P-type contact electrode 284 is formed in the second P-type region 252 to serve as an electrical contact of the second P-type region 252. The gate 262 is formed on the epitaxial layer, and part of the gate is connected to the second P-type region. The second N-type extension region is formed in the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region. The emitter has a P-type conductivity and is formed in the second N-type extension region.

The Zener diode ZD1 is formed on the semiconductor substrate 21. As shown in FIGS. 2A and 2B, the Zener diode ZD1 includes a third field oxide region 227, a fourth field oxide region 228, a third N-type region 233, and a Three N-type extension regions 243, a third P-type region 253, a second reverse end 273, and a second forward end 285. The bottom and side surfaces of the Zener diode ZD1 are surrounded by the third insulating structure ISO5. The third insulating structure ISO5 includes a third insulating bottom layer 22" and a third insulating sidewall 225.

Wherein, the third P-type region 253 is formed in the epitaxial layer EPI on the semiconductor substrate 21. The second forward end 285 has a P-type conductivity and is formed in the third P-type region 253 to serve as a clamp forward end and an electrical contact point for the third P-type region 253. The third N-type extension region 243 is formed in the third P-type region 253. The second reverse end 273 has an N-type conductivity type and is formed in the third N-type extension 243 to serve as a clamping reverse end and an electrical contact for the third N-type extension 243.

As shown in FIGS. 2A and 2B, the fourth insulating side wall 226 forms a ring-shaped closed side wall, enclosing the first insulating side wall 223, the second insulating side wall 224, and the third insulating side wall 225, that is, enclosing the power element 200 in the first insulating side wall. In the ring-shaped closed sidewall formed by the four insulating sidewalls 226.

Among them, the first insulating underlayer 22, the second insulating underlayer 22', and the second insulating underlayer 22" are formed on the semiconductor substrate 21. The semiconductor substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. Semiconductor substrate. For example, a silicon dioxide layer is formed on the semiconductor substrate 21, partly serving as the first insulating underlayer 22, another part as the second insulating underlayer 22', and another part as the third insulating underlayer 22". On the silicon dioxide layer, for example, an N-type epitaxial layer is formed, part of which is used as the first N-type region 231, the other part is used as the second N-type region 232, and the other part is used as the third N-type region 233. The aforementioned semiconductor substrate 21, the silicon dioxide layer and the N-type epitaxial layer can be realized by using silicon on insulator (SOI) wafers, which are well known to those with ordinary knowledge in the art and will not be repeated here. .

The first insulating sidewall 223, the second insulating sidewall 224, the third insulating sidewall 225, and the fourth insulating sidewall 226 are, for example, but not limited to, the same deep trench etching process steps are used to form deep trenches at the same time; and the same deposition process steps are used to simultaneously insulate A material, such as but not limited to silicon dioxide, is deposited in the aforementioned deep trench to form the first insulating sidewall 223, the second insulating sidewall 224, the third insulating sidewall 225, and the fourth insulating sidewall 226. And the first insulating sidewall 223, the second insulating sidewall 224, the third insulating sidewall 225, and the fourth insulating sidewall 226 are connected to the silicon dioxide layer connected to the semiconductor substrate 21 below, so as to form a closed epitaxial layer. Range. Among them, in a preferred embodiment, the bottom and side surfaces of the PN diode PN2 are surrounded by the first insulating structure ISO3; the bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT2 are surrounded by the second insulating structure ISO4 ; And the bottom and side surfaces of the Zener diode ZD1 are surrounded by the third insulating structure ISO5.

Please continue to refer to FIGS. 2A and 2B, where the first N-type extension region 241, the second N-type extension region 242, and the third N-type extension region 243 are, for example, but not limited to, the same lithography process steps, and the first N-type extension region is defined at the same time. Type extension region 241, the second N-type extension region 242 and the third N-type extension region 243; and by the same ion implantation process steps, at the same time N-type impurities are implanted in the form of accelerated ions by the aforementioned The region defined by the lithography process steps to form a first N-type extension region 241, a second N-type extension region 242, and a third N-type extension region 243. The first N-type extension region 241, the second N-type extension region 242, and the third N-type extension region 243 have N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under the upper surface of the N-type epitaxial layer. Connect to the upper surface.

The first field oxide region 221, the second field oxide region 222, the third field oxide region 227, and the fourth field oxide region 228 are formed on the upper surface of the aforementioned N-type epitaxial layer at the same time, for example but not limited to the same oxidation process steps. And connected to the upper surface. The first field oxide region 221, the second field oxide region 222, the third field oxide region 227, and the fourth field oxide region 228 are not limited to the local oxidation of silicon (LOCOS) structure as shown in FIG. 2B. It is a shallow trench isolation (STI) structure. As shown in FIG. 2A, the first field oxide region 221, the second field oxide region 222, the third field oxide region 227, and the fourth field oxide region 228 are viewed from the top view, for example, are annular closed structures. Wherein, the first field oxide region 221, the second field oxide region 222, and the third field oxide region 227 surround the reverse end 271, the emitter 282, and the reverse end 273, respectively.

The first P-type region 251 and the second P-type region 252 are, for example, but not limited to, by the same lithography process step, while defining the regions of the first P-type region 251 and the second P-type region 252; and are implanted by the same ion In the process step, P-type impurities are implanted in the form of accelerated ions into the region defined by the aforementioned lithography process step to form the first P-type region 251 and the second P-type region 252. The first P-type region 251 and the second P-type region 252 have a P-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under and connected to the upper surface of the N-type epitaxial layer. As shown in FIG. 2A, the first P-type region 251 and the second P-type region 252 are viewed from the top view, for example, are annular closed regions, which surround the first field oxide region 221 and the second field oxide region 222, respectively.

As shown in FIG. 2A, the gate electrode 261 and the gate electrode 262 are viewed from the top view, for example, both are annular closed areas. As seen from the top view of FIG. 2A, the gate electrode 261 is formed and contacts a part of the first field oxide region 221 and surrounds other parts of the first field oxide region 221. From the top view of FIG. 2A, the gate electrode 262 is formed and in contact with a part of the second field oxide region 222 and surrounds other parts of the second field oxide region 222.

The gate 261 and the gate 262 are, for example, but not limited to, simultaneously formed by the same gate process step. Among them, the gate 261 and the gate 262 respectively include, for example, a dielectric layer, a conductive layer, and a spacer layer, which are well known to those with ordinary knowledge in the art. Do not repeat it. Therefore, the gate process steps include process steps such as lithography and oxidation to form a dielectric layer; process steps such as lithography and deposition to form a conductive layer; and process steps such as deposition and etching to form a spacer layer

The first forward end 281, the emitter 282, the P-type contact electrode 284, and the second forward end 285 are, for example, but not limited to, the same lithography process steps, and the first forward end 281, the emitter 282, and the P-type are defined at the same time. The area of the contact electrode 284 and the second forward end 285; and by the same ion implantation process step, P-type impurities are implanted in the form of accelerated ions into the area defined by the aforementioned lithography process step to A first forward end 281, an emitter 282, a P-type contact pole 284, and a second forward end 285 are formed. The first forward end 281, the emitter 282, the P-type contact electrode 284, and the second forward end 285 have P-type conductivity, and are formed in the first P-type region 251, the second N-type extension region 242, and the second P-type region, respectively. The type region 252 and the third P type region 253 are located under and connected to the upper surface of the N-type epitaxial layer. As shown in FIG. 2A, the first forward end 281, the P-type contact electrode 284, and the second forward end 285 are seen from the top view, for example, they are all ring-shaped closed areas, which respectively surround the gate electrode 261, the drain electrode 272, and the fourth Field oxidation zone 228.

The first reverse end 271, the drain 272, and the second reverse end 273 are, for example, but not limited to, the same lithography process steps (including the gate 262 as a mask), and the first reverse end 271 and the drain are defined at the same time 272 and the second inverted end 273; and by the same ion implantation process step, at the same time, N-type impurities are implanted in the form of accelerated ions into the region defined by the aforementioned lithography process step to form the first A reverse end 271, a drain 272, and a second reverse end 273. The first reverse terminal 271, the drain electrode 272, and the second reverse terminal 273 have an N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under and connected to the upper surface of the N-type epitaxial layer. As shown in FIG. 2A, the drain electrode 272 is viewed from the top view, for example, is a ring-shaped closed area surrounding the gate electrode 262.

The present invention is superior to the prior art. In this embodiment, the Zener diode ZD1 can not only limit the voltage applied to the gate, not higher than the preset voltage threshold; it can also prevent the gate-emitter capacitance The Cge induced voltage is too large, which causes the voltage applied to the gate to be too high, which prevents the base current and the on-current IC from increasing, thereby avoiding the PNPN latching effect in the lateral insulated gate bipolar transistor LIGBT1 from being triggered. In addition, the Zener diode ZD1 is formed by using the same lithography process steps and the same ion implantation process steps as the lateral insulated gate bipolar transistor LIGBT2, without additional manufacturing cost.

3A-3B show schematic diagrams of another embodiment of the power device according to the present invention. As shown in FIGS. 3A and 3B, the power device 300 is formed on the semiconductor substrate 31, which includes a lateral insulated gate bipolar transistor LIGBT3, a PN diode PN3, and a Zener diode ZD2. Among them, the Zener diode ZD2 is used as a clamping diode to limit the gate voltage applied to the gate of the laterally insulated gate bipolar transistor LIGBT3 not to be higher than the preset voltage threshold to avoid triggering the latch Effect, while protecting the power element 300.

Fig. 3B shows a schematic cross-sectional view of the section line CC' in Fig. 3A. In the power element 300, the coupling manner of the laterally insulated gate bipolar transistor LIGBT3, the PN diode PN3, and the Zener diode ZD2 is as shown in the small diagram of the circuit symbol in FIG. 3A. In the small diagram of the circuit symbol, the horizontal insulated gate bipolar transistor LIGBT3 has gate G, emitter E and drain C; PN diode PN3 has forward end F1 and reverse end R1; Zener diode ZD2 has a forward end F2 and a reverse end R2. The PN diode PN3 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT3; the Zener diode ZD2 is electrically connected between the gate G and the drain C of the lateral insulated gate bipolar transistor LIGBT3. Among them, the drain C and emitter E of the laterally insulated gate bipolar transistor LIGBT3 are respectively electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN3; the forward end of the Zener diode ZD2 F2 and the reverse end R2 are respectively electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT3.

Wherein, the PN diode PN3 includes a first field oxide region 321, a first N-type region 331, a first N-type extension region 341, a first P-type region 351, a gate 361, a first reverse end 371, and a first Straight end 381. The bottom and side surfaces of the PN diode PN3 are surrounded by the first insulating structure ISO6. The first insulating structure ISO6 includes a first insulating bottom layer 32 and a first insulating sidewall 323.

The lateral insulated gate bipolar transistor LIGBT3 is formed on the semiconductor substrate 31. As shown in FIGS. 3A and 3B, the lateral insulated gate bipolar transistor LIGBT3 includes a second field oxide region 322, a second N-type region 332, and a second The N-type extension region 342, the second P-type region 352, the gate 362, the drain 372, the emitter 382, and the P-type contact 384. The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT3 are surrounded by the second insulating structure ISO7. The second insulating structure ISO7 includes a second insulating bottom layer 32' and a second insulating sidewall 324. When the horizontal insulated gate bipolar transistors LIGBT3 are plural, they are electrically connected in parallel with each other, that is, the gate 362, drain 372, emitter 382, and P-type contacts in different horizontal insulated gate bipolar transistors LIGBT3 The poles 384 are electrically connected to each other correspondingly.

The Zener diode ZD2 is formed on the semiconductor substrate 31. As shown in FIGS. 3A and 3B, the Zener diode ZD2 includes a third field oxide region 327, a fourth field oxide region 328, a third N-type region 333, and a third field oxide region 328. Three N-type extension regions 343, a third P-type region 353, a second reverse end 373, an N-type adjustment region 374, and a second forward end 385. The bottom and side surfaces of the Zener diode ZD2 are surrounded by the third insulating structure ISO8. The third insulating structure ISO8 includes a third insulating bottom layer 32" and a third insulating sidewall 325.

As shown in FIGS. 3A and 3B, the fourth insulating side wall 326 forms a ring-shaped closed side wall, enclosing the first insulating side wall 323, the second insulating side wall 324, and the third insulating side wall 325, that is, enclosing the power element 300 in the first insulating side wall. In the ring-shaped closed side wall formed by the four insulating side walls 326.

The difference between this embodiment and the embodiment shown in FIGS. 2A-2B is that in this embodiment, as shown in FIGS. 3A and 3B, compared to the power element 200, in the power element 300, the Zener diode The body ZD2 further includes an N-type adjustment region 374 formed under the upper surface of the epitaxial layer EPI and connected to the upper surface, and the N-type adjustment region 374 is located on the upper surface between the third P-type region 353 and the third N-type extension Between the regions 343, it is used to adjust the forward voltage of the PN junction formed by the third P-type region 353 and the third N-type extension region 343.

4A-4B show schematic diagrams of another embodiment of the power device according to the present invention. As shown in FIGS. 4A and 4B, the power device 400 is formed on a semiconductor substrate 41, which includes a laterally insulated gate bipolar transistor LIGBT4, a PN diode PN4, and a Zener diode ZD3. Among them, the Zener diode ZD3 is used as a clamping diode to limit the gate voltage applied to the gate of the laterally insulated gate bipolar transistor LIGBT4 not to be higher than the preset voltage threshold to avoid triggering the latch Effect, while protecting the power element 400.

Fig. 4B shows a schematic cross-sectional view of the section line DD' in Fig. 4A. In the power element 400, the coupling manner of the lateral insulated gate bipolar transistor LIGBT4, the PN diode PN4, and the Zener diode ZD3 is as shown in the small diagram of the circuit symbol in FIG. 4A. In the small diagram of the circuit symbol, the horizontal insulated gate bipolar transistor LIGBT4 has gate G, emitter E and drain C; PN diode PN4 has forward end F1 and reverse end R1; Zener diode ZD3 has a forward end F2 and a reverse end R2. The PN diode PN4 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT4; the Zener diode ZD3 is electrically connected between the gate G and the drain C of the lateral insulated gate bipolar transistor LIGBT4. Among them, the drain C and emitter E of the laterally insulated gate bipolar transistor LIGBT4 are respectively electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN4; the forward end of the Zener diode ZD3 F2 and the reverse terminal R2 are respectively electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT4.

The PN diode PN4 includes a first field oxide region 421, a first N-type region 431, a first N-type extension region 441, a first P-type region 451, a gate 461, a first reverse end 471, and a first顺向端481。 The forward end 481. The bottom and side surfaces of the PN diode PN4 are surrounded by the first insulating structure ISO9. Among them, the first insulating structure ISO9 includes a first insulating bottom layer 42 and a first insulating sidewall 423.

The lateral insulated gate bipolar transistor LIGBT4 is formed on the semiconductor substrate 41. As shown in FIGS. 4A and 4B, the lateral insulated gate bipolar transistor LIGBT4 includes a second field oxide region 422, a second N-type region 432, and a second The N-type extension region 442, the second P-type region 452, the gate 462, the drain 472, the emitter 482, and the P-type contact 484. The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT4 are surrounded by the second insulating structure ISO10. The second insulating structure ISO10 includes a second insulating bottom layer 42' and a second insulating sidewall 424. When the horizontal insulated gate bipolar transistors LIGBT4 are plural, they are electrically connected in parallel with each other, that is, the gate 462, drain 472, emitter 482 and P-type contacts in different horizontal insulated gate bipolar transistors LIGBT4 The poles 484 are electrically connected to each other correspondingly.

The Zener diode ZD3 is formed on the semiconductor substrate 41. As shown in FIGS. 4A and 4B, the Zener diode ZD3 includes a third field oxide region 427, a fourth field oxide region 428, a third N-type region 433, and a Three N-type extension regions 443, a third P-type region 453, a second reverse end 473, a P-type adjustment region 486, and a second forward end 485. The bottom and side surfaces of the Zener diode ZD3 are surrounded by the third insulating structure ISO11. The third insulating structure ISO11 includes a third insulating bottom layer 42" and a third insulating sidewall 425.

As shown in FIGS. 4A and 4B, the fourth insulating side wall 426 forms a ring-shaped closed side wall, enclosing the first insulating side wall 423, the second insulating side wall 424, and the third insulating side wall 425, that is, the power element 400 is enclosed in the first insulating side wall. In the ring-shaped closed sidewall formed by the four insulating sidewalls 426.

The difference between this embodiment and the embodiment shown in FIGS. 2A-2B is that in this embodiment, as shown in FIGS. 4A and 4B, compared to the power element 200, in the power element 400, the Zener diode The body ZD3 further includes a P-type adjustment region 486 formed under the upper surface of the epitaxial layer EPI and connected to the upper surface, and the P-type adjustment region 486 is located on the upper surface between the third P-type region 353 and the third N-type extension Between the regions 343, it is used to adjust the forward voltage of the PN junction formed by the third P-type region 353 and the third N-type extension region 343.

5A-5B show schematic diagrams of another embodiment of the power device according to the present invention. As shown in FIGS. 5A and 5B, the power device 500 is formed on the semiconductor substrate 51, which includes a lateral insulated gate bipolar transistor LIGBT5, a PN diode PN5, and a Zener diode ZD4. Among them, the Zener diode ZD4 is used as a clamping diode to limit the gate voltage applied to the gate of the laterally insulated gate bipolar transistor LIGBT5 not to be higher than the preset voltage threshold to avoid triggering the latch Effect, while protecting the power component 500.

Fig. 5B shows a schematic cross-sectional view of the section line EE' in Fig. 5A. In the power element 500, the coupling manner of the lateral insulated gate bipolar transistor LIGBT5, the PN diode PN5, and the Zener diode ZD4 is as shown in the small diagram of the circuit symbol in FIG. 5A. In the small diagram of the circuit symbol, the horizontal insulated gate bipolar transistor LIGBT53 has gate G, emitter E and drain C; PN diode PN5 has forward end F1 and reverse end R1; Zener diode ZD4 has a forward end F2 and a reverse end R2. The PN diode PN5 is connected in parallel with the lateral insulated gate bipolar transistor LIGBT5; the Zener diode ZD4 is electrically connected between the gate G and the drain C of the lateral insulated gate bipolar transistor LIGBT5. Among them, the drain C and emitter E of the lateral insulated gate bipolar transistor LIGBT5 are electrically connected to the forward end F1 and the reverse end R1 of the PN diode PN5, respectively; the forward end of the Zener diode ZD4 F2 and the reverse terminal R2 are respectively electrically connected to the drain C and the gate G of the lateral insulated gate bipolar transistor LIGBT5.

Among them, the PN diode PN5 includes a first field oxide region 521, a first N-type region 531, a first N-type extension region 541, a first P-type region 551, a gate 561, a first reverse end 571, and a first顺向端581. The bottom and side surfaces of the PN diode PN5 are surrounded by the first insulating structure ISO12. The first insulating structure ISO12 includes a first insulating bottom layer 52 and a first insulating sidewall 523.

The lateral insulated gate bipolar transistor LIGBT5 is formed on the semiconductor substrate 51, as shown in FIGS. 5A and 5B, the lateral insulated gate bipolar transistor LIGBT5 includes a second field oxide region 522, a second N-type region 532, and a second N-type extension region 542, second P-type region 552, gate 562, drain 572, emitter 582, and P-type contact 584. The bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT5 are surrounded by the second insulating structure ISO13. The second insulating structure ISO13 includes a second insulating bottom layer 52' and a second insulating sidewall 524. When the horizontal insulated gate bipolar transistors LIGBT5 are plural, they are electrically connected in parallel with each other, that is, the gate 562, drain 572, emitter 582 and P-type contacts of different horizontal insulated gate bipolar transistors LIGBT5 The poles 584 are electrically connected to each other correspondingly, respectively.

The Zener diode ZD4 is formed on the semiconductor substrate 51. As shown in FIGS. 5A and 5B, the Zener diode ZD4 includes a third field oxide region 527, a fourth field oxide region 528, a fifth field oxide region 529, and a Three N-type regions 533, a third N-type extension region 543, a third P-type region 553, a second reverse end 573, an N-type adjustment area 574, an electrostatic discharge (ESD) protection area 575, and a second forward end 585. The bottom and side surfaces of the Zener diode ZD4 are surrounded by the third insulating structure ISO14. The third insulating structure ISO14 includes a third insulating bottom layer 52" and a third insulating sidewall 525.

As shown in FIGS. 5A and 5B, the fourth insulating side wall 526 forms a ring-shaped closed side wall, enclosing the first insulating side wall 523, the second insulating side wall 524, and the third insulating side wall 525, that is, the power element 500 is enclosed in the first insulating side wall 523, the second insulating side wall 524, and the third insulating side wall 525. In the ring-shaped closed side wall formed by the four insulating side walls 526.

The difference between this embodiment and the embodiment shown in FIGS. 3A-3B is that in this embodiment, as shown in FIGS. 5A and 5B, compared to the power element 300, in the power element 500, the Zener diode The body ZD4 further includes an ESD protection zone 575 and a fifth field oxidation zone 529. The ESD protection area 575 has an N-type conductivity, is formed under the upper surface of the epitaxial layer EPI and is connected to the upper surface, and the ESD protection area 575 is located on the upper surface between the third N-type extension area 543 and the second forward end Between 585, the electrostatic protection area 575 is used to form an NPN transistor with the third P-type area 553 and the third N-type extension area 543, wherein the electrostatic protection area 575 is electrically connected to the second forward end 585 for the power device 500 When exposed to static voltage, the NPN transistor can be turned on to avoid damage to the power element 500 caused by the static voltage.

6A-6I show schematic diagrams of an embodiment of the method of manufacturing the power device 200 according to the present invention. 6A-6I show schematic cross-sectional views of the manufacturing method of the power device 200 as seen from the BB' cross-sectional line in FIG. 2B. As shown in FIG. 6A, first, a first insulating underlayer 22, a second insulating underlayer 22', and a third insulating underlayer 22" are formed on the substrate 21. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. It can be other semiconductor substrates. For example, a silicon dioxide layer is formed on the substrate 21, part of which serves as the first insulating underlayer 22, another part as the second insulating underlayer 22', and the other part as the third insulating underlayer 22". On the silicon dioxide layer, for example, an N-type epitaxial layer is formed, part of which is used as the first N-type region 231, the other part is used as the second N-type region 232, and the other part is used as the third N-type region 233. The aforementioned substrate 21, the silicon dioxide layer, and the N-type epitaxial layer can be realized by using a silicon on insulator (SOI) wafer, which is well known to those with ordinary knowledge in the art and will not be repeated here.

Next, as shown in FIG. 6B, the first insulating sidewall 223, the second insulating sidewall 224, and the third insulating sidewall 225 are formed, for example, but not limited to, the same deep trench etching process step and the simultaneous formation of the deep trench; and the same deposition process In the step, at the same time, an insulating material, such as but not limited to silicon dioxide, is deposited in the aforementioned deep trench to form the first insulating sidewall 223, the second insulating sidewall 224, the third insulating sidewall 225, and the fourth insulating sidewall 226. And the first insulating side wall 223, the second insulating side wall 224, the third insulating side wall 225, and the fourth insulating side wall 226 are connected to the silicon dioxide layer connected to the substrate 21 below, so as to form a closed epitaxial layer EPI. Range. Among them, in a preferred embodiment, the bottom and side surfaces of the PN diode PN2 are surrounded by the first insulating structure ISO3; the bottom and side surfaces of the lateral insulated gate bipolar transistor LIGBT2 are surrounded by the second insulating structure ISO4 ; And the bottom and side surfaces of the Zener diode ZD1 are surrounded by the third insulating structure ISO5.

Next, as shown in FIG. 6C, a first N-type extension region 241, a second N-type extension region 242, and a third N-type extension region 243 are formed. For example, but not limited to, the same lithography process steps are used to define the first N-type extension region. N-type extension region 241, second N-type extension region 242, and third N-type extension region 243; and the same ion implantation process steps, while N-type impurities, in the form of accelerated ions, are implanted by the aforementioned The region defined by the lithography process steps to form a first N-type extension region 241, a second N-type extension region 242, and a third N-type extension region 243. The first N-type extension region 241, the second N-type extension region 242, and the third N-type extension region 243 have N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under the upper surface of the N-type epitaxial layer. Connect to the upper surface.

Next, as shown in FIG. 6D, a first field oxide region 221, a second field oxide region 222, a third field oxide region 227, and a fourth field oxide region 228 are formed, which are, for example, but not limited to, the same oxidation process steps, and at the same time It is formed on the upper surface of the aforementioned N-type epitaxial layer and connected to the upper surface. The formation of the first field oxide region 221, the second field oxide region 222, the third field oxide region 227, and the fourth field oxide region 228 is not limited to the local oxidation of silicon (LOCOS) structure as shown in FIG. 6D, but also It can be a shallow trench isolation (STI) structure. Referring to FIG. 2A at the same time, the first field oxide region 221, the second field oxide region 222, the third field oxide region 227, and the fourth field oxide region 228 are formed from the top view of FIG. Part of the first N-type extension region 241, part of the second N-type extension region 242, part of the third N-type extension region 243, and part of the third N-type region 233.

Next, as shown in FIG. 6E, a first P-type region 251, a second P-type region 252, and a third P-type region 253 are formed. Among them, for example, but not limited to, the same lithography process steps are used to simultaneously define the regions of the first P-type region 251 and the second P-type region 252; and the same ion implantation process steps are used to simultaneously remove P-type impurities to accelerate In the form of ions, the regions defined by the aforementioned lithography process steps are implanted to form the first P-type region 251 and the second P-type region 252. The third P-type region 253, for example, can also be formed by the same lithography process steps and ion implantation process steps as those of the first P-type region 251 and the second P-type region 252; it can also be formed by different lithography process steps and ion implantation steps. Into the process steps to form. The first P-type region 251, the second P-type region 252, and the third P-type region 253 have P-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located below and connected to the upper surface of the N-type epitaxial layer surface. Referring to FIG. 2A at the same time, the first P-type region 251 and the second P-type region 252 from the top view of FIG. 2A are, for example, annular closed regions surrounding the first field oxide region 221 and the second field oxide region 222 respectively.

Next, as shown in FIG. 6F, the gate electrode 261 and the gate electrode 262 are formed as seen from the top view of FIG. 2A. The gate electrode 261 and the gate electrode 262 are, for example, an annular closed area. The gate 261 and the gate 262 are, for example, but not limited to, simultaneously formed by the same gate process step. Among them, the gate 261 and the gate 262 respectively include, for example, a dielectric layer, a conductive layer, and a spacer layer, which are well known to those with ordinary knowledge in the art. Do not repeat it. Therefore, the gate process steps include process steps such as lithography and oxidation to form a dielectric layer; process steps such as lithography and deposition to form a conductive layer; and process steps such as deposition and etching to form a spacer layer.

Next, as shown in FIG. 6G, a first forward end 281, an emitter 282, a P-type contact pole 284, and a second forward end 285 are formed, for example, but not limited to, the same lithography process steps, while defining the first The regions of the forward end 281, the emitter 282, the P-type contact electrode 284, and the second forward end 285; and by the same ion implantation process steps, at the same time, P-type impurities are implanted in the form of accelerated ions. The region defined by the lithography process steps to form a first forward end 281, an emitter 282, a P-type contact electrode 284, and a second forward end 285. The first forward end 281, the emitter 282, the P-type contact electrode 284, and the second forward end 285 have P-type conductivity, and are formed in the first P-type region 251, the second N-type extension region 242, and the second P-type region, respectively. The type region 252 and the third P type region 253 are located under and connected to the upper surface of the N-type epitaxial layer. Please refer to the upper view of FIG. 2A at the same time, the forward end 281, the P-type contact electrode 284, and the second forward end 285 are viewed from the upper view. Field oxidation zone 228.

Next, as shown in FIG. 6H, a first reverse end 271, a drain 272, and a second reverse end 273 are formed, which are, for example, but not limited to, the same lithography process steps (including using the gate 262 as a mask), The regions of the first reverse end 271, the drain electrode 272, and the second reverse end 273 are defined at the same time; and the same ion implantation process steps are used, and N-type impurities are implanted in the form of accelerated ions by the aforementioned micro The area defined by the process step is shadowed to form a first reverse end 271, a drain 272, and a second reverse end 273. The first reverse terminal 271, the drain electrode 272, and the second reverse terminal 273 have an N-type conductivity, are formed in the aforementioned N-type epitaxial layer, and are located under and connected to the upper surface of the N-type epitaxial layer. Please also refer to the upper view of FIG. 2A, the drain 272 is viewed from the upper view, for example, is a ring-shaped closed area surrounding the gate 262.

The present invention has been described with reference to the preferred embodiments above, but the above is only for making the content of the present invention easier for those skilled in the art, and is not used to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as deep well regions, can be added without affecting the main characteristics of the device. For another example, the lithography process steps are not limited to the photomask process steps, and may also include electron beam lithography process steps. All of these can be derived by analogy according to the teachings of the present invention. In addition, the described embodiments are not limited to a single application, and can also be applied in combination, for example, but not limited to combining the two embodiments. Therefore, the scope of the present invention should cover all the above and other equivalent changes. In addition, any implementation type of the present invention does not have to achieve all the objectives or advantages. Therefore, any item of the claimed patent scope should not be limited by this.

100, 200, 400, 500: power components 121, 221, 321, 421, 521: first field oxidation zone 122, 222, 322, 422, 522: second field oxidation zone 123, 223, 323, 423, 523: first insulating sidewall 124, 224, 324, 424, 524: second insulating sidewall 125, 225, 325, 425, 525: third insulating sidewall 131, 231, 331, 431, 531: the first N-type area 132, 232, 332, 432, 532: the second N-type area 141, 241, 341, 441, 541: the first N-type extension 142, 242, 342, 442, 542: second N-type extension 151, 251, 351, 451, 551: the first P-type zone 152, 252, 352, 452, 552: second P-type zone 161, 261, 361, 462, 562: gate 162, 262, 362, 462, 562: gate 171: reverse end 172, 272, 372, 472, 572: drain 181: forward end 182, 282, 382, 482, 582: emitter 184, 284, 384, 484, 584: P-type contact pole 226, 326, 426, 526: fourth insulating sidewall 227, 327, 427, 527: third field oxidation zone 228, 328, 428, 528: the fourth field oxidation zone 243, 343, 443, 543: the third N-type extension 253, 353, 453, 553: the third P-type zone 271, 371, 471, 571: first reverse end 273, 373, 473, 573: second reverse end 281, 381, 481, 581: the first forward end 285, 385, 485, 585: second forward end AA’, BB’, CC’, DD’, EE’: cut line C: Dip pole E: emitter F: Forward end G: Gate LIGBT1, LIGBT2, LIGBT3, LIGBT4, LIGBT5: lateral insulated gate bipolar transistor PN1, PN2, PN3, PN4, PN5: PN diode R: reverse end ZD1, ZB2, ZD3, ZD4, ZD5: Zener diode

1A and 1B show a schematic top view and a schematic cross-sectional view of a power device (power device 100) with a lateral insulated gate bipolar transistor (LIGBT) in the prior art.

1C and 1D respectively show schematic diagrams of circuit symbols and electrical characteristic curves of the power device 100.

2A-2B show schematic diagrams of an embodiment of the power device according to the present invention.

3A-3B show schematic diagrams of another embodiment of the power device according to the present invention.

4A-4B show schematic diagrams of another embodiment of the power device according to the present invention.

5A-5B show schematic diagrams of another embodiment of the power device according to the present invention.

6A-6H show schematic diagrams of an embodiment of the manufacturing method of the power device according to the present invention.

200: Power components

221: First Field Oxidation Zone

222: second field oxidation zone

223: first insulating sidewall

224: second insulating sidewall

225: third insulating side wall

226: fourth insulating side wall

227: Third Field Oxidation Zone

228: The fourth field oxidation zone

231: The first N-zone

241: The first N-type extension

242: The second N-type extension

243: The third N-type extension

251: The first P-type zone

252: The second P-type zone

253: The third P-type zone

261: Gate

262: Gate

271: first reverse end

272: Drain

273: second reverse end

281: The first forward end

282: Ejector

284: P-type contact pole

285: second forward end

291: Metal wire

BB’: Cut line

C: Dip pole

E: emitter

F: Forward end

G: Gate

LIGBT2: Lateral insulated gate bipolar transistor

PN2: PN diode

R: reverse end

ZD1: Zener diode

Claims (16)

A power element formed on a semiconductor substrate for driving a motor, including: A lateral insulated gate bipolar transistor (LIGBT); A PN diode, connected in parallel with the lateral insulated gate bipolar transistor; and A clamp diode has a clamp forward end and a clamp reverse end, which are respectively electrically connected to a drain and a gate of the laterally insulated gate bipolar transistor to limit the application to the gate The gate voltage of one of the poles is not higher than a preset voltage threshold. The power device according to claim 1, wherein the PN diode includes: A first N-type region formed in an epitaxial layer on the semiconductor substrate; A first P-type region formed in the first N-type region; A first N-type extension region formed in the first N-type region, and the first N-type extension region and the first P-type region are separated by the first N-type region; A first inverted end having an N-type conductivity type, formed in the first N-type extension region, and used as an electrical contact of the first N-type extension region; and A first forward end has a P-type conductivity and is formed in the first P-type region to serve as an electrical contact of the first P-type region. The power device according to claim 2, wherein the laterally insulated gate bipolar transistor includes: A second N-type region formed in the epitaxial layer on the semiconductor substrate; A second P-type region formed in the second N-type region; The drain electrode has an N-type conductivity and is formed in the second P-type region; A P-type contact is formed in the second P-type region to serve as an electrical contact of the second P-type region; The gate is formed on the epitaxial layer, and part of the gate is connected to the second P-type region; A second N-type extension region is formed in the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region; and An emitter with P-type conductivity is formed in the second N-type extension region. The power device according to claim 3, wherein the clamp diode system-Zener diode includes: A third P-type region formed in the epitaxial layer on the semiconductor substrate; A second forward end, having a P-type conductivity, formed in the third P-type region to serve as the clamp forward end and an electrical contact of the third P-type region; A third N-type extension region formed in the third P-type region; and A second reverse end, which has an N-type conductivity, is formed in the third N-type extension area and serves as the clamp reverse end and an electrical contact of the third N-type extension area. The power device according to claim 4, wherein the Zener diode further includes an N-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the N-type adjustment region is on the upper surface. The surface is located between the third P-type region and the third N-type extension region for adjusting the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region. The power device according to claim 4, wherein the Zener diode further includes a P-type adjustment region formed under the upper surface of the epitaxial layer and connected to the upper surface, and the P-type adjustment region is on the upper surface. The surface is located between the third P-type region and the third N-type extension region for adjusting the forward voltage of the PN junction formed by the third P-type region and the third N-type extension region. The power device according to any one of claim 5 or 6, wherein the Zener diode further includes an electrostatic discharge (ESD) protection zone, which has an N-type conductivity and is formed in the epitaxial layer The upper surface is under and connected to the upper surface, and the static electricity protection area is located on the upper surface between the third N-type extension area and the second forward end, and the static electricity protection area is used to communicate with the third P-type area And the third N-type extension area to form an NPN transistor, wherein the electrostatic protection area is electrically connected to the second forward end. The power device according to claim 4, wherein the first N-type extension region, the second N-type extension region, and the third N-type extension region are formed by the same lithography process step and the ion implantation process step simultaneously; The first P-type region and the second P-type region are formed by the same lithography process step and ion implantation process step simultaneously; The first reverse end, the drain electrode, and the second reverse end are simultaneously formed by the same lithography process step and the ion implantation process step; The first forward end, the emitter, the P-type contact pole, and the second forward end are simultaneously formed by the same lithography process step and the ion implantation process step. A method for manufacturing a power device, wherein the power device is formed on a semiconductor substrate for driving a motor, and the method for manufacturing a power device includes: Forming a lateral insulated gate bipolar transistor (LIGBT); Forming a PN diode, which is connected in parallel with the lateral insulated gate bipolar transistor; and A clamp diode is formed with a clamp forward end and a clamp reverse end, which are respectively electrically connected to a drain and a gate of the lateral insulated gate bipolar transistor to limit the application to the The gate voltage of one of the gates is not higher than a preset voltage threshold. The power device manufacturing method according to claim 9, wherein the step of forming the PN diode includes: Forming a first N-type region in an epitaxial layer on the semiconductor substrate; Forming a first P-type region in the first N-type region; Forming a first N-type extension region in the first N-type region, and the first N-type extension region and the first P-type region are separated by the first N-type region; Forming a first reverse end in the first N-type extension region, the first reverse end having an N-type conductivity type used as an electrical contact of the first N-type extension region; and A first forward end is formed in the first P-type region. The first forward end has a P-type conductivity and serves as an electrical contact of the first P-type region. The power device manufacturing method according to claim 10, wherein the step of forming the lateral insulated gate bipolar transistor includes: Forming a second N-type region in the epitaxial layer on the semiconductor substrate; Forming a second P-type region in the epitaxial layer; Forming the drain with N-type conductivity in the second P-type region; Forming the drain in the second P-type region, the drain having an N-type conductivity; Forming a P-type contact in the second P-type region as an electrical contact of the second P-type region; Forming the gate electrode on the epitaxial layer, wherein part of the gate electrode is connected to the second P-type region; Forming a second N-type extension region in the second N-type region, and the second N-type extension region and the second P-type region are separated by the second N-type region; and An emitter having a P-type conductivity is formed in the second N-type extension region. The power device manufacturing method according to claim 11, wherein the clamping diode system is a Zener diode, and the step of forming the clamping diode includes: Forming a third P-type region in the epitaxial layer on the semiconductor substrate; A second forward end is formed in the third P-type region, the second forward end has a P-type conductivity, and serves as the clamp forward end and an electrical contact of the third P-type region ； Forming a third N-type extension region in the third P-type region; and A second reverse end is formed in the third N-type extension region, the second reverse end has an N-type conductivity, and serves as the clamp reverse end, and the electrical properties of the third N-type extension region contact. According to the power device manufacturing method of claim 12, the step of forming the clamp diode further includes: forming an N-type adjustment region under the upper surface of the epitaxial layer and connecting the upper surface, and the N-type The adjustment area is between the third P-type area and the third N-type extension area on the upper surface, and is used to adjust the PN junction formed by the third P-type area and the third N-type extension area Forward voltage. According to the power device manufacturing method of claim 12, the step of forming the clamp diode further includes: forming a P-type adjustment region under the upper surface of the epitaxial layer and connected to the upper surface, and the P-type The adjustment area is between the third P-type area and the third N-type extension area on the upper surface, and is used to adjust the PN junction formed by the third P-type area and the third N-type extension area Forward voltage. The method for manufacturing a power device according to any one of claim 13 or 14, wherein the step of forming the clamp diode further comprises: forming an electrostatic discharge (ESD) protection area having an N-type conductivity type in The upper surface of the epitaxial layer is under and connected to the upper surface, and the electrostatic protection area is located on the upper surface between the third N-type extension area and the second forward end. The electrostatic protection area is used for The third P-type region and the third N-type extension region form an NPN transistor, wherein the electrostatic protection region is electrically connected to the second forward end. The method of manufacturing a power device according to claim 12, wherein the first N-type extension region, the second N-type extension region and the third N-type extension region are made by the same lithography process step and the ion implantation process step simultaneously form; The first P-type region and the second P-type region are formed by the same lithography process step and ion implantation process step simultaneously; The first reverse end, the drain electrode, and the second reverse end are simultaneously formed by the same lithography process step and the ion implantation process step; The first forward end, the emitter, the P-type contact pole, and the second forward end are simultaneously formed by the same lithography process step and the ion implantation process step.

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