201238049 六、發明說明： 【發明所屬之技術頜威】 本發明係有關於一種高壓半導體裝置’特別是有關於 一種水平擴散金氧半導體（laterally diffused metal oxide semiconductor, LDMOS )電晶體及其製造方法。 【先前技術】 高壓半導體裝置技術適用於高電壓與高功率的積體電 路領域。傳統高壓半導體裝置，例如垂直式擴散金氧半導 體（vertically diffused metal oxide semiconductor，VDMOS ) 電晶體及水平擴散金氧半導體（LDMOS)電晶體，主要用 於高於或約為18V的元件應用領域。高壓裝置技術的優點 在於符合成本效益，且易相容於其他製程，已廣泛應用於 顯示器驅動1C元件、電源供應器、電力管理、通訊、車用 電子或工業控制等領域中。 水平擴散金氧半導體（LDMOS)電晶體是利用閘極電 壓來產生通道，並控制流經源極與汲極之間的電流。在傳 統的水平擴散金氧半導體電晶體（LDMOS)中，為了防止 源極與沒極之間的擊穿效應（punch-through effect )，必須 延長電晶體的通道長度。然而，如此一來會增加裝置的尺 寸而使晶片面積增加且會使電晶體的導通電阻（on_ resistance，RQn)上升。再者，由於電洞的遷移率低於電子 的遷移率，因此P型擴散金氧半導體（PDMOS)電晶體的 導通電阻會高於N型擴散金氧半導體（NDMOS)電晶體的 導通電阻而不利於P型擴散金氧半導體電晶體效能的提 99019, 99020/0516-A42804/TW/fmal 5 201238049 升0 因此，有必要尋求一種新的高壓半導體裝置結構，其 能夠解決上述的問題。 【發明内容】 、、本發明—實施例提供一種高壓半導體裝置，包括：一 半導體基底，其内具有一高壓井區，且高壓井區具有一第 一導電型；一閘極結構，設置於高壓井區的半導體基底上 方，源極摻雜區及一汲極摻雜區，分別位於閘極結構兩 側的间[井區内；以及具有第-導電型的-淡摻雜區，位 於源極摻㈣與汲極摻雜區之間且相對鄰近源極掺雜區。 本發明另—實施例提供一種高壓半導體裝置，包括： 具有一第一導電型的一磊晶層，形成於一半導體基底上， 且蟲晶層内具有―第—高壓井區，且第—高㈣區具有相 反於該第-導電型的—第二導電型；—閘極結構，設置於 第-高壓井區的磊晶層上方；具有第一導電型的一體摻雜 區，位於閘極結構的—第—侧的第—高壓井區内；一源極 4雜區’位於體摻雜區内；—汲極彳參雜區，位於相對於 極結構的第-侧的—第二側的第—高料區内；以及且 型的一第—淡摻雜區，位於體摻雜區内且鄰近源 -貫知例提供-種高壓半導體装置之製造方 ::包括：在一半導體基底上形成具有-第-導電型的— 蠢晶層，在該層内㈣具有相反於 第二導電型的一第一高壓井區； 生的一 开匕，在第—鬲壓井區内形成且 99019, 99020/0516-A42804/TW/final 6 201238049 有第一導雷创的— 體摻雜區；在第一201238049 VI. Description of the Invention: [Technology of the Invention] The present invention relates to a high voltage semiconductor device, and more particularly to a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method of fabricating the same. [Prior Art] The high voltage semiconductor device technology is suitable for the field of high voltage and high power integrated circuits. Conventional high voltage semiconductor devices, such as vertically diffused metal oxide semiconductor (VDMOS) transistors and horizontally diffused metal oxide semiconductor (LDMOS) transistors, are mainly used in component applications above or about 18V. The advantages of high-voltage device technology are cost-effective and easily compatible with other processes, and have been widely used in display drive 1C components, power supplies, power management, communications, automotive electronics or industrial control. Horizontally diffused metal oxide semiconductor (LDMOS) transistors use gate voltage to create a channel and control the current flowing between the source and the drain. In conventional horizontally diffused metal oxide semiconductor transistors (LDMOS), in order to prevent a punch-through effect between the source and the gate, it is necessary to lengthen the channel length of the transistor. However, this increases the size of the device and increases the wafer area and increases the on-resistance (RQn) of the transistor. Furthermore, since the mobility of the hole is lower than the mobility of the electron, the on-resistance of the P-type diffusion metal oxide semiconductor (PDMOS) transistor is higher than the on-resistance of the N-type diffusion metal oxide semiconductor (NDMOS) transistor. The efficiency of the P-type diffusion MOS transistor is 99019, 99020/0516-A42804/TW/fmal 5 201238049 liter 0 Therefore, it is necessary to find a new high-voltage semiconductor device structure, which can solve the above problems. SUMMARY OF THE INVENTION The present invention provides a high voltage semiconductor device including: a semiconductor substrate having a high voltage well region therein, and the high voltage well region having a first conductivity type; and a gate structure disposed at a high voltage Above the semiconductor substrate of the well region, the source doped region and a drain doped region are respectively located between the two sides of the gate structure [well region; and have a first conductivity type-light doped region, located at the source The doped (d) is doped with the drain doping region and is relatively adjacent to the source doped region. Another embodiment of the present invention provides a high voltage semiconductor device comprising: an epitaxial layer having a first conductivity type formed on a semiconductor substrate, and having a "first" high pressure well region in the worm layer, and a first high (4) the region has a second conductivity type opposite to the first conductivity type; the gate structure is disposed above the epitaxial layer of the first high voltage well region; and the monolithic doping region of the first conductivity type is located at the gate structure - the first side of the first - high pressure well region; a source 4 hetero region 'located in the body doped region; - the 汲 彳 彳 doping region, located on the second side of the first side of the pole structure a first-high-doped region; and a first-difred-doped region of the type, located in the body-doped region and adjacent to the source-providing example, the manufacturer of the high-voltage semiconductor device: including: on a semiconductor substrate Forming a doped layer having a -first conductivity type, in which a fourth high pressure well region opposite to the second conductivity type is formed in the layer; a raw opening is formed in the first crucible well region and 99019 is formed , 99020/0516-A42804/TW/final 6 201238049 has the first lead---body doping area; One
【實施方式】[Embodiment]
作及使用本發明，並非用以侷限本發明的範圍。 本發明實施例提供一種高壓半導體裝置，例如水平擴 散金氧半導體電晶體，其利用環形植入區（hal〇 implant regi〇n)或口袋植入區（pocket implant region)來緩和擊穿 效應’進而藉由縮短電晶體通道來降低電晶體的導通電阻 並縮小裝置尺寸。 請參照第1圖，其繪示出根據本發明一實施例之高壓 半導體裝置10之剖面示意圖。在本實施例中，高壓半導體 裝置10 ’例如水平擴散金氧半導體電晶體，包括一半導體 基底100 ’其具有由一隔離結構103所定義出的一主動區 0D。在本實施例中，半導體基底1〇〇可為矽基底、鍺化矽 (SiGe)基底、塊體半導體（bulk semiconductor)基底、 化合物半導體（compound semiconductor)基底、絕緣層上 覆石夕（silicon on insulator, SOI)基底或其他習用之半導體 基底。再者’半導體基底100可依據設計需求而植入P型 或N型掺雜物。再者，隔離結構103為局部矽氧化層（local 99019, 99020/0516-A42804/TW/final 7 201238049 oxidation 〇f si】icon, L0C0S)。在其他實施例中，隔離結 構 103 可為淺溝槽隔離（shall〇w trench isolation, STI)結 構。 具有一第一導電型的一高壓井區102位於主動區〇D 的半導體基底100内。 一閘極結構117設置於高壓井區1〇2的半導體基底1〇〇 上方。閘極結構117包括與半導體基底100接觸的閘極介 電層114、位於閘極介電層114上並耦接至一閘極電壓Vg 的閘極電極116以及位於閘極電極116側壁的閘極間隙壁 115。 一源極摻雜區109及一汲極摻雜區113分別位於閘拐 結構117兩側的高_區1G2内。在本實施例中，源㈣ 雜區109祕至一源極電壓％，包括具有第一導電型的一 第-湲_區1()6及與第一濃摻雜區應相鄰且具有一第 二導電型的-第二濃摻雜區1〇δ，其中第二導電型相反於 第導電型。在一實施例中，第一導電型可為Ν型，而第 二導電型則為Ρ型。在另一實施例中第一導電型可為ρ型， 而第-導電型則為>7型。再者，沒極摻雜區ιΐ3雜接至一 2電[VD’包括具有第二導電型的—雙擴散區⑴及位 ㈣又。擴倾U2内且具有第二導電型的—第三漠換雜區 内，型的—井區1CM位於半導體基底100 -導雷井區1G2。井區刚的表面可包括具有第 7導電型的-第四濃摻雜區122，其轉接至一基底電愿 vsub ° "〇19, 99020/0516-A42804/TW/final 8 201238049 在一實於㈣一 間’且相對鄰近源極摻雜區109。 :貫細例中’淡摻雜區12〇的摻雜漠度在 的範圍’且可利用環形植入製程心。 rnipantatum)而形成，使淡摻雜區^ ^ ^區1〇8)。在本實施例中，特別的是淡摻雜區120 有錢低源極纽極之間因擊穿效應所⑽的漏電流。 请參照第2圖’其㈣出根據本發明另—實施例之言 ur裝置2。之剖面示意圖，其中相同於第1圖的部； 同的標號並省略其說明。在本實施例中，高壓半 W裝置20 ’例如水平擴散金氧半導體電晶體，包 導體基底⑽’其上形成了具有—第一導電型的一蟲晶層 蟲日日日層1G1❺導電型可與半導體基底_的導電型^目 同。再者，蟲晶層101具有由一隔離結構1〇3所定義 一主動區OD。 。”有相反於第一導電型的一第二導電型的一第—高壓 井區202位於主動區㈤的蟲晶層101内。在一實施例。中， 第一導電型可為Nf，而第二導電型則為。在另—實 施例中第—導電型可為？型，而第二導電型則為N型/ 一閘極結構117設置於第一高壓井區2〇2的遙晶層 101上方且墟至—閘極電壓VG。在本實施例中，問極結 構1Π的閘極電極116可延伸至部份的隔離結構1〇3上 方’如第2圖所示。 具有第一導電型的一體摻雜區11卜位於閘極結構117 99019, 99020/0516-A42804/TW/fmal 0 201238049 =二第:高㈣區2。2内。 電舞v 帅§ _〇η) 111内且輕接至一源極 於:摻L「有第一導電型的一第一淡摻雜區220位 、-，雜區111内且鄰近源極摻雜區1〇9。 220的摻雜濃度在⑽ 第-_ 中，源極摻雜區109包括且有圍。在本實施例 區⑽、㈣.曲 括具有第一導電型的一第-濃摻雜 口° A /、 一/辰摻雜區106相鄰且具有一第二導電型的 一第二濃摻雜區1G8以及與第二濃摻雜區⑽相鄰且 第t導電型的一第二淡摻純105。在一實施例中，第-淡摻雜區22G可藉由σ袋植人（pGeket impia咖▲)而形 成’使第-淡摻雜區220位於源極摻雜區1〇9或第二淡摻· 雜請下方的體摻雜區内⑴且鄰近第二濃摻雜區1〇8。 在本貫施例t，特別的是第—淡摻雜區22()可有效降低源 極與汲極之間因擊穿效應所引起的漏電流。 一汲極摻雜區113位於相對於閘極結構117的第一側 的-第二側的第-高壓井區2〇2 A。沒極摻雜區搞接至一 >及極電壓VD’包括具有第二導電型的—高壓雙擴散區（獅 voltage double diffused region) 212 及位於高壓雙擴散區 212内且具有第二導電型的一第三濃摻雜區 具有該第一導電型的一第二高壓井區2〇4，位於磊晶層 101内且環繞第一向壓井區202。第二高壓井區204的表面 可包括具有第一導電型的一第四濃摻雜區122,其耦接至 一基底電壓Vsub。 第3A至3G圖係繪示出第2圖中高壓半導體裝置20 之製造方法剖面示意圖。請參照第3A圖，提供一半導體 99019, 99020/0516-A42804/TW/final 】〇 201238049 基底ι〇0，例如矽基底、鍺化矽s ^ 體基底、化合物半導/夕（slGe)基底、塊體半導 立他習用之丰絕緣層上覆碎（S0I)基底或 ㈣入p 再者，半導體基底_可依據設 冲而求而植入P型或N型摻雜 上形成具有第—導電型在半導體基底100 可與半導體基底100且有相=曰1 ’其中蟲晶層101 蟲晶成長方式而形成:以以電型，且可利用選擇性 -第然US晶層1〇1内形成具有相反於第-導電型的 j導電型的—第一高壓井區2〇2。在一實施例中，第 .例中第型，而第二導電型則為P型。在另-實施 赛里可為？型’而第二導電型則為N型。在本 =例中接:利用離子植入製程，於蟲晶層仙中植入換 ”物^接者進行熱擴散製程，以形成第—高壓井區撕。 ::照第3Β圖’在蟲晶層1〇1形成隔 ⑻ 如局部矽氧化層（L〇c〇s) 區202的一主動區㈤。在義出對應於第一高磨井 可盔、u在其他貫施例中，隔離結構1〇3 了為淺溝槽隔離（STI)結構。 請參照第3C圖，可利用雜工& .. 中始Λ 」和用離子植入製程，於磊晶層101 中植入摻雜物，並接著進 熱擴散製程及退火製程，以形 成形成％繞弟一高壓井區202， Α ^ 二高_區2〇4。 且具有第-導電型的-第 5月參照第3 D圖，利用尤η ΑΑ， 製程，在第一高編入製程及熱擴散 摻雜區m及且有第1雷:：成具有弟-導電型的-體 养群導電型的—高I雙擴散區212。體 與高壓雙擴散區2〗2彼此相隔—既定距離。 9, 99020/0516-A42804/TW/final ,， 201238049 請參照第3E圖，在磊晶層1〇1的主動區〇D上形成一 閘極介電層114 ’例如氧化物、氮化物、氮氧化物、碳氧 化物或其組合或其他高介電常數材料（high_k，介電常數大 於8)，例如氧化鋁（入丨2〇3)、氧化銓、氮氧化 ^(HfON) ' (zirconium oxide, Zr02) (ZrON)或其組合。閘極介電層U4可利用熱氧化法、化 學氣相沉積法（chemical vapor deposition, CVD)或其他習 用的沉積技術而形成。接著，可利用化學氣相沉積法（cvd) 或其他習用的沉積技術，於閘極介電層114上形成閑極電 極116。閘極電極116可包括多晶石夕或金屬。之後，利用 習知微影及關製㈣圖案化閘極電極116及下方的間極 介電層114。圖案化的閘極電極116及閘極介電層大 抵位於體摻雜區111與高壓雙擴散區212之間的第一高屙 井區202上方且局部覆蓋體摻雜區⑴、高壓雙擴散區= 以及隔離結構103。 按者，在磊3日層101上形成一光阻圖案層119而露 高壓雙擴散區212及部分的體摻雜區ln。之後，利用 對準的方式進行離子植入製程，以在高壓雙擴散區212 體摻㈣ill内形成具有第二導電型的淡推雜區1〇5。 請參照第3F圖，在去除光阻圖案層U9之後，在 化的閘極電極m及間極介電層114的側壁形成閉極間 壁115，以完成閘極結構117的製做。閑極間隙壁出 包括氧化物、氮化物、氮氧化物或其組合，且可利 沉積製程及非等向性侧製程而形成。在形成閘極結構^ 之後’利用不同的離子植人製程，在體摻雜區⑴ 9卯 19,99020/0516-A42804/TW/final η ^ Ά 201238049 :、有第^電型的一第一濃按雜區106及與其相鄰且具有 第一導電型的一第二濃摻雜區〗〇8、在高壓雙擴散區Μ) =形成具有第二導電型的一第三濃摻雜區11〇以及在第二 ^壓井區204的表面形成具有第一導電型的一第四濃摻雜 區122。第一濃摻雜區1〇6、第二濃摻雜區1〇8以及淡摻雜 區/05係構成一源極摻雜區1〇9，而第三濃摻雜區I〗。及 同壓雙擴散區212係構成一汲極摻雜區113，使體摻雜區 111及汲極摻雜區113分別位於閘極結構1]7兩側。 請參照第3G @，可利用口袋植入製程，在鄰近源極 摻雜區109的體摻雜區U1内形成具有第一導電型的—淡 t雜區220 (即，口袋植入區），如此一來便完成高電壓 半導體裝置20的製做。在一實施例中，淡摻雜區22〇位於 淡摻雜區105下方的體摻雜區lu内。再者，淡摻雜區22〇 鄰近第二濃摻雜區108且摻雜濃度在1〇S/cm2至ι〇]6化爪2 的範圍。另外，特別的是形成淡摻雜區22〇所使用的離子 植入罩幕以及形成淡摻雜區1〇5所使用的離子植入罩幕可 採用同一光罩來進行微影製程而形成，因此可避免額外的 製造成本。 根據前述的實施例，由於淡摻雜區（環形植入區）12〇 以及次摻雜區（口袋植入區）22〇能夠有效降低源極與汲 極之間因擊穿效應所引起的漏電流，因此可適#地縮短高 壓半導體裝置10及2G的通道長度，進而降低高料導體 裝置10及20的導通電阻以及尺寸。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 99019, 99020/0516-A42804/TW/fmal n 201238049 脫離本發明之精神和範圍 發明之保護範圍當視後附 【圖式簡單說明】 内，當可作更 之申請專利範 動與潤飾，因此本 圍所界定者為準。 第1圖係繪示出根據本發明一 置剖面示意圖。 實施例之高壓半導體裝 第2圖係繪示出根據本發明另一 裝置剖面示意圖。 實施例之高壓半導體 第3A至3G圖係續'示出第 造方法剖面示意圖。 2圖中高壓半導體裝置之製 【主要元件符號說明】 10、20〜半導體裝置； 100〜半導體基底； 1〇1〜磊晶層； 102〜高壓井區； 103〜隔離結構； 104〜井區； 105、120、220〜淡摻雜區； 106〜第一濃摻雜區； 108〜第二濃摻雜區； 109〜源極摻雜區； 110〜第三濃摻雜區； 111〜體摻雜區； 112〜雙擴散區； 113〜汲極摻雜區； 114〜閘極介電層； 99019, 99020/05 ] 6-A42804/TW/fmal 14 201238049 115〜閘極間隙壁； 116〜間極電極， 117〜閘極結構； 119〜光阻圖案層； 122〜第四濃摻雜區 202〜第一高壓井區 2 0 4〜第二向麗井區 212〜高壓雙擴散區 OD~主動區， 〜閘極電壓；. VD〜汲極電壓；The invention is not intended to limit the scope of the invention. Embodiments of the present invention provide a high voltage semiconductor device, such as a horizontally diffused MOS transistor, which utilizes a ring implant region or a pocket implant region to mitigate a breakdown effect. The on-resistance of the transistor is reduced and the device size is reduced by shortening the transistor channel. Referring to FIG. 1, a cross-sectional view of a high voltage semiconductor device 10 in accordance with an embodiment of the present invention is shown. In the present embodiment, the high voltage semiconductor device 10', such as a horizontally diffused MOS transistor, includes a semiconductor substrate 100' having an active region 0D defined by an isolation structure 103. In this embodiment, the semiconductor substrate 1 may be a germanium substrate, a germanium telluride (SiGe) substrate, a bulk semiconductor substrate, a compound semiconductor substrate, and an insulating layer on silicon on silicon. Insulator, SOI) substrate or other conventional semiconductor substrate. Furthermore, the semiconductor substrate 100 can be implanted with a P-type or N-type dopant depending on design requirements. Furthermore, the isolation structure 103 is a partial tantalum oxide layer (local 99019, 99020/0516-A42804/TW/final 7 201238049 oxidation 〇f si] icon, L0C0S). In other embodiments, the isolation structure 103 can be a shallow trench isolation (STI) structure. A high voltage well region 102 having a first conductivity type is located within the semiconductor substrate 100 of the active region 〇D. A gate structure 117 is disposed over the semiconductor substrate 1A of the high voltage well region 1〇2. The gate structure 117 includes a gate dielectric layer 114 in contact with the semiconductor substrate 100, a gate electrode 116 on the gate dielectric layer 114 and coupled to a gate voltage Vg, and a gate on the sidewall of the gate electrode 116. Clearance wall 115. A source doping region 109 and a drain doping region 113 are respectively located in the high_region 1G2 on both sides of the gate structure 117. In the present embodiment, the source (four) impurity region 109 is secret to a source voltage %, including a first - - - region 1 () 6 having a first conductivity type and adjacent to the first densely doped region and having a The second conductivity type - the second concentrated doping region 1 〇 δ, wherein the second conductivity type is opposite to the first conductivity type. In one embodiment, the first conductivity type may be a Ν type, and the second conductivity type is a Ρ type. In another embodiment, the first conductivity type may be a p-type and the first conductivity type is a > type 7. Further, the electrodeless doping region ιΐ3 is mixed to a voltage [VD' includes a double diffusion region (1) and a bit (four) having a second conductivity type. In the third inversion zone, which has the second conductivity type, the well-type 1CM is located in the semiconductor substrate 100 - the mine well 1G2. The surface of the well region may include a fourth-concentrated doped region 122 having a seventh conductivity type, which is transferred to a substrate, vsub ° "〇19, 99020/0516-A42804/TW/final 8 201238049 It is (4) a 'and relatively adjacent source doped region 109. In the detailed example, the doping inversion of the lightly doped region 12〇 is in the range of 'the ring implant process core. Rnipantatum) is formed so that the lightly doped region ^ ^ ^ region 1 〇 8). In this embodiment, in particular, the light-doped region 120 has a low leakage current between the source and the source due to the breakdown effect (10). Referring to Fig. 2, (d), the ur device 2 according to another embodiment of the present invention is shown. A cross-sectional view of the same drawing as that of Fig. 1; the same reference numerals are used and the description thereof is omitted. In the present embodiment, the high-voltage half-W device 20' is, for example, a horizontally diffused MOS transistor, and the package conductor substrate (10)' is formed with a first-conductivity type of a worm-like layer of the day layer 1G1 ❺ conductivity type. The same as the conductivity type of the semiconductor substrate. Furthermore, the insecticidal layer 101 has an active region OD defined by an isolation structure 1〇3. . A first high-voltage well region 202 having a second conductivity type opposite to the first conductivity type is located in the crystal layer 101 of the active region (5). In an embodiment, the first conductivity type may be Nf, and The second conductivity type is: in another embodiment, the first conductivity type may be a ? type, and the second conductivity type is an N type / a gate structure 117 disposed in the first high voltage well region 2 〇 2 of the remote layer Above the 101, the gate-gate voltage VG. In this embodiment, the gate electrode 116 of the pole structure 1 可 can extend over a portion of the isolation structure 1 〇 3 as shown in Fig. 2. The type of integrated doping region 11 is located in the gate structure 117 99019, 99020/0516-A42804/TW/fmal 0 201238049 = two: high (four) area 2. 2 inside. Electric dance v handsome § _ 〇 )) 111 and Lightly connected to a source: doped with "a first lightly doped region of the first conductivity type 220 bits, -, within the impurity region 111 and adjacent to the source doping region 1 〇 9. The doping concentration of 220 is (10) In the -_th, the source doping region 109 includes and has a circumference. In the present embodiment, (10), (4), a first-rich doping port having a first conductivity type, a /, a / □ doping Zone 106 is adjacent and has a second concentrated doped region 1G8 of a second conductivity type and a second lightly doped pure 105 adjacent to the second heavily doped region (10) and of the tth conductivity type. In one embodiment, the first light doping The region 22G can be formed by the σ bag implant (pGeket impia ▲) to make the first-light doped region 220 in the body doped region under the source doped region 1〇9 or the second light doped region. (1) and adjacent to the second concentrated doping region 1 〇 8. In the present embodiment t, in particular, the first light-doped region 22 () can effectively reduce the leakage caused by the breakdown effect between the source and the drain A drain-doped region 113 is located in the first high-voltage well region 2〇2 A on the second side with respect to the first side of the gate structure 117. The gate-doped region is connected to a > The VD' includes a shi voltage double diffused region 212 having a second conductivity type and a third concentrated doped region having a second conductivity type in the high voltage double diffusion region 212 having the first conductivity type a second high pressure well region 2〇4 is located within the epitaxial layer 101 and surrounds the first direction well region 202. The surface of the second high voltage well region 204 may include a first conductivity type The four-doped doped region 122 is coupled to a substrate voltage Vsub. Figures 3A to 3G are schematic cross-sectional views showing the manufacturing method of the high-voltage semiconductor device 20 in Fig. 2. Referring to Figure 3A, a semiconductor 99019 is provided. 99020/0516-A42804/TW/final 】201283049 Substrate ι〇0, such as ruthenium substrate, ruthenium s ^ base, compound semi-conductive / s(Ge) substrate, bulk semi-conductive Overlying the (S0I) substrate or (4) into the p, the semiconductor substrate _ can be implanted on the P-type or N-type doping to form a first conductivity type in the semiconductor substrate 100 and the semiconductor substrate 100 There is a phase = 曰 1 ' in which the worm layer 101 crystal growth mode is formed: in an electric type, and the selectivity - the first US crystal layer 1 〇 1 is formed to have a j conductivity type opposite to the first conductivity type - The first high-pressure well area 2〇2. In one embodiment, the first type is in the first example, and the second conductivity type is in the P type. In the other-implementation competition? The second conductivity type is N type. In this example, the ion implantation process is used, and the material diffusion is implanted in the insect layer to perform the thermal diffusion process to form the first high-pressure well region tear. :: Photograph 3 The crystal layer 1〇1 forms a spacer (8) such as an active region (5) of the local tantalum oxide layer (L〇c〇s) region 202. In the sense, the first high-grinding well can be helmeted, and in other embodiments, the isolation is The structure 1〇3 is a shallow trench isolation (STI) structure. Please refer to the 3C figure, the dopant can be implanted in the epitaxial layer 101 by using the handyman & And then proceeding to the thermal diffusion process and the annealing process to form a high-frequency well region 202, Α ^ 2 high_region 2 〇 4. And the first conductivity type - the fifth month refers to the 3rd D picture, using the η ΑΑ, the process, the first high-programming process and the thermal diffusion doping region m and the first Ray:: Type-body group conductive type-high I double diffusion region 212. The body and the high pressure double diffusion zone 2 are separated from each other by a given distance. 9, 99020/0516-A42804/TW/final , , 201238049 Please refer to FIG. 3E to form a gate dielectric layer 114 'eg oxide, nitride, nitrogen on the active region 〇D of the epitaxial layer 1〇1. Oxide, carbon oxide or a combination thereof or other high dielectric constant material (high_k, dielectric constant greater than 8), such as alumina (into 丨2〇3), yttrium oxide, oxynitride (HfON) ' (zirconium oxide , Zr02) (ZrON) or a combination thereof. The gate dielectric layer U4 can be formed by thermal oxidation, chemical vapor deposition (CVD) or other conventional deposition techniques. Next, the idler electrode 116 can be formed on the gate dielectric layer 114 by chemical vapor deposition (cvd) or other conventional deposition techniques. Gate electrode 116 may comprise polycrystalline or metallic. Thereafter, the gate electrode 116 and the underlying dielectric layer 114 are patterned by conventional lithography and (4). The patterned gate electrode 116 and the gate dielectric layer are located above the first high well region 202 between the body doped region 111 and the high voltage double diffusion region 212 and partially cover the doped region (1) and the high voltage double diffusion region. = and isolation structure 103. As a result, a photoresist pattern layer 119 is formed on the layer 3 of the ray 3 to expose the high voltage double diffusion region 212 and a portion of the body doped region ln. Thereafter, the ion implantation process is performed by means of alignment to form a light dummy region 1〇5 having a second conductivity type in the high-pressure double diffusion region 212. Referring to FIG. 3F, after the photoresist pattern layer U9 is removed, the gate electrodes 115 are formed on the sidewalls of the gate electrode m and the interlayer dielectric layer 114 to complete the gate structure 117. The interstitial spacers include oxides, nitrides, oxynitrides, or combinations thereof, and can be formed by a deposition process and an anisotropic side process. After forming the gate structure ^, using different ion implantation processes, in the body doped region (1) 9卯19,99020/0516-A42804/TW/final η ^ Ά 201238049 :, there is a first electric type a thick doped region 106 and a second heavily doped region adjacent thereto having a first conductivity type, in the high voltage double diffusion region =) forming a third heavily doped region 11 having a second conductivity type A fourth heavily doped region 122 having a first conductivity type is formed on the surface of the second well region 204. The first heavily doped region 〇6, the second heavily doped region 〇8, and the lightly doped region /05 constitute a source doped region 1〇9, and the third heavily doped region I 。. And the double-diffusion region 212 of the same voltage constitutes a drain-doped region 113, and the body-doped region 111 and the drain-doped region 113 are respectively located on both sides of the gate structure 1]7. Referring to FIG. 3G, a pocket implant process can be used to form a light-doped region 220 (ie, a pocket implant region) having a first conductivity type in the body doped region U1 adjacent to the source doping region 109. In this way, the fabrication of the high voltage semiconductor device 20 is completed. In one embodiment, the lightly doped region 22 is located within the body doped region lu below the lightly doped region 105. Furthermore, the lightly doped region 22 is adjacent to the second heavily doped region 108 and has a doping concentration in the range of 1 〇 S/cm 2 to ι 〇 6 . In addition, in particular, the ion implantation mask used to form the lightly doped region 22 and the ion implantation mask used to form the lightly doped region 1〇5 can be formed by using the same mask for the lithography process. Therefore, additional manufacturing costs can be avoided. According to the foregoing embodiment, since the lightly doped region (annular implant region) 12 〇 and the sub-doped region (pocket implant region) 22 〇 can effectively reduce the leakage between the source and the drain due to the breakdown effect The current can therefore shorten the channel length of the high voltage semiconductor devices 10 and 2G, thereby reducing the on-resistance and size of the high-material conductor devices 10 and 20. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art, without departing from the invention, is not in the scope of the present invention. The scope of protection of the spirit and scope of the invention shall be deemed to be more patented and retouched in the following [simplified description of the schema], so the definition in this enclosure shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing the present invention. High voltage semiconductor package of the embodiment Fig. 2 is a schematic cross-sectional view showing another apparatus according to the present invention. The high voltage semiconductor of the embodiment 3A to 3G is a schematic cross-sectional view showing the first method. 2In the figure, the high voltage semiconductor device is manufactured [main component symbol description] 10, 20~ semiconductor device; 100~ semiconductor substrate; 1〇1~ epitaxial layer; 102~ high voltage well region; 103~ isolation structure; 104~ well region; 105, 120, 220~ lightly doped region; 106~ first concentrated doped region; 108~ second concentrated doped region; 109~ source doped region; 110~ third concentrated doped region; Miscellaneous region; 112~double diffusion region; 113~dip doped region; 114~gate dielectric layer; 99019, 99020/05] 6-A42804/TW/fmal 14 201238049 115~gate spacer; 116~ Electrode electrode, 117~ gate structure; 119~ photoresist pattern layer; 122~ fourth concentrated doping region 202~ first high voltage well region 2 0 4~ second to Lijing area 212~ high voltage double diffusion region OD~ active Zone, ~ gate voltage; VD~汲 pole voltage;
Vs〜源極電壓；Vs~source voltage;
Vsub〜基底電壓。 99019, 99020/0516-A42804/TW/finalVsub ~ substrate voltage. 99019, 99020/0516-A42804/TW/final