CN115274859B - LDMOS transistor and manufacturing method thereof - Google Patents
LDMOS transistor and manufacturing method thereof Download PDFInfo
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- CN115274859B CN115274859B CN202211205804.6A CN202211205804A CN115274859B CN 115274859 B CN115274859 B CN 115274859B CN 202211205804 A CN202211205804 A CN 202211205804A CN 115274859 B CN115274859 B CN 115274859B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 210000000746 body region Anatomy 0.000 claims abstract description 32
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- 239000000758 substrate Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 235000012239 silicon dioxide Nutrition 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 238000005468 ion implantation Methods 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
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- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
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- 230000000694 effects Effects 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
Abstract
The invention relates to the field of semiconductors, and provides an LDMOS transistor and a manufacturing method thereof. The LDMOS transistor comprises a substrate, a P-type body region, an N-type drift region, an N-type high-voltage well region, a source electrode positioned in the P-type body region, a drain electrode positioned in the N-type drift region, a grid electrode and a shallow groove isolation region, wherein the N-type drift region is provided with a P-type doped region, the P-type doped region wraps the lower edge corner of the shallow groove isolation region and is connected with the drain electrode, and the P-type doped region and the N-type drift region form a PN junction to share an electric field between the drain electrode and the N-type drift region; the upper surface of the shallow trench isolation region is provided with a polysilicon field plate structure; the polysilicon field plate structure, the shallow groove isolation region and the P-type doped region form a RESURF structure so as to reduce an electric field between the P-type doped region and the N-type drift region. The invention can reduce the electric field intensity of the drain terminal in the channel direction, improve the breakover voltage of the device and reduce the hot carrier effect.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an LDMOS transistor and a manufacturing method of the LDMOS transistor.
Background
A Lateral Double-diffused metal oxide semiconductor field effect transistor (LDMOS) has the characteristics of high voltage resistance, low power consumption, large current driving capability and the like, and is widely applied to power management circuits.
The main performance criteria of LDMOS transistors include on-resistance and breakdown voltage. Generally, the ratio of the working voltage to the working current of the LDMOS transistor is large, when the LDMOS transistor is turned on, the high-low junction electric field between the drain and the drift region is large, and the electric field of the drain in the channel direction is strong, which is easily broken down, affecting the breakdown voltage Bvon (turn-on breakdown voltage) when turned on, resulting in a reduction in the performance of the device; meanwhile, because a large number of electrons flow through a high electric field region, a hot carrier effect is easily caused, thereby affecting the reliability of the LDMOS transistor.
Disclosure of Invention
The invention aims to provide an LDMOS transistor and a manufacturing method thereof, which are used for improving the on breakdown voltage of a device.
In order to achieve the above object, a first aspect of the present invention provides an LDMOS transistor, which includes a substrate, a P-type body region, an N-type drift region, an N-type high voltage well region, a source located in the P-type body region, a drain located in the N-type drift region, a gate, and a shallow trench isolation region, where the N-type drift region is provided with a P-type doped region, the P-type doped region wraps a lower edge corner of the shallow trench isolation region and is connected to the drain, and the P-type doped region and the N-type drift region form a PN junction to share an electric field between the drain and the N-type drift region; a polysilicon field plate structure is arranged on the upper surface of the shallow trench isolation region; the polysilicon field plate structure, the shallow groove isolation region and the P-type doped region form a RESURF structure so as to reduce an electric field between the P-type doped region and the N-type drift region.
In the embodiment of the invention, an N + protection ring is arranged in the region where the N-type high-voltage well region and the shallow slot isolation region are bordered; the N + protection ring and the drain electrode form a double RESURF structure with the polysilicon field plate structure, the shallow groove isolation region and the P-type doped region.
In the embodiment of the invention, the P-type body region is provided with a P + protection ring, and the P + protection ring is connected with the source electrode.
In the embodiment of the invention, the polysilicon field plate structure comprises a polysilicon field plate and a field plate isolation oxide layer.
A second aspect of the present invention provides a method for manufacturing an LDMOS transistor, comprising:
forming an N-type high-voltage well region, a P-type body region and an N-type drift region on a P-type silicon substrate;
forming a shallow groove isolation region and a P-type doped region;
forming an oxide layer;
depositing polysilicon on the oxide layer to form a polysilicon gate and a polysilicon field plate;
and forming a source electrode in a corresponding region of the P-type body region and forming a drain electrode in a corresponding region of the N-type drift region.
In an embodiment of the present invention, the forming an N-type hvw region, a P-type body region, and an N-type drift region on a P-type silicon substrate includes:
oxidizing the surface of the P-type silicon substrate to form a silicon dioxide thin layer;
photoetching the silicon dioxide thin layer to form a pattern area of an N-type high-voltage well area, a P-type body area and an N-type drift area;
and respectively carrying out N-type ion implantation, P-type ion implantation and N-type ion implantation in the pattern regions of the N-type high-voltage well region, the P-type body region and the N-type drift region, propelling at high temperature, and removing the silicon dioxide thin layer to form the N-type high-voltage well region, the P-type body region and the N-type drift region.
In an embodiment of the present invention, the forming of the shallow trench isolation region and the P-type doped region includes:
forming a silicon dioxide thin layer on the surface of a P-type silicon substrate on which an N-type high-voltage well region, a P-type body region and an N-type drift region are formed through thermal oxidation, and depositing silicon nitride on the silicon dioxide thin layer;
photoetching to form a pattern area of the shallow trench isolation area, and etching silicon nitride, a silicon dioxide thin layer and silicon of the N-type drift area by a dry method to form a trench of the shallow trench isolation area;
performing large-angle rotation ion implantation along the groove wall of the groove to form a P-type doped region;
carrying out thermal oxidation treatment on the damage caused by dry etching silicon and ion implantation;
and depositing silicon dioxide in the groove, carrying out surface planarization treatment, removing the silicon nitride and the silicon dioxide thin layer on the surface, and carrying out high-temperature annealing to form the shallow groove isolation region.
In an embodiment of the present invention, the forming an oxide layer includes: forming an oxide layer on the surface of the P-type silicon substrate on which the shallow trench isolation region and the P-type doped region are formed through thermal oxidation; and etching the oxide layer to form a gate oxide layer and a field plate isolation oxide layer.
In an embodiment of the present invention, the depositing polysilicon on the oxide layer to form a polysilicon gate and a polysilicon field plate includes: and depositing polycrystalline silicon on the gate oxide layer and the field plate isolation oxide layer, carrying out N-type ion heavy doping on the polycrystalline silicon, and etching the heavily doped polycrystalline silicon to form a polycrystalline silicon gate and a polycrystalline silicon field plate.
In an embodiment of the present invention, the forming a source in a region corresponding to the P-type body region and a drain in a region corresponding to the N-type drift region includes: heavily doping and injecting N-type ions into a corresponding region of the P-type body region to form a source electrode, heavily doping and injecting N-type ions into a corresponding region of the N-type drift region to form a drain electrode, and heavily doping and injecting N-type ions into a region of the N-type high-voltage well region, which is bordered by the shallow groove isolation region, to form an N + protection ring; and heavily doping and injecting P-type ions into a region where the P-type body region is adjacent to the source electrode to form a P + protective ring.
According to the LDMOS transistor, the P-type doped region and the NRF form a PN junction, so that high and low junction electric fields between the drain electrode and the NRF can be shared, the electric field intensity of the drain end in the channel direction is reduced, the drain end is prevented from being broken down, and the on breakdown voltage of the device can be improved. In addition, the P-type doped region wraps the corners of the lower edge of the shallow trench isolation region, and the P-type doped region can absorb an electric field at the corners of the shallow trench isolation region, so that electric leakage at the corners of the shallow trench isolation region is reduced.
Because the electric field shared by the P-type doped region from the NRF is also strong, the P-type doped region has a transverse large electric field under the hot carrier effect, and is easy to deplete under the action of the large electric field. Based on this, the invention sets a polysilicon Field plate structure on the upper SURface of the shallow trench isolation region, the polysilicon Field plate structure, the shallow trench isolation region and the P-type doped region form a RESURF structure, and the RESURF (Reduced SURface Field) structure can counteract the electric Field at the drain end to a certain extent, reduce the lateral electric Field between the P-type doped region and the NRF, reduce the depletion of the P-type doped region, enhance the partial pressure effect of the P-type doped region on the high-low junction electric Field between the drain electrode and the NRF, further improve the on-state breakdown voltage of the device, and reduce the hot carrier effect.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a schematic structural diagram of an LDMOS transistor provided in an embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating an LDMOS transistor according to an embodiment of the present invention;
fig. 3a is a schematic structural diagram of an N-type hvw region, a P-type body region and an N-type drift region formed in a method for manufacturing an LDMOS transistor according to an embodiment of the invention;
fig. 3b is a schematic structural diagram of a shallow trench isolation region and a P-type doped region formed in the method for manufacturing the LDMOS transistor according to the embodiment of the invention;
FIG. 3c is a schematic structural diagram of an oxide layer formed in the method for fabricating an LDMOS transistor according to the present invention;
fig. 3d is a schematic structural diagram of a polysilicon gate and a polysilicon field plate formed in the method for manufacturing the LDMOS transistor according to the embodiment of the present invention;
fig. 3e is a schematic structural diagram of the source and the drain formed in the method for manufacturing the LDMOS transistor according to the embodiment of the invention.
Description of the reference numerals
101-source, 102-drain, 103-gate, 104-shallow trench isolation, 105-P-type doped region,
106 a-polysilicon gate, 106 b-polysilicon field plate, 107 a-gate oxide,
107 b-field plate isolation oxide layer, 108-N + guard ring, 109-P + guard ring.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
In the description herein, it will be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present application.
Fig. 1 is a schematic structural diagram of an LDMOS transistor provided in an embodiment of the present invention. As shown in fig. 1, an embodiment of the invention provides an LDMOS transistor, which includes a substrate P-SUB, a P-body region P-body, an N-drift region NRF, an N-HVNW, a source 101 located in the P-body region P-body, a drain 102 located in the N-drift region NRF, a gate 103, and a shallow trench isolation region 104, wherein the N-drift region NRF has a P-doped region 105, the P-doped region 105 wraps the lower edge corner of the shallow trench isolation region 104 and is connected to the drain 102, and the P-doped region 105 and the N-drift region NRF form a PN junction. The upper surface of the shallow trench isolation region 104 is provided with a polysilicon field plate structure, and the polysilicon field plate structure, the shallow trench isolation region 104 and the P-type doped region 105 form a RESURF structure. The gate 103 includes a polysilicon gate 106a and a gate oxide layer 107a, and the polysilicon field plate structure includes a polysilicon field plate 106b and a field plate isolation oxide layer 107b.
Since the N-type ion concentration of the drain 102 is much higher than that of the NRF, the electric field between the drain 102 and the NRF is very strong when the device is turned on, and the electric field at the drain end in the channel direction is very strong, which is easily broken down. In the embodiment of the invention, the P-type doped region 105 and the NRF form a PN junction, so that high and low junction electric fields between the drain electrode 102 and the NRF can be shared, the electric field strength of a drain end in the channel direction is reduced, the drain end is not broken down, and the on breakdown voltage of a device can be improved. In addition, the P-type doped region 105 wraps the lower edge corner of the shallow trench isolation region 104, and the P-type doped region 105 can absorb the electric field at the sharp corner of the shallow trench isolation region 104, thereby reducing the leakage at the sharp corner of the shallow trench isolation region 104.
Since the electric field shared by the P-type doped region 105 from the NRF is also strong, the P-type doped region 105 has a large transverse electric field under the hot carrier effect, and is easily depleted under the action of the large electric field. Therefore, a polysilicon field plate structure is provided on the upper surface of the shallow trench isolation region 104, and the polysilicon field plate structure, the shallow trench isolation region 104 and the P-type doped region 105 form a RESURF structure. Applying a driving voltage V on the polysilicon field plate when the device is conducted GS The RESURF (Reduced SURface Field ) structure can offset the drain end electric Field to a certain extent, reduce the lateral electric Field between the P-type doped region 105 and the NRF, reduce the depletion of the P-type doped region 105, enhance the voltage division effect of the P-type doped region 105 on the high and low junction electric fields between the drain 102 and the NRF, further improve the on breakdown voltage of the device, and reduce the hot carrier effect.
In one embodiment, the region where the N-type high voltage well region HVNW borders the shallow trench isolation region 104 is provided with an N + guard ring 108, and the N + guard ring 108 and the drain 102 form a Double RESURF (Double RESURF) structure with the polysilicon field plate structure, the shallow trench isolation region 104 and the P-type doped region 105. Further reducing the lateral electric field between the P-type doped region 105 and the NRF, reducing the depletion of the P-type doped region 105, and further improving the on-breakdown voltage of the device. In addition, the RESURF structure formed by the P-type doped region 105 and the shallow trench isolation region 104 can also reduce the surface electric field of the shallow trench isolation region 104 and reduce the leakage.
In one embodiment, a P + guard ring 109 is disposed on the surface of the P-body region, and P + guard ring 109 is connected to source 101. The P-body region P-body can be externally connected to the voltage through the P + guard ring 109, and the P + guard ring 109 and the source 101 are at the same potential, thereby improving or reducing the latch-up effect.
The embodiment of the invention also provides a manufacturing method of the LDMOS transistor of the embodiment. As shown in fig. 2, an embodiment of the present invention provides a method for manufacturing an LDMOS transistor, which includes the following steps:
Referring to fig. 3a, a thin silicon dioxide layer is formed on the surface of a P-type silicon substrate P-SUB by oxidation. And photoetching the silicon dioxide thin layer to form a pattern area of an N-type high-voltage well area, a P-type body area and an N-type drift area. N-type ion implantation, P-type ion implantation and N-type ion implantation are respectively carried out on the pattern regions of the N-type high-voltage well region, the P-type body region and the N-type drift region, high-temperature propulsion is carried out, the thin silicon dioxide layer is removed, and the N-type high-voltage well region HVNW, the P-type body region P-body and the N-type drift region NRF are formed, wherein the structure formed in the step is shown in figure 3 a.
Referring to fig. 3b, next to step 201, a silicon dioxide thin layer is formed on the surface of the P-type silicon substrate by thermal oxidation, and silicon nitride is deposited on the silicon dioxide thin layer; and photoetching to form a pattern area of the shallow trench isolation area, etching silicon nitride, a silicon dioxide thin layer and silicon of the N-type drift area by a dry method to form a trench of the shallow trench isolation area, and performing large-angle rotation P-type ion implantation along the trench wall of the trench to form a P-type doped area 105. After thermal oxidation treatment is performed on the damage caused by dry etching silicon and ion implantation, silicon dioxide is deposited in the trench, surface planarization treatment is performed, a silicon nitride and a silicon dioxide thin layer on the surface are removed, high-temperature annealing is performed, and a shallow trench isolation region 104 is formed, wherein the structure formed in the step is shown in fig. 3 b. In the embodiment, after the groove of the shallow groove isolation region is formed, the large-angle rotation ion implantation is performed to form the P-type doped region 105, the groove is refilled to form the shallow groove isolation region 104, the P-type doped region 105 and the shallow groove isolation region 104 are integrally formed, only one photoetching is needed, compared with a mode that the P-type doped region is formed by ion implantation and then the groove is etched to form the shallow groove isolation region, one photoetching is omitted, one mask plate is saved, and the process flow is simplified.
Referring to fig. 3c, an oxide layer is formed on the surface of the P-type silicon substrate where the shallow trench isolation region 104 and the P-type doped region 105 are formed by thermal oxidation, and the oxide layer is etched to form a gate oxide layer 107a and a field plate isolation oxide layer 107b, which form the structure shown in fig. 3 c.
Referring to fig. 3d, polysilicon is deposited on the gate oxide layer 107a and the field plate isolation oxide layer 107b, N-type ion heavy doping is performed on the polysilicon, and the heavily doped polysilicon is etched to form a polysilicon gate 106a and a polysilicon field plate 106b, wherein the structure formed in this step is as shown in fig. 3 d.
In step 205, a source is formed in a region corresponding to the P-type body region, and a drain is formed in a region corresponding to the N-type drift region.
Referring to fig. 3e, N-type ions are heavily doped and implanted in a region corresponding to the P-body of the P-type body region to form a source 101, N-type ions are heavily doped and implanted in a region corresponding to the N-type drift region NRF to form a drain 102, and N-type ions are heavily doped and implanted in a region of the N-type high-voltage well region HVNW, which is adjacent to the shallow trench isolation region 104, to form an N + guard ring 108; p-type ions are heavily doped in the region where the P-body of the P-type body region borders the source 101 to form a P + guard ring 109, and finally the LDMOS transistor is formed, and the overall structure thereof is shown in fig. 3 e.
In this document, unless expressly stated or limited otherwise, the terms "connected," "connected," and "connecting" are used broadly and encompass, for example, direct connection, indirect connection through an intermediary, communication between two elements, or interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. An LDMOS transistor comprises a substrate, a P-type body region, an N-type drift region, an N-type high-voltage well region, a source electrode positioned in the P-type body region, a drain electrode positioned in the N-type drift region, a grid electrode and a shallow groove isolation region, and is characterized in that the N-type drift region is provided with a P-type doped region connected with the drain electrode, the P-type doped region wraps corners of the lower edge of the shallow groove isolation region and is connected with the drain electrode, and the P-type doped region and the N-type drift region form a PN junction so as to share an electric field between the drain electrode and the N-type drift region;
the upper surface of the shallow trench isolation region is provided with a polysilicon field plate structure;
the polysilicon field plate structure, the shallow groove isolation region and the P-type doped region form a RESURF structure so as to reduce an electric field between the P-type doped region and the N-type drift region.
2. The LDMOS transistor of claim 1, wherein an N + guard ring is disposed in a region where the N-type high-voltage well region borders the shallow trench isolation region;
the N + protection ring and the drain electrode form a double RESURF structure together with the polysilicon field plate structure, the shallow groove isolation region and the P-type doped region.
3. The LDMOS transistor set forth in claim 1 wherein said P-type body region is provided with a P + guard ring, said P + guard ring being connected to the source.
4. The LDMOS transistor set forth in claim 1 wherein said polysilicon field plate structure comprises a polysilicon field plate and a field plate isolation oxide layer.
5. A method of fabricating an LDMOS transistor, said LDMOS transistor being the LDMOS transistor of claim 1, the method comprising:
forming an N-type high-voltage well region, a P-type body region and an N-type drift region on a P-type silicon substrate;
forming a shallow groove isolation region and a P-type doped region;
forming an oxide layer;
depositing polycrystalline silicon on the oxide layer to form a polycrystalline silicon grid and a polycrystalline silicon field plate;
and forming a source electrode in a corresponding area of the P-type body area, and forming a drain electrode in a corresponding area of the N-type drift area.
6. The method for manufacturing the LDMOS transistor of claim 5, wherein the forming of the N-type HVW region, the P-type body region and the N-type drift region on the P-type silicon substrate comprises:
oxidizing the surface of the P-type silicon substrate to form a silicon dioxide thin layer;
photoetching the silicon dioxide thin layer to form a pattern area of an N-type high-voltage well area, a P-type body area and an N-type drift area;
and respectively carrying out N-type ion implantation, P-type ion implantation and N-type ion implantation in the pattern regions of the N-type high-voltage well region, the P-type body region and the N-type drift region, propelling at high temperature, and removing the silicon dioxide thin layer to form the N-type high-voltage well region, the P-type body region and the N-type drift region.
7. The method of manufacturing the LDMOS transistor set forth in claim 5 wherein said forming of the shallow trench isolation region and the P-type doped region comprises:
forming a silicon dioxide thin layer on the surface of a P-type silicon substrate on which an N-type high-voltage well region, a P-type body region and an N-type drift region are formed through thermal oxidation, and depositing silicon nitride on the silicon dioxide thin layer;
photoetching to form a pattern area of the shallow trench isolation area, and etching silicon nitride, a silicon dioxide thin layer and silicon of the N-type drift area by a dry method to form a trench of the shallow trench isolation area;
performing large-angle rotation ion implantation along the groove wall of the groove to form a P-type doped region;
carrying out thermal oxidation treatment on the damage caused by dry etching silicon and ion implantation;
and depositing silicon dioxide in the groove, carrying out surface planarization treatment, removing the silicon nitride and silicon dioxide thin layers on the surface, and carrying out high-temperature annealing to form the shallow groove isolation region.
8. The method of manufacturing an LDMOS transistor set forth in claim 5 wherein said forming an oxide layer comprises:
forming an oxide layer on the surface of the P-type silicon substrate on which the shallow trench isolation region and the P-type doped region are formed through thermal oxidation;
and etching the oxide layer to form a gate oxide layer and a field plate isolation oxide layer.
9. The method of manufacturing an LDMOS transistor set forth in claim 8 wherein said depositing polysilicon over an oxide layer to form a polysilicon gate and a polysilicon field plate comprises:
and depositing polycrystalline silicon on the gate oxide layer and the field plate isolation oxide layer, carrying out N-type ion heavy doping on the polycrystalline silicon, and etching the heavily doped polycrystalline silicon to form a polycrystalline silicon gate and a polycrystalline silicon field plate.
10. The method of manufacturing an LDMOS transistor set forth in claim 5 wherein said forming a source in a corresponding region of the P-type body region and a drain in a corresponding region of the N-type drift region comprises:
heavily doping and injecting N-type ions into a corresponding region of the P-type body region to form a source electrode, heavily doping and injecting N-type ions into a corresponding region of the N-type drift region to form a drain electrode, and heavily doping and injecting N-type ions into a region of the N-type high-voltage well region, which is bordered by the shallow groove isolation region, to form an N + protection ring;
and heavily doping and injecting P-type ions into a region where the P-type body region is adjacent to the source electrode to form a P + protective ring.
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