KR970054416A - Manufacturing method of MOS field effect transistor - Google Patents

Manufacturing method of MOS field effect transistor Download PDF

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Publication number
KR970054416A
KR970054416A KR1019950066095A KR19950066095A KR970054416A KR 970054416 A KR970054416 A KR 970054416A KR 1019950066095 A KR1019950066095 A KR 1019950066095A KR 19950066095 A KR19950066095 A KR 19950066095A KR 970054416 A KR970054416 A KR 970054416A
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South Korea
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manufacturing
effect transistor
field effect
forming
mos field
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KR1019950066095A
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Korean (ko)
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KR100203910B1 (en
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김현수
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김주용
현대전자산업 주식회사
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Publication of KR100203910B1 publication Critical patent/KR100203910B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 모스 전계효과 트랜지스터의 제조방법에 관한 것으로서, 폴리사이드 구조의 게이트전극을 구비하는 MOS FET에서 게이트전극 형성후 전표면에 부도체에 가까운 언도프트 실리콘층을 형성한 후, 후속 공정을 진행하여 산화막 스페이서와 소오스/드레인 영역을 형성하였으므로, 스크림 산화막의 역할을 수행하는 언도포트 실리콘층을 안정적으로 형성할 수 있어 소자의 재현성이 향상되고, 누설전류가 감소되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS field effect transistor. In an MOS FET having a gate electrode having a polyside structure, an undoped silicon layer close to an insulator is formed on the entire surface after a gate electrode is formed, and then a subsequent process is performed. Since the oxide spacer and the source / drain regions are formed, the undoped silicon layer serving as the scrim oxide film can be stably formed, thereby improving device reproducibility and reducing leakage current to improve process yield and device operation reliability. You can.

Description

모스 전계효과 트랜지스터의 제조방법Manufacturing method of MOS field effect transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 모스 전계효과 트랜지스터의 단면도.2 is a cross-sectional view of a MOS field effect transistor according to the present invention.

Claims (6)

반도체기판상에 게이트산화막을 형성하는 공정과, 상기 게이트산화막 상에 게이트전극을 형성하는 공정과, 상기 구조의 전표면에 언도프트 실리콘층을 형성하는 공정과, 상기 게이트전극 양측의 반도체기판에 저농도 불순물 영역을 형성하는 공정과, 상기 게이트전극 측벽의 언도포트 실리콘층상에 산화막 스페이서를 형성하는 공정과, 상기 스페이서 양측의 반도체기판에 고농도 불순물 영역을 형성하여 LDD구조의 소오스/드레인 영역을 형성하는 공정을 구비하는 모스전계효과 트랜지스터의 제조방법.Forming a gate oxide film on the semiconductor substrate, forming a gate electrode on the gate oxide film, forming an undoped silicon layer on the entire surface of the structure, and low concentration on the semiconductor substrate on both sides of the gate electrode. Forming an impurity region, forming an oxide spacer on the undoped silicon layer on the sidewall of the gate electrode, and forming a source / drain region of the LDD structure by forming a high concentration impurity region on the semiconductor substrate on both sides of the spacer. Method of manufacturing a MOS field effect transistor having a. 제1항에 있어서, 상기 게이트전극이 도핑된 다결정실리콘층과 금속-실리사이드막의 적층 구조로 형성하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.2. The method of claim 1, wherein the gate electrode is formed of a stacked structure of a doped polysilicon layer and a metal-silicide layer. 제2항에 있어서, 상기 금속 실리사이드막을 W, Ti, Co, Mo, Ta, Ni, Pb 또는 Zr 로 이루어지는 군에서 임의로 선택되는 하나의 금속 실리사이드막을 사용하는 것을 특징으로하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 2, wherein the metal silicide film is one metal silicide film arbitrarily selected from the group consisting of W, Ti, Co, Mo, Ta, Ni, Pb or Zr. . 제1항에 있어서, 상기 언도포트 실리콘층을 CVD 방법으로 형성하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the undoped silicon layer is formed by a CVD method. 제1항에 있어서, 상기 언도포트 실리콘층을 10∼300Å 두께로 형성하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the undoped silicon layer is formed to a thickness of 10 to 300 kHz. 제1항에 있어서, 상기 언도포트 실리콘층을 400∼800℃ 온도에서 형성하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the undoped silicon layer is formed at a temperature of 400 to 800 占 폚. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066095A 1995-12-29 1995-12-29 Method of manufacturing a mos field effect transistor KR100203910B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100506878B1 (en) * 1997-12-29 2005-10-19 주식회사 하이닉스반도체 Manufacturing method of MOS field effect transistor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100549572B1 (en) * 1999-12-15 2006-02-08 주식회사 하이닉스반도체 Method for forming transistor provided with buffer layer for LDD screen

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100506878B1 (en) * 1997-12-29 2005-10-19 주식회사 하이닉스반도체 Manufacturing method of MOS field effect transistor

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