KR970054418A - Manufacturing method of MOS field effect transistor - Google Patents

Manufacturing method of MOS field effect transistor Download PDF

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Publication number
KR970054418A
KR970054418A KR1019950066182A KR19950066182A KR970054418A KR 970054418 A KR970054418 A KR 970054418A KR 1019950066182 A KR1019950066182 A KR 1019950066182A KR 19950066182 A KR19950066182 A KR 19950066182A KR 970054418 A KR970054418 A KR 970054418A
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KR
South Korea
Prior art keywords
film
effect transistor
field effect
silicide film
mos field
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KR1019950066182A
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Korean (ko)
Inventor
오세중
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김주용
현대전자산업 주식회사
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Priority to KR1019950066182A priority Critical patent/KR970054418A/en
Publication of KR970054418A publication Critical patent/KR970054418A/en

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Abstract

본 발명은 모스 전계효과 트랜지스터의 제조방법에 관한 것으로서, 게이트전극과 P형 소오스/드레인 영역의 면저항 및 접촉저항을 감소시키기 위하여 각각의 상측에 Ti실리사이드막을 구비하는 MOSFET에서 MOSFET의 표면을 보호 평탄화시키는 층간 절연막으로서의 다량의 B을 함유하는 BSG막을 사용하고 일차로 형성된 C49상의 Ti실리사이드막을 안정된 C54상의 Ti실리사이드막으로 안정화시키는 이차 RTP 공정을 상기 BSG막의 재유동 공정과 함께 진행하여 상기 BSG막 내부의 B이 상기 Ti 실리사이드막으로 확산되도록 확산되도록 하여 상기 P-소오스/드레인 영역에서의 B확산을 방지하였으므로, P+ 소오스/드레인 영역 형성을 위한 B이온 주입량을 증가시키지 않아도 되므로 얕은 접합의 형성이 용이하고, 펀치 쓰루 전압이 증가되며, 소자의 전류 구동능력이 향상되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a MOS field effect transistor, and in order to reduce the sheet resistance and contact resistance of a gate electrode and a P-type source / drain region, to protect and planarize the surface of a MOSFET in a MOSFET having a Ti silicide film on the upper side thereof. A secondary RTP process of using a BSG film containing a large amount of B as an interlayer insulating film and stabilizing a Ti silicide film formed on a C49 phase to a stabilized Ti silicide film on a C54 phase proceeds with the reflowing process of the BSG film to perform the B B inside the BSG film. Since diffusion into the Ti silicide layer is diffused to prevent diffusion of B in the P-source / drain region, the amount of B ions implanted for forming the P + source / drain region does not have to be increased, thereby making it easy to form a shallow junction. Increase punch-through voltage, improve device current drive capability A control process yield and reliability of the device operation can be improved.

Description

모스 전계효과 트랜지스터의 제조방법Manufacturing method of MOS field effect transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1E도는 본 발명에 따른 모스 전계효과 트랜지스터의 제조공정도.1A to 1E are manufacturing process diagrams of a MOS field effect transistor according to the present invention.

Claims (6)

반도체 기판상에 게이트 산화막을 형성하는 공정과, 상기 게이트 산화막 상에 게이트전극을 형성하는 공정과, 상기 게이트전극의 양측벽과 반도체 기판에 산화막 스페이서와 소오스 드레인 영역을 형성하는 공정과, 상기 구조의 전표면에 Ti층을 형성하는 공정과, 상기 Ti층을 게이트전극 및 소오스/드레인 영역의 실리콘과 Ti를 반응시켜 Ti실리사이드막을 형성하는 공정과, 상기 반응하지 않은 Ti를 제거하는 공정과, 상기 구조의 전표면에 BSG막을 형성하는 공정과, 상기 BSG막을 재유동시키며 Ti 실리사이드막을 이차 열처리하여 안정화시키는 공정을 구비하는 모스 전계효과 트랜지스터의 제조방법.Forming a gate oxide film on the semiconductor substrate, forming a gate electrode on the gate oxide film, forming an oxide spacer and a source drain region on both sidewalls of the gate electrode and the semiconductor substrate; Forming a Ti layer on an entire surface, forming a Ti silicide film by reacting the Ti layer with silicon in a gate electrode and a source / drain region, and removing a Ti silicide film; Forming a BSG film on the entire surface of the film; and reflowing the BSG film and stabilizing the Ti silicide film by secondary heat treatment. 제1항에 있어서, 상기 Ti층을 1500Å 이하의 두께로 형성하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the Ti layer is formed to a thickness of 1500 Pa or less. 제1항에 있어서, 상기 열처리 공정을 급속 열처리 방법으로서 550∼750℃에서 5∼40초간 실시하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the heat treatment step is performed at 550 to 750 ° C for 5 to 40 seconds as a rapid heat treatment method. 제1항에 있어서, 상기 일차 열처리 후의 Ti실리사이드막이 C49상인 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the Ti silicide film after the primary heat treatment is C49 phase. 제1항에 있어서, 상기 이차 열처리 후의 Ti실리사이드막이 C54상인 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the Ti silicide film after the secondary heat treatment is C54 phase. 제1항에 있어서, 상기 Ti실리사이드막을 Cr,Mo,W 및 Nb등의 실리사이드막으로 대신 형성하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a MOS field effect transistor according to claim 1, wherein the Ti silicide film is formed instead of a silicide film such as Cr, Mo, W, and Nb. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066182A 1995-12-29 1995-12-29 Manufacturing method of MOS field effect transistor KR970054418A (en)

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KR1019950066182A KR970054418A (en) 1995-12-29 1995-12-29 Manufacturing method of MOS field effect transistor

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KR1019950066182A KR970054418A (en) 1995-12-29 1995-12-29 Manufacturing method of MOS field effect transistor

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KR970054418A true KR970054418A (en) 1997-07-31

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010060156A (en) * 1999-12-27 2001-07-06 다니구찌 이찌로오, 기타오카 다카시 Semiconductor device and method of manufacturing the same
KR20030072197A (en) * 2002-03-05 2003-09-13 미쓰비시덴키 가부시키가이샤 Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010060156A (en) * 1999-12-27 2001-07-06 다니구찌 이찌로오, 기타오카 다카시 Semiconductor device and method of manufacturing the same
KR20030072197A (en) * 2002-03-05 2003-09-13 미쓰비시덴키 가부시키가이샤 Method of manufacturing semiconductor device

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