KR970003700A - Manufacturing method of MOS transistor - Google Patents

Manufacturing method of MOS transistor Download PDF

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Publication number
KR970003700A
KR970003700A KR1019950019135A KR19950019135A KR970003700A KR 970003700 A KR970003700 A KR 970003700A KR 1019950019135 A KR1019950019135 A KR 1019950019135A KR 19950019135 A KR19950019135 A KR 19950019135A KR 970003700 A KR970003700 A KR 970003700A
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KR
South Korea
Prior art keywords
source
ion implantation
drain region
titanium
drain
Prior art date
Application number
KR1019950019135A
Other languages
Korean (ko)
Inventor
송택근
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019135A priority Critical patent/KR970003700A/en
Publication of KR970003700A publication Critical patent/KR970003700A/en

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

1. 청구 범위에 지재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 MOSFET 제조 방법은 소스/드레인 영역의 계면과 티타늄실리사이드의 계면과의 거리가 너무 짧아 상기 티타늄실리사이드의 형성 수행시 소스/드레인 영역에 주입된 이온들이 외방확산되어 소스/드레인 영역의 계면과 티타늄실리사이드의 계면간의 저항이 증가하여 결국 모스 트랜지스터의 전기적 특성을 악화시키는 문제점을 해결하고자 함.In the conventional MOSFET fabrication method, the distance between the interface of the source / drain region and the titanium silicide interface is too short. Thus, when the titanium silicide is formed, ions implanted into the source / drain region are diffused outward so that the interface between the source / drain region and titanium To solve the problem that the resistance between silicide's interface increases and eventually worsens the electrical characteristics of MOS transistor.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

측벽 스페이서를 이용하여 두번에 걸친 소스/드레인 이온 주입을 실시하고, 티탄실리사이드 공정을 진행하여 소스/드레인 영역에 주입된 이온들의 외방확산을 방지하므로써 소자의 특성이 양호한 MOSFET 제조 방법을 제공하고자 함.The present invention provides a method for fabricating a MOSFET having good device characteristics by performing two-time source / drain ion implantation using sidewall spacers and a titanium silicide process to prevent outward diffusion of ions implanted into the source / drain region.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 소자의 제조, 특히 모스 트랜지스터의 제조에 이용됨.Used in the manufacture of semiconductor devices, in particular in the manufacture of MOS transistors.

Description

모스 트랜지스터의 제조 방법Manufacturing method of MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명의 모스 트랜지스터의 제조 방법에 따른 제조 공정도.2A to 2E are manufacturing process diagrams according to the manufacturing method of the MOS transistor of the present invention.

Claims (2)

반도체 기판 상에 소자 분리막, 게이트 산화막, 게이트 전극, 저도핑 드레인 영역이 형성된 모스 트랜지스터의 제조방법에 있어서, 전체 구조 상부에 스페이서 산화막을 형성한 후 블랭킷 식각을 실시하여 상기 게이트 전극의 측벽에 제1측벽 스페이서를 형성하는 단계와, 제1소스/드레인 영역을 형성하기 위한 이온 주입을 실시하고, 어닐링을 실시하는 단계와, 전체 구조 상부에 스페이서 산화막을 형성한 후 블랭킹 식각을 실시하여 제2측벽 스페이서를 형성하는 단계와, 제2소스/드레인 영역을 형성하기 위한 이온 주입을 실시하고, 어닐링을 실시하는 단계와, 전체 구조 상부에 티타늄을 증착하는 단계와, 열처리 공정을 수행하여 티타늄실리사이드를 형성하는 단계 및, 반응하지 않은 티타늄을 제거하는 단계를 포함해서 이루어진 모스 트랜지스터의 제조 방법.In the method of manufacturing a MOS transistor having a device isolation film, a gate oxide film, a gate electrode, and a low doping drain region formed on a semiconductor substrate, a spacer oxide film is formed over an entire structure, and a blanket etching is performed to form first spacers on sidewalls of the gate electrode. Forming sidewall spacers, performing ion implantation to form the first source / drain regions, annealing, forming a spacer oxide layer over the entire structure, and then performing a blanking etch to perform second sidewall spacers. Forming titanium oxide, performing ion implantation to form a second source / drain region, performing annealing, depositing titanium on the entire structure, and performing a heat treatment process to form titanium silicide. And removing the unreacted titanium. Manufacturing method. 제1항에 있어서, 상기 제2소오스/드레인 이온 주입 단계의 이온주입 에너지가 제1소스/드레인 이온 주입 단계의 이온 주입 에너지보다도 높은 것을 특징으로 하는 모스 트랜지스터의 제조 방법.The method of claim 1, wherein the ion implantation energy of the second source / drain ion implantation step is higher than the ion implantation energy of the first source / drain ion implantation step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019135A 1995-06-30 1995-06-30 Manufacturing method of MOS transistor KR970003700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019135A KR970003700A (en) 1995-06-30 1995-06-30 Manufacturing method of MOS transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019135A KR970003700A (en) 1995-06-30 1995-06-30 Manufacturing method of MOS transistor

Publications (1)

Publication Number Publication Date
KR970003700A true KR970003700A (en) 1997-01-28

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Application Number Title Priority Date Filing Date
KR1019950019135A KR970003700A (en) 1995-06-30 1995-06-30 Manufacturing method of MOS transistor

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