KR100309137B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR100309137B1 KR100309137B1 KR1019950046318A KR19950046318A KR100309137B1 KR 100309137 B1 KR100309137 B1 KR 100309137B1 KR 1019950046318 A KR1019950046318 A KR 1019950046318A KR 19950046318 A KR19950046318 A KR 19950046318A KR 100309137 B1 KR100309137 B1 KR 100309137B1
- Authority
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- South Korea
- Prior art keywords
- spacer
- amorphous silicon
- semiconductor device
- silicon spacer
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000007790 solid phase Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract 1
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 1
- 238000004151 rapid thermal annealing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001684 chronic effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로서, 특히, 서브 쿼터 마이크론(Sub-Quarter Micron)MOSFET를 제조할 수 있도록 한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of manufacturing a Sub-Quarter Micron MOSFET.
일반적으로 종래의 LDD(lightly-doped drain) 방식에 의한 MOSFET 제조에 있어서는 이온 주입 방식에 의해 고농도의 극히 얕은 접합 영역의 형성하는데 한계가있고 또한 LDD 지역에서의 높은 면 저항(Sheet Resistance)과 소오스 및 드레인 직렬 저항(Source/Drian Series Resistance)및 고질적인 숏 채널 (Short Channel) 효과에 문제가 있는 단점이 있다.In general, in the manufacture of a conventional LDD (lightly-doped drain) MOSFET, the ion implantation method has a limitation in forming a very shallow junction region of high concentration, and also has a high sheet resistance and source and There are drawbacks to the problem of drain series resistance (Source / Drian Series Resistance) and chronic short channel effects.
따라서, 본 발명은 단결정 실리콘 스페이서와 SPD(solid phase diffusion)방법을 사용하므로서 상기한 단점을 해소할 수 있는 반도체 소자의 접합 영역 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a junction region of a semiconductor device which can solve the above-mentioned disadvantages by using a single crystal silicon spacer and a solid phase diffusion (SPD) method.
상기한 목적을 달성하기 위한 본 발명은 실리콘 기판상의 선택된 영역상에 게이트 전극을 형성하는 단계와, 상기 전체 구조 상부에 질화막을 증착하고, 게이트 측벽에 질화막 스페이서를 형성하는 단계와, 상기 질화막 스페이서가 형성된 게이트 측벽에 붕소가 도프된 비정질 실리콘 스페이서을 형성하는 단계와, 상기 비정질 실리콘 스페이서 단결정 실리콘 스페이서로 변화시키는 단계와, 상기 실리콘기판상에 불순물 이온을 주입하여 깊은 소오스 및 드레인 영역을 형성하는 단계와, 상기 전체 소자에 RTA 공정을 실시하여 상기 실리콘 기판에 LDD 영역을 형성하는 단계로 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate electrode on a selected region on a silicon substrate, depositing a nitride film over the entire structure, forming a nitride spacer on a gate sidewall, Forming an amorphous silicon spacer doped with boron on the formed gate sidewalls, changing the amorphous silicon spacer into a single silicon spacer, implanting impurity ions onto the silicon substrate to form deep source and drain regions; RTA process is performed on the entire device to form an LDD region on the silicon substrate.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 1A내지 1E도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
제 1A 도와 관련하여, 실리콘 기판(1)상에 게이트 산화막(2), 폴리 실리콘(3)이 적층된 된 게이트 전극(4)이 형성된다.In relation to the first A diagram, a gate electrode 4 having a gate oxide film 2 and a polysilicon 3 laminated thereon is formed on the silicon substrate 1.
제 1B도와 관련하여, 상기 전체 구조 상부에 질화막이 증착되고, 식각 공정에 의해 게이트 전극(4)측벽에 질화막 스페이서 (5)가 형성된다. 상기 질화막 스페이서(5) 측벽에 인 시투(In-Situ) 공정에 의해 붕소가 도프된 비정질 실리콘스페이서(Boron Doped Amorphous-Silicon Sidewall)(6A)을 형성한다. 이 때, 낮은 온도, 예를들어 350℃에서 비정질 실리콘을 증착하면 증착면에서 산소농도가 억제되기때문에 비정질 실리콘과 기판사이의 자연산화막(Native Oxide)을 배제시킬 수 있다.In connection with FIG. 1B, a nitride film is deposited over the entire structure, and a nitride film spacer 5 is formed on the side wall of the gate electrode 4 by an etching process. Boron-doped amorphous silicon spacers 6A are formed on sidewalls of the nitride film spacer 5 by an in-situ process. At this time, when the amorphous silicon is deposited at a low temperature, for example, 350 ° C., since the oxygen concentration is suppressed at the deposition surface, the native oxide layer between the amorphous silicon and the substrate may be excluded.
제 1C 도와 관련하여, 상기 비정질 실리콘 스페이서(6A)은 600℃의 질소(N2) 분위기에서의 열처리에 의해 재결정화되어 단결정 실리콘 스페이서(Single Crystal Silicon-Sidewall)(6B)로 변화된다. 그로 인하여 임플랜팅에 의한 손상을 배제할 수 있다. 상기 실리콘 기판(1)상에 BF2이온이 주입되어 깊은 소오스 및 드레인 영역(7A)이 형성된다.In relation to the first C diagram, the amorphous silicon spacer 6A is recrystallized by heat treatment in a nitrogen (N 2 ) atmosphere at 600 ° C. to be changed into a single crystal silicon spacer 6B. Thereby, the damage by implantation can be excluded. BF 2 ions are implanted onto the silicon substrate 1 to form deep source and drain regions 7A.
제 1D 도와 관련하여, 상기 전체 소자에 RTA(Rapid Thermal Anneal) 공정을 1000℃온도에서 10초간 실시하면 상기 단결정 실리콘 스페이서(6B) 내의 붕소가 실리콘기판(1)내로 전파되어 LDD 영역(7B)이 형성된다. 이러한 공정 방법을 SPD(Solid Phase Diffusion)이라고 한다.Regarding the 1D diagram, when the Rapid Thermal Anneal (RTA) process is performed on the entire device for 10 seconds at a temperature of 1000 ° C., boron in the single crystal silicon spacer 6B is propagated into the silicon substrate 1, so that the LDD region 7B is formed. Is formed. This process method is called Solid Phase Diffusion (SPD).
제 1E 도와 관련하여, 전체 구조 상부에 Ti가 증착되고 실리사이데이션(Silicidation) 공정으로 티타늄실리사이드(8)가 형성된다.In relation to the first E diagram, Ti is deposited on the entire structure and titanium silicide 8 is formed by a silicidation process.
상술한 바와 같이 본 발명에 의하면 단결정 실리콘 스페이서와 SPD(solid phase diffusion)방법을 사용하므로서 숏 채널 효과를 억제할 수 있고 또한 소오스 및 드레인 직렬 저항을 감소할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the short channel effect can be suppressed and the source and drain series resistance can be reduced by using a single crystal silicon spacer and a solid phase diffusion (SPD) method.
제 1A 내지 1E도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 실리콘 기판 2 : 게이트 산화막1 silicon substrate 2 gate oxide film
3 : 폴리 실리콘 4 : 게이트 전극3: polysilicon 4: gate electrode
5 : 질화막 스페이서 6A : 비정질 실리콘 스페이서5: nitride film spacer 6A: amorphous silicon spacer
6B : 단결정 실리콘 스페이서 7A : 소오스 및 드레인 영역6B: single crystal silicon spacer 7A: source and drain region
7B : LDD 영역 8 : 티타늄 실리 사이드7B: LDD Zone 8: Titanium Silicide
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046318A KR100309137B1 (en) | 1995-12-04 | 1995-12-04 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046318A KR100309137B1 (en) | 1995-12-04 | 1995-12-04 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053012A KR970053012A (en) | 1997-07-29 |
| KR100309137B1 true KR100309137B1 (en) | 2003-07-07 |
Family
ID=37530752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950046318A KR100309137B1 (en) | 1995-12-04 | 1995-12-04 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100309137B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH021938A (en) * | 1988-06-09 | 1990-01-08 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH05267328A (en) * | 1992-03-18 | 1993-10-15 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH05343418A (en) * | 1992-06-09 | 1993-12-24 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US5393685A (en) * | 1992-08-10 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Peeling free metal silicide films using rapid thermal anneal |
-
1995
- 1995-12-04 KR KR1019950046318A patent/KR100309137B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH021938A (en) * | 1988-06-09 | 1990-01-08 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH05267328A (en) * | 1992-03-18 | 1993-10-15 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH05343418A (en) * | 1992-06-09 | 1993-12-24 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US5393685A (en) * | 1992-08-10 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Peeling free metal silicide films using rapid thermal anneal |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053012A (en) | 1997-07-29 |
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