KR970018701A - Method of manufacturing transistor in semiconductor device - Google Patents

Method of manufacturing transistor in semiconductor device Download PDF

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Publication number
KR970018701A
KR970018701A KR1019950031080A KR19950031080A KR970018701A KR 970018701 A KR970018701 A KR 970018701A KR 1019950031080 A KR1019950031080 A KR 1019950031080A KR 19950031080 A KR19950031080 A KR 19950031080A KR 970018701 A KR970018701 A KR 970018701A
Authority
KR
South Korea
Prior art keywords
forming
semiconductor device
melting point
high melting
polysilicon layer
Prior art date
Application number
KR1019950031080A
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Korean (ko)
Inventor
김재웅
엄중섭
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950031080A priority Critical patent/KR970018701A/en
Publication of KR970018701A publication Critical patent/KR970018701A/en

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

고집적 반도체장치에 있어서, 핫캐리어에 의한 소자 특성의 열화를 방지하는 트랜지스터의 제조방법에 관한 것으로, 반도체장치의 트랜지스터의 제조방법은, 상기 반도체기판 상의 전면에 게이트산화막을 형성하는 단계, 상기 게이트산화막 상에 다결정실리콘층을 도포하고 패터닝하여 개구부를 형성하는 단계, 상기 개구부의 내측벽에 스페이서를 형성하는 단계, 상기 다결정실리콘층을 제거하는 단계, 상기 스페이서들 사이의 반도체기판에 다른 다결정 실리콘층과 고융점실리사이드인 텅스텐실리사이드를 순차적으로 적층하여 게이트전극을 형성하는 단계 및 상기 고융점실리사이드가 형성된 기판전면에 이온주입공정을 실시하여 소오스영역 및 드레인영역을 형성하는 단계를 구비하여, 종래의 방법으로 형성된 트랜지스터에서 문제가 되는 강한 전계에 의한 핫캐리어 생성과 그에 따른 게이트에지(특히 드레인영역부분) 부분의 전자트랩 및 관통현상에 의한 게이트산화막의 열화 및 손상을 효과적으로 방지하여 반도체 소자의 신뢰성을 향상시킨다.In a highly integrated semiconductor device, a method of manufacturing a transistor that prevents deterioration of device characteristics by a hot carrier, the method of manufacturing a transistor of a semiconductor device, the method comprising: forming a gate oxide film on the entire surface of the semiconductor substrate, the gate oxide film Forming an opening by applying and patterning a polysilicon layer on the substrate, forming a spacer on an inner wall of the opening, removing the polysilicon layer, and forming another polycrystalline silicon layer on the semiconductor substrate between the spacers. Forming a gate electrode by sequentially stacking tungsten silicide, which is a high melting point silicide, and forming a source region and a drain region by performing an ion implantation process on the entire surface of the substrate on which the high melting point silicide is formed; Steel problematic in transistors formed To effectively prevent the deterioration and damage of the gate oxide film by the electron traps and through the phenomenon of hot carrier generation, and hence the gate-edge of the electric field (in particular the drain region portion) portion to improve the reliability of the semiconductor device.

Description

반도체 장치의 트랜지스터 제조방법Method of manufacturing transistor in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 트랜지스터의 단면도이다.5 is a cross-sectional view of a transistor according to the present invention.

Claims (3)

소자분리산화막에 의해 한정되는 반도체기판을 가지는 반도체장치의 제조방법에 있어서, 반도체 기판 상에 다결정실리콘층을 도포하고 패터닝하여 개구부를 형성하는 단계, 상기 개구부의 내측벽에 스페이서를 형성하는 단계, 상기 다결정실리콘층을 제거하는 단계, 상기 스페이서들 사이의 반도체기판에 다른 다결정실리콘층과 고융점금속실리사이드를 순차적으로 적층하는 단계, 및 상기 고융점실리사이드가 형성된 기판전면에 이온주입공정을 실시하여 소오스영역 및 드레인영역을 형성하는 단계를 구비함을 특징으로 하는 반도체장치의 제조방법.A method of manufacturing a semiconductor device having a semiconductor substrate defined by an element isolation oxide film, the method comprising: forming an opening by applying and patterning a polysilicon layer on a semiconductor substrate, forming a spacer on an inner wall of the opening, Removing the polysilicon layer, sequentially laminating another polysilicon layer and a high melting point metal silicide on the semiconductor substrate between the spacers, and performing an ion implantation process on the entire surface of the substrate on which the high melting point silicide is formed; And forming a drain region. 제1항에 있어서, 상기 고융점실리사이드가 텅스텐실리사이드임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said high melting point silicide is tungsten silicide. 제1항에 있어서, 상기 순차적으로 적층된 다결정실리콘층과 고융점금속실리사이드가 게이트전극임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the sequentially stacked polysilicon layer and the high melting point metal silicide are gate electrodes. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950031080A 1995-09-21 1995-09-21 Method of manufacturing transistor in semiconductor device KR970018701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950031080A KR970018701A (en) 1995-09-21 1995-09-21 Method of manufacturing transistor in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950031080A KR970018701A (en) 1995-09-21 1995-09-21 Method of manufacturing transistor in semiconductor device

Publications (1)

Publication Number Publication Date
KR970018701A true KR970018701A (en) 1997-04-30

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KR1019950031080A KR970018701A (en) 1995-09-21 1995-09-21 Method of manufacturing transistor in semiconductor device

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KR (1) KR970018701A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100470126B1 (en) * 2002-09-17 2005-02-05 동부아남반도체 주식회사 Method for forming gate of semiconductor element
KR100461336B1 (en) * 1997-12-27 2005-04-06 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100461336B1 (en) * 1997-12-27 2005-04-06 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100470126B1 (en) * 2002-09-17 2005-02-05 동부아남반도체 주식회사 Method for forming gate of semiconductor element

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