JPH0498850A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make small the difference between the concentration of an impurity layer having an impurity concentration of a type opposite to that of the substrate and the concentration of the junction surface between the impurity layer and an impurity layer forming a transistor under an element isolation region, to spread a depletion layer, to make small a parasitic capacitance and to increase the operating speed of a semiconductor device by a method wherein an impurity concentration of the same type as that of the substrate is made high at one part only under the element isolation region of the device. CONSTITUTION:An oxide film and a nitride film 1 are formed on a P-type silicon semiconductor substrate 6 and a part, which is used as an element isolation region 7, of the film 1 is etched. Then, a place other than one part, which is located under the element isolation region and at which the concentration of a P<+> impurity layer 3 having an impurity concentration of the same type as that of the substrate is made high, is covered with a photoresist 2 and a high-concentration part 3 of the impurity layer is formed by ion-implantation. Then, the photoresist 2 is removed and an oxidation is performed using the film 1 as a mask to form the element isolation region 7. Moreover, the film 1 is removed, a gate oxide film, gate electrodes 5 and N-type impurity layers 4 are formed and a semiconductor device is completed. Thereby, the depletion layer is made broad, the parasitic capacitance is reduced and the operating speed of the device can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an element isolation region of a semiconductor device.

[Conventional technology]

In the conventional semiconductor device, as shown in FIG. 2, the concentration of impurities of the same type as the semiconductor substrate is higher than that of the semiconductor substrate under the element isolation region of the N-type or P-type transistor formation region.

[Problem to be solved by the invention]

In this conventional semiconductor device, the impurity concentration in the entire area under the isolation region is high, and as shown in FIG. Since the difference in the concentration of layer 3 is large, the width of the depletion layer at the junction surface becomes narrow, and the parasitic capacitance becomes large. This has resulted in a reduction in the operating speed of the semiconductor device.

An object of the present invention is to reduce the concentration difference at the junction surface between the impurity layer of the opposite type to the substrate forming the transistor and the impurity layer forming the transistor under the element isolation region, widening the depletion layer, and thereby reducing the parasitic capacitance. An object of the present invention is to provide a semiconductor device that can reduce the size of the semiconductor device and increase the operating speed of the semiconductor device.

[Means to solve the problem]

In the element isolation region of the semiconductor device of the present invention, by increasing the concentration of only a portion of the impurity layer of the same type as the substrate under the element isolation region, a high concentration impurity layer of the same type as the substrate and an impurity layer of the opposite type to the substrate can be formed. As a result, the width of the air debris formed around the impurity layer of the opposite type to the substrate increases over the entire surface of the junction, reducing the parasitic capacitance at the junction. This effect can be obtained.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor device shown in the order of steps for explaining the structure and manufacturing method of an embodiment of the present invention.

In the method for manufacturing a semiconductor device of the present invention, first, as shown in FIG. 1(a), an oxide film is formed on a silicon substrate.

Form a nitride film and etch the nitride film in the part that will become the device isolation region. Cover the parts under the device isolation region with photoresist except for increasing the concentration of the impurity layer of the same type as the substrate, and perform ion implantation. Therefore, the part 3 with high concentration of the impurity layer
form.

Next, as shown in FIG. 1(b), the photoresist 2 is removed, and the element isolation region 7 is oxidized using the nitride film 1 as a mask.
form.

Next, as shown in FIG. 1(c), the nitride film is removed, and the gate oxide film, gate electrode 5, and N
A type impurity layer 4 is formed to complete the semiconductor device.

By increasing the concentration of the impurity layer of the same type as the part of the substrate under the element isolation region, it is possible to bond the impurity layer of the opposite type to the substrate forming the transistor and the impurity layer of the same type as the part of the substrate under the element isolation region. The difference in the concentration of impurities on the plane becomes smaller, and the width of the depletion layer becomes wider than before, so the parasitic capacitance becomes smaller.

〔Effect of the invention〕

As explained above, in the present invention, by increasing the concentration of the impurity layer of the same type as the substrate only in a part under the element isolation region of the semiconductor, the impurity layer of the opposite type to the substrate forming the transistor and the impurity layer under the element isolation region are formed. Since the concentration difference at the junction surface with the impurity layer forming the transistor becomes smaller, the depletion layer becomes wider, the parasitic capacitance becomes smaller, and the operating speed of the semiconductor device is increased.

[Brief explanation of drawings]

FIGS. 1A to 1C are FR side views of a semiconductor device shown in order of steps to explain the structure and manufacturing method of an embodiment of the present invention, and FIG. 2 is an example of a conventional semiconductor device. FIG. 1...Nitride film, 2...Photoresist, 3...P
type impurity layer, 4... N type impurity layer, 5... Kate electrode, 6... P type semiconductor substrate, 7... Element isolation region.

Claims (1)

[Claims] A semiconductor device characterized in that the concentration of an impurity of the same type as a substrate is increased only in a portion under an element isolation region of the semiconductor device.