JPH04359567A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a MOS semiconductor device wherein the effect of a channel depletion layer is reduced and a high driving capacity and a high-speed performance are realized. CONSTITUTION:A shallow p-type well 4 is formed in a region surrounded with an element isolation oxide film 2 on an n-type silicon substrate 1 and a gate electrode 8 is formed on this well 4 via a gate oxide film 7. second p-type wells 5 and 6 deeper than the well 4 are formed in the substrate surface, in which source and drain regions are formed, holding the electrode 8 between them and source and drain layers 9 and 10 are respectively formed by deposition on these wells 5 and 6 in a state that the layers 9 and 10 are isolated from the electrode 8 by an oxide film 11.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device having a shallow well structure and a method for manufacturing the same.

0002

2. Description of the Related Art The degree of integration of MOS type integrated circuits has been increasingly improved by miniaturizing elements. As is well known, element miniaturization is carried out in accordance with the scaling law, but miniaturization causes various problems in terms of element characteristics.

The first problem is that carrier mobility and carrier density in the inversion channel layer decrease. In a MOSFET, when a gate bias is applied, a depletion layer first expands in the substrate, and when the gate bias reaches a certain value, an inversion channel is formed and the device turns on. At this time, the space charge in the depletion layer works to strengthen the effective gate electric field, which works in the direction of reducing the carrier mobility of the channel. However, if the way the depletion layer spreads does not change even when miniaturized, , the effect will be relatively large. Furthermore, since a portion of the gate bias is spent on forming a depletion layer, when the impurity concentration of the substrate is increased according to the scaling law, the gate electric field component applied to the inversion channel in the substrate decreases, and the carrier density in the channel layer decreases. this is,
This causes a reduction in the driving ability of the MOSFET.

The second problem is a decrease in high-speed performance due to an increase in parasitic capacitance. As described above, when the substrate impurity concentration is increased according to the scaling law, the width of the depletion layer becomes smaller, and the capacitance of the depletion layer becomes relatively larger.

The third problem is an increase in subthreshold current. The subthreshold current depends on the depletion layer width and channel length, but for MOS with small channel length,
For FETs, the S factor (=dVG /d log
ID) will be small.

[0006]

[Problem to be solved by the invention] As described above, the conventional M
In OSFETs, miniaturization has increased the influence of the depletion layer extending into the substrate at the gate portion, resulting in problems such as a decrease in drive capability, a decrease in high-speed performance, and an increase in subthreshold current.

[0007] The present invention was made in view of the above points, and is an M that can exhibit high performance even when miniaturized.
An object of the present invention is to provide an OS type semiconductor device and a method for manufacturing the same. [Structure of the invention]

[0008]

[Means for Solving the Problems] A semiconductor device according to the present invention has a thin second conductivity type well in an element formation region surrounded by an element isolation insulating film of a first conductivity type semiconductor substrate. A gate electrode is formed via a gate insulating film on the surface of the conductive well, and source and drain layers of a first conductive type separated from the gate electrode by an insulating film are deposited across the gate electrode.

In the present invention, in such a structure, the thickness of the portion of the second conductivity type well below the gate electrode is xj1, and when a voltage is applied to the gate electrode, the thickness of the second conductivity type well is The maximum depletion layer width that extends is Wg, and the maximum depletion layer width that extends from the junction surface of the second conductivity type well and the substrate to the second conductivity type well side when a voltage is applied to the substrate is Ws.
The thickness of the second conductivity type well is set so that xj1<Wg +Ws is satisfied.

The method of the present invention, when manufacturing a semiconductor device as described above, includes the steps of forming a second conductivity type well in a region surrounded by an element isolation insulating film of a first conductivity type semiconductor substrate; A step of forming a gate electrode on the surface of the second conductivity type well via a gate insulating film, and after forming an insulating film on the sidewalls of the gate electrode, a first conductivity type well is formed on the surface of the second conductivity type well with the gate electrode in between. The method is characterized by comprising a step of depositing source and drain layers.

[0011]

[Operation] According to the present invention, in a MOSFET with a well structure, by setting the thickness of the portion of the second conductivity type well below the gate electrode to be small as described above, the depletion layer extending into the active layer due to gate bias is reduced. The extension is limited, and as a result, the gate bias is effectively used to form the inversion channel.

[0012] Limiting the extension of the depletion layer improves the carrier mobility and carrier density of the inversion channel, thereby providing a fine MOSFET with high driving ability and high-speed performance. Furthermore, limiting the extension of the depletion layer by the gate bias leads to a reduction in subthreshold current and improves the cutoff characteristics of the MOSFET. Further, under the inversion channel, the depletion layer extending from the gate side due to the gate bias and the depletion layer extending from the substrate side due to the substrate bias are easily connected, so the width of the depletion layer becomes large as a whole, and the depletion layer capacitance is reduced. This also leads to improvement in the high-speed performance of the MOSFET.

Further, the source and drain layers are formed not inside the second conductivity type well but on the second conductivity type well,
A substantially recessed channel structure is obtained. In particular, if the source and drain layers are formed so that part of them extends over the element isolation insulating film, the pn junction capacitance of the source and drain can be made small, and high-speed operation becomes possible. Furthermore, if the thickness under the source and drain layers is set thicker than the thickness under the gate electrode of the second conductivity type well,
It is possible to prevent punch-through from occurring between the drain and the substrate when a voltage is applied to the drain.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a MOSF according to an embodiment of the present invention.
This is a cross-sectional structure of ET. An element isolation oxide film 2 is formed in the element isolation region of the n-type silicon substrate 1 by a LOCOS method or the like, and a p+ type anti-inversion layer 3 is formed under the element isolation oxide film 2. On the substrate surface of the element formation region surrounded by the element isolation oxide film 2, a shallow p-type well 4 is formed in the channel region, and a deeper p-type well 5 is formed in the source and drain regions continuously. , 6 are formed.

A gate electrode 8 is formed on the surface of the p-type well 4 with a gate oxide film 7 interposed therebetween. N-type source and drain layers 9 and 10 are deposited to extend from the p-type wells 5 and 6 onto the element isolation oxide film 2 with the gate electrode 8 in between. Here, source layer 9, drain layer 1
0 are monocrystalline silicon layers 91 and 101 on the p-type wells 5 and 6, respectively, and polycrystalline silicon layers 92 and 102 continuous thereon on the element isolation oxide film 2. By solid phase diffusion from these source and drain layers 9 and 10, extremely thin n-type layers 12 and 13 are formed on the surfaces of p-type wells 5 and 6. The gate electrode 8 and the source layer 9 and drain layer 10 are electrically isolated by an oxide film 11 formed on the sidewalls of the gate electrode 8.

The substrate on which the gate, source, and drain are formed is covered with, for example, a CVD oxide film 16, contact holes are formed in this, and source and drain electrodes 14 and 15 are formed.

FIG. 2 is an enlarged view of the main parts of FIG. 1 to show the dimensional relationship of each part. In this embodiment, the thickness of the p-type well 4 under the gate electrode is xj1, and the thickness of the p-type wells 5 and 6 under the source and drain layers 9 and 10 is xj2.
<xj2...(1) is set.

Wg in FIG. 2 indicates that when a bias is applied to the gate electrode 8, the p-type well 4 is removed from the interface of the gate oxide film 7.
Indicates the maximum depletion layer width extending within the substrate 1 and p
It shows the maximum depletion layer width extending from the p-n junction surface to the p-type well 4 side when a bias is applied between the type wells 4. In relation to these depletion layer widths, the above-mentioned thicknesses xj1 and xj2
is set to satisfy the following conditional expression xj1<Wg +Ws (2).

Furthermore, Wd is the maximum depletion layer width that extends into the p-type wells 5 and 6 below when a voltage is applied to the source and drain, and in relation to this, the thickness xj2 of the p-type wells 5 and 6 is , xj2>Wd +Ws (3).

FIGS. 3 and 4 show the MO according to this embodiment.
The manufacturing process of SFET is shown. As shown in FIG. 3A, an element isolation oxide film 2 and a p+ type inversion prevention layer 3 are formed on an n-type silicon substrate 1 by a well-known LOCOS process. Next, a first p-type well 4 is formed by B+ ion implantation. Thereafter, as shown in FIG. 3(b), a 20 nm thick gate oxide film 7 is formed by thermal oxidation, and then a 20 nm thick n-type polycrystalline silicon layer is deposited and patterned to form a gate electrode 8.

Next, as shown in FIG. 3(c), an oxide film 11 is formed around the gate electrode 8 and on the exposed surface of the substrate. Then, B+ ions are implanted again to form second p-type wells 5 and 6 self-aligned with the gate electrode 8 on the substrate surface. The second p-type wells 5 and 6 are continuous with the first p-type well 4 and are deeper than the first p-type well 4.

Next, as shown in FIG. 4(a), of the oxide film 11 formed on the surface of the gate electrode 8 and the substrate surface, the oxide film on the side walls of the gate electrode 8 is left, and an anisotropic film is formed. Remove by etching. Then, epitaxial growth of silicon is performed to form n-type single crystal silicon layers 91 and 101 on the surfaces of the p-type wells 5 and 6, and an n-type polycrystalline silicon layer 92 on the element isolation oxide film 2.
, 102 are formed. A polycrystalline silicon film layer 21 is also grown on the gate electrode 8 . The thickness of these silicon layers is
The thickness is smaller than the thickness of the gate electrode 8, for example, about 100 nm. As a result, the source layer 9 and the drain layer 10 are automatically separated and formed with the gate electrode 8 in between. After that, heat treatment was performed at 900°C for 30 minutes, and the source layer 9
, very thin n-type layers 12 and 13 are formed on the surfaces of p-type wells 5 and 6 by solid phase diffusion from drain layer 10.

Next, as shown in FIG. 4(b), a photoresist pattern 22 is formed by a photolithography process.
Using this as a mask, the polycrystalline silicon film 21 on the gate electrode 8 is etched away.

After removing the photoresist pattern 22, as shown in FIG.
6 is deposited, contact holes are made, and source and drain electrodes 14 and 15 are formed through deposition and patterning of an Al film.
form.

According to this embodiment, conditional expressions (1) and (2)
By setting the thickness of the p-type well 4 as shown in
The way the depletion layer extends into the p-type well 4 is restricted by the gate bias. As a result, high drive ability and high-speed performance in a fine MOSFET, as well as excellent cutoff characteristics can be obtained. Furthermore, if a predetermined substrate bias is applied, under the inversion channel, the depletion layer extending from the gate side due to the gate bias and the depletion layer extending from the substrate side due to the substrate bias are easily connected, and the depletion layer capacitance becomes small.

Furthermore, as shown in conditional expressions (1) and (3),
By setting the thickness of the p-type wells 5 and 6 in the source and drain regions, punch-through between the drain region and the substrate is prevented.

FIGS. 5 and 6 show the manufacturing process of another embodiment to obtain the structure of FIG. As shown in FIG. 5(a), first, element isolation regions are formed in the same manner as in the previous embodiment, and the first
After forming a p-type well 4, a gate oxide film 7 is formed, and a 200 nm thick polycrystalline silicon film 80 and a 100 nm thick oxide film 23, which will become a gate electrode, are successively formed thereon. Next, as shown in FIG. 5(b), the laminated film of the oxide film 23 and the polycrystalline silicon film 80 is patterned to form the gate electrode 8 covered with the oxide film 23.

Thereafter, as shown in FIG. 5(c), an oxide film 11 is formed on the side walls of the gate electrode 8 and the exposed surface of the substrate. Then, by ion implantation, a second layer is formed on both sides of the gate electrode 8.
p-type wells 5 and 6 are formed.

Next, as in the previous embodiment, as shown in FIG. 6(a), of the oxide film 11 formed on the surface of the gate electrode 8 and the substrate surface, the oxide film on the side wall portion of the gate electrode 8 is removed. is removed by anisotropic etching, and silicon is epitaxially grown to form n-type single crystal silicon layers 91 and 101 on the surfaces of p-type wells 5 and 6.
, an n-type polycrystalline silicon layer 92 is formed on the element isolation oxide film 2.
, 102 are formed. A polycrystalline silicon film layer 21 is also grown on the gate electrode 8 . Thereafter, heat treatment is performed at 900° C. for 30 minutes to form very thin n-type layers 12 and 13 on the surfaces of p-type wells 5 and 6 by solid phase diffusion from source layer 9 and drain layer 10.

Then, as shown in FIG. 6B, a photoresist pattern 22 is formed by a photolithography process, and using this as a mask, the polycrystalline silicon film 21 on the gate electrode 8 is etched away.

After removing the photoresist pattern 22, as shown in FIG.
6 is deposited, contact holes are made, and source and drain electrodes 14 and 15 are formed through deposition and patterning of an Al film.
form.

According to the method of this embodiment, in the process of forming p-type wells 5 and 6 in the source and drain regions by ion implantation, doping of p-type impurities into gate electrode 8 is simultaneously prevented. This embodiment also provides a MOSFET with excellent characteristics similar to those of the previous embodiment.

FIG. 7 shows yet another example of a manufacturing process for obtaining a similar device. After passing through the steps of forming an element isolation region, forming a p-type well 4, and forming a gate oxide film 7 in the same way as in the previous embodiment, a gate electrode 8 made of polycrystalline silicon and its gate electrode 8 are formed, as shown in FIG. 7(a). A structure is formed in which a high melting point metal silicide film (for example, a tungsten silicide film) 24 is laminated thereon. This can be obtained by successively depositing a polycrystalline silicon layer and a high melting point metal, and patterning these laminated films. Thereafter, an oxide film 11 is formed on the side walls of the gate electrode 8 and the exposed surface of the substrate.

Thereafter, as shown in FIG. 7(b), silicon is epitaxially grown to form source and drain layers 9 and 10. Then, as shown in FIG. 7C, a photoresist pattern 22 is formed, and using this as a mask, the polycrystalline silicon film layer 21 and silicide film 24 on the gate electrode 8 are etched away. The rest is the same as in the previous embodiment.

According to this embodiment, when unnecessary polycrystalline silicon layer 21 on gate electrode 8 is etched, silicide film 24 serves as a stopper, and film reduction of gate electrode 8 is prevented. This embodiment also provides a MOSFET with excellent characteristics similar to those of the previous embodiment. FIG. 8 shows an example in which the source layer 31 and the drain layer 32 are formed not by epitaxial growth but by using polycrystalline silicon layers by CVD or the like.

FIG. 9 shows the manufacturing process for obtaining the structure of this embodiment. FIG. 9(a) shows a state in which, after forming the structure of FIG. 5(c) in the same process as the embodiment of FIG. 5, an n-type polycrystalline silicon layer 30 is deposited on the entire surface by CVD. .

Thereafter, as shown in FIG. 9(b), the polycrystalline silicon layer 30 is selectively etched using a photoresist mask to separate it into a source layer 31 and a drain layer 32. Then, the n-type layers 12 and 13 are formed by solid phase diffusion from the source layer 31 and drain layer 32. Thereafter, an oxide film 16 is deposited in the same manner as in the previous embodiments, contact holes are formed, and a source electrode 14 and a drain electrode 15 are formed using an Al film. This embodiment also provides the same effects as those of the previous embodiments.

In the above embodiment, only n-channel MO
Although the SFET has been described, it goes without saying that the present invention can be similarly applied to a p-channel MOSFET in which the conductivity types of each part are reversed.

[0040]

As explained above, according to the present invention, by using a structure in which a shallow well is formed in the channel region,
It is possible to provide a micro MOSFET that achieves high drive capability and high-speed performance.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a MOSFET according to an embodiment of the present invention.

FIG. 2 is an enlarged view of the main part of FIG. 1;

FIG. 3 is a diagram showing the first half of the first manufacturing process of the same example.

FIG. 4 is a diagram showing the latter half of the first manufacturing process.

FIG. 5 is a diagram showing the first half of the second manufacturing process of the same example.

FIG. 6 is a diagram showing the second half of the second manufacturing process.

FIG. 7 is a diagram showing a third manufacturing process of the same example.

FIG. 8 is a sectional view showing a MOSFET of another example.

FIG. 9 is a diagram showing the manufacturing process of the same example.

[Explanation of symbols]

1...n-type silicon substrate, 2...Element isolation oxide film, 3...inversion prevention layer, 4...first p-type well, 5, 6... second p-type well, 7...Gate oxide film, 8...gate electrode, 9, 10...source, drain layer, 11...Oxide film, 12, 13...n-type layer, 14, 15...source, drain electrode, 16...CVD oxide film, 22...Photoresist pattern, 23...Oxide film, 24...High melting point metal silicide film, 31, 32...source, drain layer.

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type, and a second semiconductor substrate formed in an element formation region surrounded by an element isolation insulating film of the substrate.
A conductivity type well, a gate electrode formed on the second conductivity type well via a gate insulating film, and the gate electrode deposited on the surface of the second conductivity type well with the gate electrode sandwiched therebetween. a first conductivity type source and drain layer separated by an insulating film, a thickness of a portion of the second conductivity type well below the gate electrode is xj1, and when a voltage is applied to the gate electrode, the gate insulation The maximum depletion layer width extending from the film interface into the second conductivity type well is Wg,
When a maximum depletion layer width extending from the junction surface of the second conductivity type well and the substrate toward the second conductivity type well side when a voltage is applied to the substrate is Ws, the second A semiconductor device characterized in that the thickness of a portion of a conductive well below a gate electrode is set. 2. A step of forming a second conductivity type well on a surface of a first conductivity type semiconductor substrate; and a step of forming a gate electrode on the surface of the second conductivity type well with a gate insulating film interposed therebetween.
The method further comprises the step of forming an insulating film on the sidewalls of the gate electrode, and then depositing source and drain layers of the first conductivity type on the surface of the second conductivity type well with the gate electrode in between. A method for manufacturing a semiconductor device.