JPH08330578A - High breakdown voltage field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE: To provide a high breakdown voltage field-effect transistor wherein both reliability and current drive ability are high, by reducing parasitic resistance caused by an offset drain region. CONSTITUTION: A lightly doped region 35 and an SiO2 film 36 on the region 35 are formed. A gate electrode a part of which is superposed with a part of the SiO2 film 36 is formed of a polycrystalline Si film 42. After a part of the SiO2 film 36 which part is not covered with the polycrystalline Si film 42 is eliminated, an impurity region 45 as a drain region is formed. Thereby the length wherein the SiO2 film 36 is superposed with the polycrystalline Si film 42 becomes the length of an offset drain region, and can be made shorter than the working minimum width.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect type high breakdown voltage transistor, which is called a LOCOS offset drain structure and has an offset drain region provided under a field insulating film, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional example of an NMOS type high breakdown voltage transistor having a LOCOS offset drain structure, which is included in a CMOS type semiconductor device. To manufacture this conventional example, as shown in FIG. 6, a SiO ₂ film 12 is formed on the surface of a Si substrate 11 having a P-type or P-well by thermal oxidation, and this SiO ₂ film 12 is formed.
A SiN film 13 is deposited on the film 12 by the CVD method or the like.

Next, as shown in FIG. 7A, the field region and the offset drain of the NMOS high withstand voltage transistor are covered by covering the source region, the drain region and the channel region where the NMOS high withstand voltage transistor is to be formed. A resist 14 having a pattern having an opening 14a is formed on a portion where a region is to be formed, and the resist 14 is formed by photolithography.
It is formed on the N film 13. Then, the SiN film 13 is etched using the resist 14 as a mask.

Next, as shown in FIG. 7B, the resist 1
4 is removed, and a resist (not shown) having a pattern having an opening only on the portion where the offset drain region of the NMOS high breakdown voltage transistor is to be formed is formed by photolithography. Then, using this resist as a mask, S
Impurities are ion-implanted into the i substrate 11 to form an N-type impurity region 15 having a relatively low concentration.

After that, the resist is removed and the SiN film 13 is removed.
Is used as an anti-oxidation mask for thermal oxidation, thermal diffusion, etc.
An SiO ₂ film 16 having a film thickness of about 500 nm is formed in a portion where the N film 13 is not provided, and the impurities in the impurity region 15 are activated. Then, the SiN film 13 is removed by etching or the like.

Next, as shown in FIG. 8A, the SiO ₂ film 16 and, if necessary, a resist (not shown) covering the formation region of the PMOS type transistor are used as a mask to make impurities for adjusting the threshold voltage. Ions 17 are implanted near the surface of the Si substrate 11. Then, after removing the SiO ₂ film 12, S
A SiO ₂ film 21 as a gate oxide film is formed on the surface of the Si substrate 11 surrounded by the iO ₂ film 16.

After that, a polycrystalline Si film 22 is deposited by the CVD method, and the polycrystalline Si film 2 is formed by the photolithography method.
2, a resist (not shown) is processed into a pattern of the gate electrode, and this resist is used as a mask to form the polycrystalline Si film 22.
Is etched. At this time, SiO on the impurity region 15
_{The 2} film 16 and the polycrystalline Si film 22 are partially overlapped with each other.

Next, as shown in FIG. 8B, a resist 23 is processed by a lithographic method so as to form a pattern covering the formation region of the PMOS type transistor. And this resist 2
3 and the polycrystalline Si film 22 and the SiO ₂ film 16 are used as masks to ion-implant impurities into the Si substrate 11 to form high-concentration N-type impurity regions 2 which are source regions and drain regions.
4 and 25 are formed. Then, if the resist 23 is removed, this one conventional example shown in FIG. 5 is formed.

In the conventional example manufactured as described above, since the depletion layer from the impurity region 25 which is the drain region extends in the impurity region 15 having a relatively low concentration, this impurity region 15 is the drain of the channel region. The offset drain region serves to relax the electric field at the end on the region side and improve the drain breakdown voltage.

[0010]

However, in the above-mentioned conventional example, as shown in FIG.
Since the range of the impurity region 15 is defined by patterning No. 4, the length of the low concentration impurity region 15 cannot be made shorter than the minimum processing width due to the limit of photolithography. Therefore, in this conventional example, the impurity region 1
Therefore, it was difficult to obtain a high current driving ability.

[0011]

According to another aspect of the present invention, there is provided a field effect high breakdown voltage transistor, wherein an offset drain region and a field insulating film on the offset drain region are provided on a semiconductor substrate, and the field insulating film is a gate. A part of the electrode is covered, and a drain region is provided in the semiconductor substrate on the side of the field insulating film and the gate electrode.

According to a second aspect of the present invention, there is provided a method of manufacturing a field effect type high withstand voltage transistor, which comprises a step of forming an offset drain region and a field insulating film on the offset drain region on a semiconductor substrate, and a part of the field insulating film. A step of forming an overlapping gate electrode on the semiconductor substrate, a step of removing a portion of the field insulating film which is not covered by the gate electrode, and a step of removing the portion,
Forming a drain region on the semiconductor substrate using the gate electrode as a mask.

[0013]

In the field effect type high withstand voltage transistor and the method of manufacturing the same according to the present invention, the length of the offset drain region is set to the overlapping length of the field insulating film and the gate electrode.

Therefore, even if the field insulating film is initially formed to have a width equal to or larger than the minimum processing width, if the gate electrode is superposed on the field insulating film with a length shorter than the minimum processing width, the field insulating film can be formed. By removing the portion not covered with the gate electrode after that, the length of the offset drain region can be made shorter than the minimum processing width.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to an NMOS type high breakdown voltage transistor included in a CMOS type semiconductor device will be described below with reference to FIGS. FIG.
Shows the NMOS type high breakdown voltage transistor of this embodiment. In order to manufacture this example, as shown in FIG.
A SiO ₂ film 32 is formed on the surface of a Si substrate 31 having a P type or P well by thermal oxidation, and a SiN film 33 is deposited on the SiO ₂ film 32 by a CVD method or the like.

Next, as shown in FIG. 3A, a resist 3 having the same pattern as the resist 14 in the above-mentioned conventional example.
4 is formed on the SiN film 33 by photolithography,
The SiN film 33 is etched using the resist 34 as a mask.

Next, as shown in FIG. 3B, the resist 3
4 is removed, and a resist (not shown) having a pattern having an opening only on the portion where the drain region of the NMOS high withstand voltage transistor is to be formed and the portion in the vicinity thereof is formed by photolithography. Then, using this resist as a mask, impurities are ion-implanted into the Si substrate 31 to form a relatively low concentration N-type impurity region 35.

After that, the resist is removed and the SiN film 33 is formed.
Is used as an anti-oxidation mask for thermal oxidation, thermal diffusion, etc.
A SiO ₂ film 36 having a film thickness of about 500 nm is formed in a portion where the N film 33 is not provided, and the impurities in the impurity region 35 are activated. Then, the SiN film 33 is removed by etching or the like.

Next, as shown in FIG. 4A, the SiO ₂ film 36 and, if necessary, a resist (not shown) covering the formation region of the PMOS type transistor are used as a mask, and impurities for threshold voltage adjustment are used. 37 is ion-implanted near the surface of the Si substrate 31. Then, after removing the SiO ₂ film 32, S
A SiO ₂ film 41 as a gate oxide film is formed on the surface of the Si substrate 31 surrounded by the iO ₂ film 36.

Then, a polycrystalline Si film 42 is deposited by the CVD method, and the polycrystalline Si film 4 is formed by the photolithography method.
2, a resist (not shown) is processed into a pattern of a gate electrode, and the resist is used as a mask to form the polycrystalline Si film 42.
Is etched. At this time, SiO on the impurity region 35
_{The 2} film 36 and the polycrystalline Si film 42 are partially overlapped with each other.

Next, as shown in FIG. 4B, a resist 43 is processed by a lithographic method into a pattern having an opening 43a only in the formation region of the NMOS high withstand voltage transistor, and the resist 43 and the polycrystalline Si film are processed. The SiO ₂ film 36 is etched using 42 and 42 as a mask.

Then, the resist 43 and the polycrystalline Si film 42
Impurities are ion-implanted into the Si substrate 31 by using the and as masks to form high-concentration N-type impurity regions 44 and 45 which are source and drain regions. Then resist 4
If 3 is removed, the present embodiment shown in FIG. 1 is formed.

In the present embodiment manufactured as described above, as is apparent from FIG. 1, the length in which the SiO ₂ film 36 and the polycrystalline Si film 42 are overlapped is the length of the offset drain region. However, the overlapping length can be shorter than the minimum processing width. Therefore, it is possible to increase the drain breakdown voltage by the impurity region 35, reduce the parasitic resistance caused by the impurity region 35, and improve both the reliability and the current driving capability.

In the above embodiment, as described above, in the step of FIG. 4B, the SiO ₂ film 36 is selectively etched, and the portion of the Si substrate 31 whose surface is exposed by this etching is exposed. An impurity region 45 is formed as a drain region.

Therefore, in this embodiment, the pattern of the resist 34 formed in the step of FIG. 3A is made the same as the pattern of the resist 14 formed in the step of FIG. However, it is not always necessary to provide the resist 34 with a pattern portion corresponding to the element active region for forming the impurity region 25 as the drain region in the conventional example.

[0026]

In the field effect type high withstand voltage transistor and the manufacturing method thereof according to the present invention, since the length of the offset drain region can be made shorter than the minimum processing width, the drain withstand voltage can be increased by the offset drain region. The parasitic resistance caused by the offset drain region can be reduced. Therefore, it is possible to provide a field effect type high breakdown voltage transistor having high reliability and high current driving capability.

[Brief description of drawings]

FIG. 1 is a side sectional view of an NMOS high breakdown voltage transistor according to an embodiment of the present invention.

FIG. 2 is a side sectional view showing a first step of an example.

FIG. 3 is a side sectional view sequentially showing a step following FIG.

FIG. 4 is a side sectional view sequentially showing a step following FIG.

FIG. 5 is a side sectional view of an NMOS type high breakdown voltage transistor according to a conventional example of the present invention.

FIG. 6 is a side sectional view showing a first step of a conventional example.

FIG. 7 is a side sectional view sequentially showing a step following FIG.

FIG. 8 is a side sectional view sequentially showing a step following FIG.

[Explanation of symbols]

31 Si substrate 35 Impurity region 36 SiO ₂ film 42 Polycrystalline Si film 45 Impurity region

Claims (2)

[Claims] 1. An offset drain region and a field insulating film on the offset drain region are provided on a semiconductor substrate, a part of a gate electrode covers the field insulating film, and the field insulating film and the gate. A field effect type high breakdown voltage transistor, characterized in that a drain region is provided on the semiconductor substrate on the side of an electrode. 2. A step of forming an offset drain region and a field insulating film on the offset drain region on a semiconductor substrate, and a step of forming a gate electrode partially overlapping the field insulating film on the semiconductor substrate. And a step of removing a portion of the field insulating film which is not covered with the gate electrode, and a step of forming a drain region in the semiconductor substrate after the removal using the gate electrode as a mask. A method of manufacturing a field-effect high-voltage transistor, comprising: