KR100206130B1 - Method of fabricating cmos semiconductor device - Google Patents
Method of fabricating cmos semiconductor device Download PDFInfo
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- KR100206130B1 KR100206130B1 KR1019960038051A KR19960038051A KR100206130B1 KR 100206130 B1 KR100206130 B1 KR 100206130B1 KR 1019960038051 A KR1019960038051 A KR 1019960038051A KR 19960038051 A KR19960038051 A KR 19960038051A KR 100206130 B1 KR100206130 B1 KR 100206130B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
복잡한 공정 적용없이도 핫-캐리어 효과를 감소시킬 수 있도록 한 씨모스 반도체 장치 제조방법이 개시된다. 이를 구현하기 위하여 본 발명에서는, 게이트 산화막이 구비된 제2도전형의 반도체 기판 상에 제1도전형의 고농도 불순물이 도핑된 제1폴리실리콘막과 실리콘질화막을 순착적으로 형성하는 단계와; 게이트 폴리 형성부를 한정하는 마스크를 이용하여 실리콘질화막을 선택식각하여 제1폴리실리콘막의 표면이 소정 부분 노출되도록 개구부를 형성하는 단계와; 실리콘질화막내의 개구부 측벽에 산화막 재질의 스페이서를 형성하는 단계와; 개구부 내에 제1도전형의 고농도 불순물이 도핑된 제2폴리실리콘막과 실리사이드막이 순차 적층된 구조의 게이트 폴리를 형성하는 단계와; 실리콘질화막을 제거하고, 상기 기판상으로 제1도전형의 고농도 불순물을 이온주이한 후 스페이서를 제거하고, 상기 기판 상으로 제1도전형의 저농도 불순물을 이온주입하여 LDD를 갖는 소오스/드레인 영역을 형성하는 단계; 및 상기 결과물 상에 산화막을 형성하고, 게이트 산화막의 표면이 노출될 때까지 이를 이방성 건식식각하여 게이트 폴리의 양 측벽에 스페이서를 형성하는 단계로 이루어진 씨모스 반도체 장치 제조방법이 제공된다.Disclosed is a method of manufacturing a CMOS semiconductor device capable of reducing a hot-carrier effect without applying a complicated process. In order to achieve this, the present invention provides a method of manufacturing a semiconductor device, comprising: sequentially forming a first polysilicon film doped with a high-concentration impurity of a first conductivity type and a silicon nitride film on a second conductive semiconductor substrate provided with a gate oxide film; Selectively etching the silicon nitride film using a mask defining a gate poly forming portion to form openings so that a surface of the first polysilicon film is partially exposed; Forming a spacer of an oxide film on a sidewall of the opening in the silicon nitride film; Forming a gate poly having a structure in which a second polysilicon film doped with a high-concentration impurity of the first conductivity type and a silicide film are sequentially stacked in the opening; Removing the silicon nitride film, ion-concentrating the first conductivity type high-concentration impurity on the substrate, removing the spacer, and ion-implanting the low-concentration impurity of the first conductivity type onto the substrate to form a source / ; Forming an oxide film on the resultant product, and anisotropically dry etching the oxide film to expose a surface of the gate oxide film, thereby forming spacers on both side walls of the gate poly.
Description
본 발명은 씨모스(CMOS) 반도체 장치 제조방법에 관한 것으로, 보다 상세하게는 반도체 장치의 고집적화가 진행됨에 따라 증가되고 있는 핫-캐리어(hot carrier) 효과를 효과적으로 감소시킬 수 있도록 한 인버스 트랜지스터 엘디디(Inverse Transistor Lightly Doped Drain : ITLDD) CMOS 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor device manufacturing method, and more particularly, to a method of manufacturing a CMOS semiconductor device, (Inverse Transistor Lightly Doped Drain: ITLDD) CMOS semiconductor device.
반도체 장치가 고집적화됨에 따라 CMOS의 크기 또한 작아지게 되어 미론(㎛)급 채널 길이가 이미 보편화 되었고, 최근에는 하프(half) 미크론급 또는 쿼터(quarter) 미크론급 크기의 채널을 갖는 CMOS 소자까지도 등장하고 있다.As the semiconductor device has become highly integrated, the size of the CMOS becomes smaller, so that the channel length of the micrometer (탆) has already become common, and recently, a CMOS device having a half micron or quarter micron- have.
이와 같이 채널 길이가 작아짐에 따라 CMOS 소자는 제1도에 도시된 바와 같이 소스/드레인 영역(50)(50a), (52)(52a)과 각 게이트 폴리(40)를 이루는 제1폴리실리콘층(42) 사이에 존재하는 과도한 불순물로 인하여 소자 구동시 핫-캐리어 효과가 발생하게 되었다. 특히 쇼트-채널인 엔모스(NMOS) 소자는 시간의 흐름에 따라 채널 영역에 걸리는 전기장의 크기가 커져 문턱 전압이 증가하고 드레인/소오스 영역 간의 전류가 감소하여, 결국 소자의 특성이 저하되는 현상까지도 야기되게 되었다. 제1도에서 미설명 부호 10은 기판을, 20은 p웰을, 22는 n웰을, 30은 소자분리 산화막을, 42와 44는 게이트 폴리(40)를 구성하는 폴리실리콘막을, 70은 절연막을, 80, 80a 그리고 82, 82a는 각각 전극을 나타낸다.As the channel length is reduced, the CMOS device is formed with the source / drain regions 50, 50a, 52, and 52a and the first polysilicon layer (42), the hot-carrier effect occurs when the device is driven. Particularly, a short-channel in-NMOS (NMOS) device has a problem in that the electric field applied to the channel region increases with time and the threshold voltage increases and the current between the drain and source regions decreases, . In FIG. 1, reference numeral 10 denotes a substrate, 20 denotes a p-well, 22 denotes an n-well, 30 denotes a device isolation oxide film, 42 and 44 denote polysilicon films constituting the gate poly 40, And reference numerals 80, 80a, 82, and 82a denote electrodes, respectively.
따라서 최근에는 상기 단점을 해결한 것으로, LDD(Lightly Doped Drain) 구조나 게이트 오버랩 LDD(Gate Overlapped LDD : GOLD) 구조 혹은 ITLDD 구조등과 같은 형태의 여러 종류의 소자가 제안되어 사용되고 있으나, 이들 또한 그 제조 공정이 매우 복잡하다.Therefore, recently, many kinds of devices such as LDD (Lightly Doped Drain) structure, gate overlap LDD (GOLD) structure or ITLDD structure have been proposed and used, The manufacturing process is very complicated.
이에 본 발명의 목적은 복잡한 공정 적용없이도 씨모스의 핫-캐리어 효과를 감소시킬 수 있도록 한 씨모스 반도체 장치 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a CMOS semiconductor device capable of reducing the hot-carrier effect of CMOS without using complicated processes.
제1도는 종래의 씨모스 반도체 장치 구조를 도시한 단면도,FIG. 1 is a cross-sectional view showing a conventional CMOS semiconductor device structure,
제2도는 본 발명에 의한 씨모스 반도체 장치의 구조를 도시한 단면도.FIG. 2 is a cross-sectional view showing a structure of a CMOS semiconductor device according to the present invention. FIG.
제3도 내지 제10도는 제2도에 제시된 씨모스 반도체 장치의 제조방법을 도시한 공정수순도이다.FIGS. 3 to 10 are process flow charts showing the method of manufacturing the CMOS semiconductor device shown in FIG. 2. FIG.
상기 목적을 달성하기 위하여 본 발명에서는, 제1 및 제2도전형 웰이 구비된 반도체 기판 상의 비활성영역에 소자분리 산화막을 형성하고, 활성영역에 게이트 산화막을 형성하는 제1단계와; 상기 결과물 전면에 제1도전형 고농도 불순물이 도핑된 제1폴리실리콘막을 형성하고, 그 위에 실리콘질화막을 형성하는 제2단계와; 게이트 폴리 형성부를 한정하는 마스크를 이용하여 상기 실리콘질화막을 선택식각하여 상기 제1폴리실리콘막의 표면이 소정 부분 노출되도록 상기 실리콘질화막 내에 개구부를 형성하는 제3단계와; 상기 실리콘질화막 내의 개구부 측벽에 산화막 재질의 스페이서를 형성하는 제4단계와; 상기 개구부 내에 제1도전형의 고농도 불순물이 도핑된 제2폴리실리콘막과 실리사이드막이 순차 적층된 구조의 게이트 폴리를 형성하는 제5단계와; 상기 실리콘질화막을 제거하고, 상기 웰에 주입된 불순물과 다른 도전형의 고농도 불순물을 상기 기판 상으로 이온 주입하는 제6단계와; 상기 스페이서 제거후 제6단계에서 이온주입된 상기 고농도 불순물과 동일 타입의 저농도 불순물을 상기 기판 상으로 이온주입하여 LDD를 갖는 소오스/드레인 영역을 형성하는 제7단계; 및 상기 결과물 상에 산화막을 형성하고, 상기 게이트 산화막의 표면이 노출될 때까지 이를 이방성 건식식각하여 상기 게이트 폴리의 양 측벽에 스페이서를 형성하는 제8단계로 이루어진 써모스 반도체 장치 제조방법이 제공된다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a first step of forming a device isolation oxide film in an inactive region on a semiconductor substrate having first and second conductivity type wells and forming a gate oxide film in an active region; A second step of forming a first polysilicon film doped with a first conductive type high-concentration impurity on the entire surface of the resultant structure, and forming a silicon nitride film thereon; A third step of selectively etching the silicon nitride film using a mask defining a gate poly forming portion to form an opening in the silicon nitride film so that a surface of the first polysilicon film is exposed at a predetermined portion; A fourth step of forming a spacer of an oxide film on a sidewall of the opening in the silicon nitride film; A fifth step of forming a gate poly having a structure in which a second polysilicon film doped with a high-concentration impurity of the first conductivity type and a silicide film are sequentially stacked in the opening; A sixth step of removing the silicon nitride film and ion-implanting a high-concentration impurity of a conductivity type different from that of the impurity implanted into the well, onto the substrate; A seventh step of forming a source / drain region having an LDD by ion-implanting a low-concentration impurity of the same type as the high-concentration impurity ion-implanted in the sixth step after removing the spacer, onto the substrate; And an eighth step of forming an oxide film on the resultant product and forming an spacer on both side walls of the gate poly via anisotropic dry etching until the surface of the gate oxide film is exposed.
상기 공정을 적용하여 씨모스 반도체 장치를 제조할 경우, 종래 요구되던 복잡한 공정 적용없이도 소오스/드레인 영역의 LDD가 게이트 폴리 하단의 제1폴리실리콘막에 의해 덮혀지므로 간단하게 핫 캐리어 효과를 감소시킬 수 있게 된다.In the case of manufacturing a CMOS semiconductor device by the above process, the LDD of the source / drain region is covered with the first polysilicon film at the bottom of the gate poly layer without the complicated process, which is conventionally required, so that the hot carrier effect can be simply reduced .
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에서 제안된 씨모스 반도체 장치의 구조를 도시한 단면도를 나타낸 것으로, 제3도 내지 제11도에는 제2도에 제시된 반도체 장치의 구체적인 제조 방법을 도시한 공정수순도가 제시되어 있다.FIG. 2 is a cross-sectional view showing the structure of a CMOS semiconductor device proposed in the present invention. FIGS. 3 to 11 show a process flow chart showing a specific manufacturing method of the semiconductor device shown in FIG. 2 have.
상기 공정수순도를 참조하여 그 제조방법을 제8단계로 구분하여 살펴보면 다음과 같다.The manufacturing method will be described in the eighth step with reference to the above process flow chart.
제1단계로서, 제3도에 도시된 바와 같이 통상의 불순물 이온주입 공정을 통해 반도체 기판(예컨대, 실리콘 기판)(10) 내의 표면 근방에 p웰(20)과 n웰(22)을 각각 형성한 후, NMOS와 PMOS의 활성영역과 비활성영역을 구분하기 위하여 로커스 공정을 이용하여 기판(10) 상의 비활성영역에만 선택적으로 소자분리 산화막(30)을 형성한다. 이어, 열산화 공정을 이용하여 상기 결과물 상에 150~200Å 두께의 게이트 산화막(32)을 형성하고, 그 위에 고농도 n형 불순물이 도핑된 제1폴리실리콘막(42)을 400`500Å 두께로 형성한 다음, 상기 제1폴리실리콘막(42) 상에 4000~5000Å 두께의 실리콘질화막(35)을 형성한다. 그후, 게이트 폴리 형성부를 한정하는 마스크를 이용하여 실리콘질화막(35)을 선택식각하여, p웰(20)과 n웰(22) 상의 제1폴리실리콘막(42) 표면이 소정 부분 노출되도록 실리콘질화막(35) 내에 개구부에 형성하고, 실리콘질화막(35) 내의 개구부를 통해 각 웰(20), (22)의 표면 근방에 채널 이논(예컨대, Br)을 주입한다.As a first step, a p-well 20 and an n-well 22 are formed in the vicinity of the surface in a semiconductor substrate (for example, a silicon substrate) 10 through a normal impurity ion implantation process as shown in FIG. After that, the device isolation oxide film 30 is selectively formed only in the inactive regions on the substrate 10 by using the locus process in order to distinguish the active region and the inactive region of the NMOS and the PMOS. Next, a gate oxide film 32 having a thickness of 150-200 Å is formed on the resultant using a thermal oxidation process, and a first polysilicon film 42 doped with a high concentration n-type impurity is formed thereon to a thickness of 400 Å Then, a silicon nitride film 35 having a thickness of 4000 to 5000 Å is formed on the first polysilicon film 42. Thereafter, the silicon nitride film 35 is selectively etched by using a mask defining the gate poly forming portion to form the silicon nitride film 35 so that the surface of the first polysilicon film 42 on the p-well 20 and the n- (For example, Br) is implanted in the vicinity of the surface of each of the wells 20 and 22 through the opening in the silicon nitride film 35. Next, as shown in FIG.
이와 같이 채널이 형성될 부분에만 선택적으로 Br을 이온주입한 것은 후속 공정 진행시(예컨대, LDD를 갖는 소오스/드레인 영역 형성시)상기 Br이 소오스/드레인 영역의 LDD에 주입되어져 전자 이동도를 감소시키는 것을 막기 위함이다.The selective implantation of Br into only the portion where the channel is to be formed is performed when the Br is injected into the LDD of the source / drain region (for example, when the source / drain region having the LDD is formed) This is to prevent them from doing so.
제2단계로서, 제4도에 도시된 바와 같이 상기 결과물 전면에 LTO 재질의 산화막을 형성하고, 이를 이방성 건식식각하여 실리콘질화막(35)의 내의 개구부 양측벽에 스페이서(48)를 형성한다.As a second step, as shown in FIG. 4, an oxide film of an LTO material is formed on the entire surface of the resultant, and anisotropic dry etching is performed to form spacers 48 on both sides of the openings in the silicon nitride film 35.
제3단계로서, 제5도에 도시된 바와 같이 상기 개구부를 포함한 실리콘질화막(35) 상에 고농도 n형 불순물이 도핑된 제2폴리실리콘막(44)를 7000~10000Å의 두께로 형성하고, 상기 개구부 상단의 스페이서(48)가 소정 부분 노출되도록 이를 에치백하여 상기 개구부 내에 제2폴리실리콘막(44)을 매립한 다음, 상기 제2폴리실리콘막(44) 상에만 선택적으로 실리사이드막(46)을 형성한다. 그 결과, 상기 개구부 내에 제2폴리실리콘막(44)과 실리사이드막(46)이 적층된 구조의 게이트 폴리(40a)가 형성된다.5, a second polysilicon film 44 doped with a high concentration n-type impurity is formed on the silicon nitride film 35 including the opening to a thickness of 7000 to 10000 Å, The second polysilicon film 44 is buried in the opening and then the silicide film 46 is selectively selectively formed only on the second polysilicon film 44. Then, . As a result, a gate poly 40a having a structure in which the second polysilicon film 44 and the silicide film 46 are stacked in the opening is formed.
제4단계로서, 제6도에 도시된 바와 같이 실리콘질화막(35)을 제거하고, 상기 결과물 상에 제1포토레지스트막(60)을 전면 도포한 다음, NMOS 형성부(p웰(20)이 형성되어 있는 부분)가 노출되도록 이를 선택식각하고, 식각처리된 제1포토레지스트막(60)을 마스크로 이용하여 기판 상으로 고농도 n형 불순물을 이온주입하여 p웰 (20)의 표면 근방에 소오스/드레인 영역(50), (50a)으로 사용되어질 고농도 n형 불순물 주입 영역을 형성한다.6, the silicon nitride film 35 is removed, the first photoresist film 60 is coated on the resultant product, and then the NMOS forming portion (the p-well 20) And a high-concentration n-type impurity is ion-implanted into the substrate using the first photoresist film 60 as an etching mask to form a source region in the vicinity of the surface of the p- / Drain regions 50 and 50a are formed.
제5단계로서, 제7도에 도시된 바와 같이 스페이서(48)를 제거하고, 기판 상으로 저농도 n형 불순물을 이온주입하여, 상기 게이트 폴리(40a) 양 에지측의 p웰(20) 내부에 LDD(ℓ)를 갖는 소오스/드레인 영역(50), (50a)을 형성한다. 이때 LDD(ℓ)의 폭은 스페이서(48)의 폭에 의해 조절되며, 이 경우 한번의 사진공정에 의해 엔모스 영역에 LDD(ℓ)를 갖는 소오스/드레인 영역(50)(50a) 이 형성되므로 종래에 비해 공정 단순화를 이룰 수 있게 된다.As a fifth step, as shown in FIG. 7, the spacers 48 are removed, and low-concentration n-type impurities are ion-implanted on the substrate to form the gate pores 40a inside the p- And source / drain regions 50 and 50a having LDD (l) are formed. At this time, the width of the LDD (l) is controlled by the width of the spacer 48. In this case, the source / drain regions 50 and 50a having LDD (l) are formed in the emmos region by a single photolithography process It is possible to simplify the process as compared with the conventional method.
제6단계로서, 제8도에 도시된 바와 같이 제1포토레지스트막(60)을 제거하고, 상기 결과물 상에 제2포토레지스트막(62)을 전면 도포한 다음, PMOS 형성부(n웰(22)이 형성되어 있는 부분)가 노출되도록 이를 선택식각하고, 식각처리된 제2포토레지스트막(62)을 마스크로 이용하여 기판 상으로 고농도 p형 불순물을 이온주입하여 n웰(22)의 표면 근방에 소오스/드레인 영역(52), (52a)으로 사용되어질 고농도 p형 불순물 주입 영역을 형성한다.As a sixth step, the first photoresist film 60 is removed, the second photoresist film 62 is coated on the resultant as shown in FIG. 8, and then a PMOS forming portion (n-well 22) are formed on the surface of the n-type well 22, and then the high-concentration p-type impurity is ion-implanted onto the substrate using the etched second photoresist film 62 as a mask, Concentration p-type impurity implantation region to be used as the source / drain regions 52 and 52a.
제7단계로서, 제9도에 도시된 바와 같이 스페이서(48)를 제거하고, 기판 상으로 저농도 p형 불순물을 이온주입하여, 상기 게이트 폴리(40a) 양 에지측의 n웰(22) 내부에 LDD(ℓ)를 갖는 소오스/드레인 영역(52), (52a)을 형성한다.In the seventh step, as shown in FIG. 9, the spacers 48 are removed, and lightly doped p-type impurities are ion-implanted into the n-type well 22 on both edge sides of the gate poly 40a And source / drain regions 52 and 52a having LDD (l) are formed.
제8단계로서, 제10도에 도시된 바와 같이 제2포토레지스트막(62)을 제거하고, 그 위에 LTO 재질의 산화막을 전면 증착한 다음, 게이트 절연막(32)의 표면이 노출될 때까지 이를 이방성 건식식각하여 게이트 폴리(40a)의 양 측벽에 스페이서(48a)를 형성한다. 이어, 상기 결과물 전면에 절연막(70)을 형성하고, 소오스/드레인 영역(50), (50a), (52), (52a) 의 표면이 소정 부분 노출되도록 상기 절연막(70)과 게이트 절연막(32)을 소정 부분 식각하여 콘택 홀을 형성한 다음, 금속막 증착 및 식각 공정을 통해 소오스/드레인 영역과 접속되는 전극(80), (80a), (82), (82a) 을 형성해 주므로써, 본 공정 진행을 완료한다.10, the second photoresist film 62 is removed, an oxide film of an LTO material is entirely deposited thereon, and then the surface of the gate insulating film 32 is exposed Anisotropic dry etching is performed to form spacers 48a on both side walls of the gate poly 40a. Next, an insulating film 70 is formed on the entire surface of the resultant product, and the insulating film 70 and the gate insulating film 32 (see FIG. 2) are formed so that the surfaces of the source / drain regions 50, 50a, 52, ) 80a, 82a, and 82a connected to the source / drain regions through a metal film deposition and etching process, thereby forming the contact holes 82a, The process is completed.
그 결과, LDD(ℓ)상부에 제1폴리실리콘막(42)이 덮혀 있는 구조의 씨모스 반도체 장치가 완성된다.As a result, a CMOS semiconductor device having a structure in which the first polysilicon film 42 is covered on the LDD (l) is completed.
이와 같이 씨모스 반도체 장치를 제조할 경우, NMOS 형성부의 LDD(ℓ)를 갖는 소오스/드레인 영역(50), (50a) 형성시나 혹은 PMOS 형성부의 LDD(ℓ)를 갖는 소오스/드레인 영역(52), (52a) 형성시 개별적으로 각각 한번의 사진공정만이 요구되므로 종래에 비해 공정 단순화를 이룰 수 있게 되고, LDD(ℓ) 상부에 제1폴리실리콘막(42)이 덮혀져 있으므로 핫-캐리어 효과 또한 줄일 수 있게 된다.When the CMOS semiconductor device is manufactured, the source / drain region 52 having the LDD (l) of the NMOS forming portion, the source / drain region 52 having the LDD (l) of the PMOS forming portion, (52a) are formed, only a single photolithography process is required. Therefore, the process can be simplified compared to the conventional method. Since the first polysilicon film (42) is covered on the LDD It is also possible to reduce it.
이상에서 살펴본 바와 같이 본 발명에 의하면, 복잡한 공정 적용없이도 게이트 폴리 하단에 놓여져, 게이트 폴리의 역할을 하는 제1폴리실리콘막이 LDD를 덮도록 소자 제조가 이루어지므로, 종래에 비해 공정 단순화를 이룰 수 있게 될 뿐 아니라 핫-캐리어 효과에 대한 내성을 강화시킬 수 있게 된다.As described above, according to the present invention, since the device is manufactured so that the first polysilicon film, which serves as the gate poly, is placed on the bottom of the gate poly without complicated processes, so that the process can be simplified But also to enhance resistance to hot-carrier effects.
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